[RISC-V] add more tests for analyzeBranch with zero-comparison. NFC

[inclyc]

Summary

Functions of branch analysis firstly introduced in
https://reviews.llvm.org/D40808, This patch add more tests in
analyze-branch.ll which have zero-comparison instruction,
in this case beqz, because this instruction has one less operand
than previously tested.

Signed-off-by: YingChi Long <[e-mail]>

[inclyc]

llvm/test/CodeGen/RISCV/analyze-branch.ll

15

In previous versions, the name of this function seemed to be derived from the test file of AAarch64 (see https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/analyze-branch.ll). In order to make the meaning of this test file more concise and understandable, I changed this to beq.

[jrtc27]

Why are these tests interesting? The MC instruction doesn’t have any fewer operands, it’s still a BEQ. BEQZ is just an alias in the textual assembly.

[inclyc]

Sorry for wasting your time, I might have some misunderstanding of MC codes.

llvm/test/CodeGen/RISCV/analyze-branch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 
 ; This test checks that LLVM can do basic stripping and reapplying of branches
 ; to basic blocks.
 
 declare void @test_true()
 declare void @test_false()
 
 ; !0 corresponds to a branch being taken, !1 to not being takne.
 !0 = !{!"branch_weights", i32 64, i32 4}
 !1 = !{!"branch_weights", i32 4, i32 64}
 
-define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
-; RV32I-LABEL: test_bcc_fallthrough_taken:
+define void @test_beq_fallthrough_taken(i32 %in) nounwind {
+; RV32I-LABEL: test_beq_fallthrough_taken:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    li a1, 42
 ; RV32I-NEXT:    bne a0, a1, .LBB0_3
 ; RV32I-NEXT:  # %bb.1: # %true
 ; RV32I-NEXT:    call test_true@plt
 ; RV32I-NEXT:  .LBB0_2: # %true
true:
   call void @test_true()
   ret void
 
 false:
   call void @test_false()
   ret void
 }
 
-define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
-; RV32I-LABEL: test_bcc_fallthrough_nottaken:
+define void @test_beq_fallthrough_nottaken(i32 %in) nounwind {
+; RV32I-LABEL: test_beq_fallthrough_nottaken:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    li a1, 42
 ; RV32I-NEXT:    beq a0, a1, .LBB1_3
 ; RV32I-NEXT:  # %bb.1: # %false
 ; RV32I-NEXT:    call test_false@plt
 ; RV32I-NEXT:  .LBB1_2: # %true
true:
   call void @test_true()
   ret void
 
 false:
   call void @test_false()
   ret void
 }
 
-; TODO: how can we expand the coverage of the branch analysis functions?
+define void @test_beqz_fallthrough_taken(i32 %in) nounwind {
+; RV32I-LABEL: test_beqz_fallthrough_taken:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    bnez a0, .LBB2_3
+; RV32I-NEXT:  # %bb.1: # %true
+; RV32I-NEXT:    call test_true@plt
+; RV32I-NEXT:  .LBB2_2: # %true
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB2_3: # %false
+; RV32I-NEXT:    call test_false@plt
+; RV32I-NEXT:    j .LBB2_2
+  %tst = icmp eq i32 %in, 0
+  br i1 %tst, label %true, label %false, !prof !0
+
+; Expected layout order is: Entry, TrueBlock, FalseBlock
+
+true:
+  call void @test_true()
+  ret void
+
+false:
+  call void @test_false()
+  ret void
+}
+
+define void @test_beqz_fallthrough_nottaken(i32 %in) nounwind {
+; RV32I-LABEL: test_beqz_fallthrough_nottaken:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    beqz a0, .LBB3_3
+; RV32I-NEXT:  # %bb.1: # %false
+; RV32I-NEXT:    call test_false@plt
+; RV32I-NEXT:  .LBB3_2: # %true
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB3_3: # %true
+; RV32I-NEXT:    call test_true@plt
+; RV32I-NEXT:    j .LBB3_2
+  %tst = icmp eq i32 %in, 0
+  br i1 %tst, label %true, label %false, !prof !1
+
+; Expected layout order is: Entry, FalseBlock, TrueBlock
+
+true:
+  call void @test_true()
+  ret void
+
+false:
+  call void @test_false()
+  ret void
+}