[LLDB][RISCV] Add riscv register definition and read/write

[Emmmer]

Summary

This patch is based on the minimal extract of D128250.

What is implemented:

• Use the same register layout as Linux kernel and mock read/write for x0 register (the always zero register).
• Refactor some duplicate code, and delete unused register definitions.

[JDevlieghere]

lldb/source/Utility/ArchSpec.cpp

1390–1395

I don't think this is needed. The case where the two cores are identical is already covered by line 1084. This would be for something like eCore_riscv32 if that were a thing.

[DavidSpickett]

lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp

1347

Why is this only needed for PECOFF? (maybe it is the only one that lists them like this)

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp

25

This can be sys/uio.h I'm pretty sure.

I know the other NativeRegisterContexts include socket.h but I'm looking at changing those.

[Emmmer]

Why is this only needed for PECOFF? (maybe it is the only one that lists them like this)

At first, I tracked a bug from LLDBServerTests and thought that GetArchitecture() returned a wrong match, so I added case llvm::COFF::IMAGE_FILE_MACHINE_RISCV64 to the function (there is indeed an IMAGE_FILE_MACHINE_RISCV64 in COFF.h, so I regarded it was a global architecture judgment ).

Later, I found out that HostInfoBase.cpp did not add a match to riscv64, and it ran as expected after adding it.

I forgot to delete it in my local repo, sorry.

[DavidSpickett]

Please note in the commit title/description that this is adding riscv64 only.

Does this build if you don't have the rest of the changes from https://reviews.llvm.org/D128250? Or do you plan to split out more from that and have this depend on those changes.

(thanks for splitting them out though, it is easier to get through!)

[Emmmer]

case llvm::Triple::riscv64: in ArchSpec::CharIsSignedByDefault() is unnecessary as well.

[Emmmer]

In D130342#3676318, @DavidSpickett wrote:

Please note in the commit title/description that this is adding riscv64 only.

Does this build if you don't have the rest of the changes from https://reviews.llvm.org/D128250? Or do you plan to split out more from that and have this depend on those changes.

(thanks for splitting them out though, it is easier to get through!)

I try to split unrelated code as much as possible so that they are easier to check and look cleaner.

[Emmmer]

What is implemented:

• Use the same register layout as Linux kernel and mock read/write for x0 register (the always zero register).
• Take RISC-V ebreak instruction as breakpoint trap code, so our breakpoint works as expected now.
• Refactor some duplicate code.

Further work:

• RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
• Add support for RVC extension (the trap code, etc.).

[tzb99]

In D130342#3709772, @Emmmer wrote:

What is implemented:

• Use the same register layout as Linux kernel and mock read/write for x0 register (the always zero register).
• Take RISC-V ebreak instruction as breakpoint trap code, so our breakpoint works as expected now.
• Refactor some duplicate code.

Further work:

• RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
• Add support for RVC extension (the trap code, etc.).

Thank you so much for the contribution! I have few more questions. What is your qemu spec? Is it operated in the user mode or the system mode? In addition, did your cross compilation build using in-tree build or build lldb separately?

[Emmmer]

In D130342#3710122, @tzb99 wrote:

In D130342#3709772, @Emmmer wrote:

What is implemented:

• Use the same register layout as Linux kernel and mock read/write for x0 register (the always zero register).
• Take RISC-V ebreak instruction as breakpoint trap code, so our breakpoint works as expected now.
• Refactor some duplicate code.

Further work:

• RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
• Add support for RVC extension (the trap code, etc.).

Thank you so much for the contribution! I have few more questions. What is your qemu spec? Is it operated in the user mode or the system mode? In addition, did your cross compilation build using in-tree build or build lldb separately?

I'm using qemu-system 7.0.0 and in-tree cross build.

[tzb99]

In D130342#3710299, @Emmmer wrote:

In D130342#3710122, @tzb99 wrote:

In D130342#3709772, @Emmmer wrote:

What is implemented:

• Use the same register layout as Linux kernel and mock read/write for x0 register (the always zero register).
• Take RISC-V ebreak instruction as breakpoint trap code, so our breakpoint works as expected now.
• Refactor some duplicate code.

Further work:

• RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
• Add support for RVC extension (the trap code, etc.).

Thank you so much for the contribution! I have few more questions. What is your qemu spec? Is it operated in the user mode or the system mode? In addition, did your cross compilation build using in-tree build or build lldb separately?

I'm using qemu-system 7.0.0 and in-tree cross build.

I am sorry to bother you again, is the dwarf header file changed since the last diff? I noticed the title of the file is changed, and based on the observation, such change should be related to the RISCV64_DWARF_Registers.h file? Directly using the file from last diff will not compile, so I rearrange the file with dwarf_gpr naming convention, but seems like the functionality is not complete.

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

18

Do you change the name of it since last diff?

[Emmmer]

In D130342#3711534, @tzb99 wrote:

In D130342#3710299, @Emmmer wrote:

In D130342#3710122, @tzb99 wrote:

In D130342#3709772, @Emmmer wrote:

What is implemented:

• Use the same register layout as Linux kernel and mock read/write for x0 register (the always zero register).
• Take RISC-V ebreak instruction as breakpoint trap code, so our breakpoint works as expected now.
• Refactor some duplicate code.

Further work:

• RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
• Add support for RVC extension (the trap code, etc.).

Thank you so much for the contribution! I have few more questions. What is your qemu spec? Is it operated in the user mode or the system mode? In addition, did your cross compilation build using in-tree build or build lldb separately?

I'm using qemu-system 7.0.0 and in-tree cross build.

I am sorry to bother you again, is the dwarf header file changed since the last diff? I noticed the title of the file is changed, and based on the observation, such change should be related to the RISCV64_DWARF_Registers.h file? Directly using the file from last diff will not compile, so I rearrange the file with dwarf_gpr naming convention, but seems like the functionality is not complete.

RISCV64_DWARF_Registers.h has been merged to main in D130686, you may need rebase from main

[DavidSpickett]

Can "and make breakpoint work" be made into its own patch? I'd much rather see "register read and write" and "software breakpoints" in their own changes (and please differentiate in commit title/messages between hardware break and software break).

(otherwise the content seems fine just some comments on names and formatting)

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

50

clang-format will align these to the left. So I suggest adding "// clang-format off" to disable that and go with the "clang-format on" below. Then indent them as if they were normal code.

131

I check the arm64 file and it also had an orphaned "on". I fixed that in https://github.com/llvm/llvm-project/commit/552dccf311c6134c6c895328602172821e3efaed.

See comment above.

lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h

20 ↗

(On Diff #451140)

We want to keep the "riscv" tag here. It provides a sort of namespace for the enumerator otherwise overlapping names in different anonymous enums is an error.

https://godbolt.org/z/1W8P1z83T

E.g. if arm64 just used "gpr_x0" we'd get an error, so it uses "gpr_x0_arm64" to prevent that.

94 ↗

(On Diff #451140)

Why did the vector registers get removed?

[Emmmer]

Address review comments:

• Split the software breakpoint as a separate PR.
• Add _riscv suffix to register enums

About vector registers:

• Deleted as they are unused in current codebase, we can add them back if required in the future.

[DavidSpickett]

we can add them back if required in the future.

Sounds good to me. Certainly SVE for Arm required a bunch of changes, a lot easier to do it later.

This LGTM, but:

[LLDB][RISCV] Add riscv register stuff

Can we have something more specific than "stuff" :) (not that I don't use vague terms sometimes) "Add RISCV register information" ?

Just thinking that if I was a riscv user and I was looking at lldb logs I'd want to know "what did this commit enable", what works now that didn't before? And "stuff" doesn't help me there. "information" at least doesn't commit to enabling any new functionality.

[thakis]

This breaks building on windows: http://45.33.8.238/win/64255/step_4.txt

Please take a look and revert for now if it takes a while to fix.

[Emmmer]

In D130342#3715622, @thakis wrote:

This breaks building on windows: http://45.33.8.238/win/64255/step_4.txt

Please take a look and revert for now if it takes a while to fix.

Yes. This is probably because we don't have a CI configured to enable riscv target.
It should be a simple fix and it is coming, don't worry :)

[Emmmer]

In D130342#3715622, @thakis wrote:

This breaks building on windows: http://45.33.8.238/win/64255/step_4.txt

Please take a look and revert for now if it takes a while to fix.

Should be fixed after D131667

[DavidSpickett]

The error appears to be:

../../lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h(67,5): error: constant expression evaluates to -1 which cannot be narrowed to type 'uint32_t' (aka 'unsigned int') [-Wc++11-narrowing]
    DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),

So I'm not sure that patch will fix everything but let's see.

lldb/source/Host/common/HostInfoBase.cpp

   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
   case llvm::Triple::x86_64:
+  case llvm::Triple::riscv64:
     arch_64.SetTriple(triple);
     arch_32.SetTriple(triple.get32BitArchVariant());
     break;

lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp

   case llvm::COFF::IMAGE_FILE_MACHINE_ARMNT:
   case llvm::COFF::IMAGE_FILE_MACHINE_THUMB:
   case llvm::COFF::IMAGE_FILE_MACHINE_ARM64:
+  case llvm::COFF::IMAGE_FILE_MACHINE_RISCV64:
     ArchSpec arch;
     arch.SetArchitecture(eArchTypeCOFF, machine, LLDB_INVALID_CPUTYPE,
                          IsWindowsSubsystem() ? llvm::Triple::Win32

lldb/source/Plugins/Process/Linux/CMakeLists.txt

   NativeRegisterContextLinux_arm.cpp
   NativeRegisterContextLinux_arm64.cpp
   NativeRegisterContextLinux_ppc64le.cpp
+  NativeRegisterContextLinux_riscv64.cpp
   NativeRegisterContextLinux_s390x.cpp
   NativeRegisterContextLinux_x86_64.cpp
   NativeThreadLinux.cpp

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h

+//===-- NativeRegisterContextLinux_riscv64.h -------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__riscv) && __riscv_xlen == 64
+
+#ifndef lldb_NativeRegisterContextLinux_riscv64_h
+#define lldb_NativeRegisterContextLinux_riscv64_h
+
+#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+#include <asm/ptrace.h>
+
+namespace lldb_private {
+namespace process_linux {
+
+class NativeProcessLinux;
+
+class NativeRegisterContextLinux_riscv64 : public NativeRegisterContextLinux {
+public:
+  NativeRegisterContextLinux_riscv64(
+      const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
+      std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up);
+
+  uint32_t GetRegisterSetCount() const override;
+
+  uint32_t GetUserRegisterCount() const override;
+
+  const RegisterSet *GetRegisterSet(uint32_t set_index) const override;
+
+  Status ReadRegister(const RegisterInfo *reg_info,
+                      RegisterValue &reg_value) override;
+
+  Status WriteRegister(const RegisterInfo *reg_info,
+                       const RegisterValue &reg_value) override;
+
+  Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
+
+  Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
+
+  void InvalidateAllRegisters() override;
+
+  std::vector<uint32_t>
+  GetExpeditedRegisters(ExpeditedRegs expType) const override;
+
+  bool RegisterOffsetIsDynamic() const override { return true; }
+
+protected:
+  Status ReadGPR() override;
+
+  Status WriteGPR() override;
+
+  Status ReadFPR() override;
+
+  Status WriteFPR() override;
+
+  void *GetGPRBuffer() override { return &m_gpr_riscv64; }
+
+  // GetGPRBufferSize returns sizeof riscv64 GPR ptrace buffer, it is different
+  // from GetGPRSize which returns sizeof RegisterInfoPOSIX_riscv64::GPR.
+  size_t GetGPRBufferSize() { return sizeof(m_gpr_riscv64); }
+
+  void *GetFPRBuffer() override { return &m_fpr; }
+
+  size_t GetFPRSize() override { return sizeof(m_fpr); }
+
+private:
+  bool m_gpr_is_valid;
+  bool m_fpu_is_valid;
+
+  struct user_regs_struct m_gpr_riscv64; // 64-bit general purpose registers.
+
+  RegisterInfoPOSIX_riscv64::FPR
+      m_fpr; // floating-point registers including extended register sets.
+
+  bool IsGPR(unsigned reg) const;
+
+  bool IsFPR(unsigned reg) const;
+
+  uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
+
+  RegisterInfoPOSIX_riscv64 &GetRegisterInfo() const;
+};
+
+} // namespace process_linux
+} // namespace lldb_private
+
+#endif // #ifndef lldb_NativeRegisterContextLinux_riscv64_h
+
+#endif // defined(__riscv) && __riscv_xlen == 64

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp

+//===-- NativeRegisterContextLinux_riscv64.cpp ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__riscv) && __riscv_xlen == 64
+
+#include "NativeRegisterContextLinux_riscv64.h"
+
+#include "lldb/Utility/DataBufferHeap.h"
+#include "lldb/Utility/Log.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/Utility/Status.h"
+
+#include "Plugins/Process/Linux/NativeProcessLinux.h"
+#include "Plugins/Process/Linux/Procfs.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+// System includes - They have to be included after framework includes because
+// they define some macros which collide with variable names in other modules
+#include <sys/socket.h>
+// NT_PRSTATUS and NT_FPREGSET definition
+#include <elf.h>
+
+#define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize())
+
+using namespace lldb;
+using namespace lldb_private;
+using namespace lldb_private::process_linux;
+
+std::unique_ptr<NativeRegisterContextLinux>
+NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
+    const ArchSpec &target_arch, NativeThreadLinux &native_thread) {
+  switch (target_arch.GetMachine()) {
+  case llvm::Triple::riscv64: {
+    Flags opt_regsets;
+    auto register_info_up =
+        std::make_unique<RegisterInfoPOSIX_riscv64>(target_arch, opt_regsets);
+    return std::make_unique<NativeRegisterContextLinux_riscv64>(
+        target_arch, native_thread, std::move(register_info_up));
+  }
+  default:
+    llvm_unreachable("have no register context for architecture");
+  }
+}
+
+NativeRegisterContextLinux_riscv64::NativeRegisterContextLinux_riscv64(
+    const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
+    std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up)
+    : NativeRegisterContextRegisterInfo(native_thread,
+                                        register_info_up.release()),
+      NativeRegisterContextLinux(native_thread) {
+  ::memset(&m_fpr, 0, sizeof(m_fpr));
+  ::memset(&m_gpr_riscv64, 0, sizeof(m_gpr_riscv64));
+
+  m_gpr_is_valid = false;
+  m_fpu_is_valid = false;
+}
+
+RegisterInfoPOSIX_riscv64 &
+NativeRegisterContextLinux_riscv64::GetRegisterInfo() const {
+  return static_cast<RegisterInfoPOSIX_riscv64 &>(
+      *m_register_info_interface_up);
+}
+
+uint32_t NativeRegisterContextLinux_riscv64::GetRegisterSetCount() const {
+  return GetRegisterInfo().GetRegisterSetCount();
+}
+
+const RegisterSet *
+NativeRegisterContextLinux_riscv64::GetRegisterSet(uint32_t set_index) const {
+  return GetRegisterInfo().GetRegisterSet(set_index);
+}
+
+uint32_t NativeRegisterContextLinux_riscv64::GetUserRegisterCount() const {
+  uint32_t count = 0;
+  for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index)
+    count += GetRegisterSet(set_index)->num_registers;
+  return count;
+}
+
+Status
+NativeRegisterContextLinux_riscv64::ReadRegister(const RegisterInfo *reg_info,
+                                                 RegisterValue &reg_value) {
+  Status error;
+
+  if (!reg_info) {
+    error.SetErrorString("reg_info NULL");
+    return error;
+  }
+
+  const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+
+  if (reg == LLDB_INVALID_REGNUM)
+    return Status("no lldb regnum for %s", reg_info && reg_info->name
+                                               ? reg_info->name
+                                               : "<unknown register>");
+
+  uint8_t *src = nullptr;
+  uint32_t offset = LLDB_INVALID_INDEX32;
+
+  if (IsGPR(reg)) {
+    error = ReadGPR();
+    if (error.Fail())
+      return error;
+
+    offset = reg_info->byte_offset;
+    assert(offset < GetGPRSize());
+    src = (uint8_t *)GetGPRBuffer() + offset;
+
+  } else if (IsFPR(reg)) {
+    error = ReadFPR();
+    if (error.Fail())
+      return error;
+
+    offset = CalculateFprOffset(reg_info);
+    assert(offset < GetFPRSize());
+    src = (uint8_t *)GetFPRBuffer() + offset;
+  } else
+    return Status("failed - register wasn't recognized to be a GPR or an FPR, "
+                  "write strategy unknown");
+
+  reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
+                              eByteOrderLittle, error);
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteRegister(
+    const RegisterInfo *reg_info, const RegisterValue &reg_value) {
+  Status error;
+
+  if (!reg_info)
+    return Status("reg_info NULL");
+
+  const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+
+  if (reg == LLDB_INVALID_REGNUM)
+    return Status("no lldb regnum for %s", reg_info->name != nullptr
+                                               ? reg_info->name
+                                               : "<unknown register>");
+
+  uint8_t *dst = nullptr;
+  uint32_t offset = LLDB_INVALID_INDEX32;
+
+  if (IsGPR(reg)) {
+    error = ReadGPR();
+    if (error.Fail())
+      return error;
+
+    assert(reg_info->byte_offset < GetGPRSize());
+    dst = (uint8_t *)GetGPRBuffer() + reg_info->byte_offset;
+    ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+    return WriteGPR();
+  } else if (IsFPR(reg)) {
+    error = ReadFPR();
+    if (error.Fail())
+      return error;
+
+    offset = CalculateFprOffset(reg_info);
+    assert(offset < GetFPRSize());
+    dst = (uint8_t *)GetFPRBuffer() + offset;
+    ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+    return WriteFPR();
+  }
+
+  return Status("Failed to write register value");
+}
+
+Status NativeRegisterContextLinux_riscv64::ReadAllRegisterValues(
+    lldb::WritableDataBufferSP &data_sp) {
+  Status error;
+
+  data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
+
+  error = ReadGPR();
+  if (error.Fail())
+    return error;
+
+  error = ReadFPR();
+  if (error.Fail())
+    return error;
+
+  uint8_t *dst = const_cast<uint8_t *>(data_sp->GetBytes());
+  ::memcpy(dst, GetGPRBuffer(), GetGPRSize());
+  dst += GetGPRSize();
+  ::memcpy(dst, GetFPRBuffer(), GetFPRSize());
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteAllRegisterValues(
+    const lldb::DataBufferSP &data_sp) {
+  Status error;
+
+  if (!data_sp) {
+    error.SetErrorStringWithFormat(
+        "NativeRegisterContextLinux_riscv64::%s invalid data_sp provided",
+        __FUNCTION__);
+    return error;
+  }
+
+  if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) {
+    error.SetErrorStringWithFormat(
+        "NativeRegisterContextLinux_riscv64::%s data_sp contained mismatched "
+        "data size, expected %" PRIu64 ", actual %" PRIu64,
+        __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize());
+    return error;
+  }
+
+  uint8_t *src = const_cast<uint8_t *>(data_sp->GetBytes());
+  if (src == nullptr) {
+    error.SetErrorStringWithFormat("NativeRegisterContextLinux_riscv64::%s "
+                                   "DataBuffer::GetBytes() returned a null "
+                                   "pointer",
+                                   __FUNCTION__);
+    return error;
+  }
+  ::memcpy(GetGPRBuffer(), src, GetRegisterInfoInterface().GetGPRSize());
+
+  error = WriteGPR();
+  if (error.Fail())
+    return error;
+
+  src += GetRegisterInfoInterface().GetGPRSize();
+  ::memcpy(GetFPRBuffer(), src, GetFPRSize());
+
+  error = WriteFPR();
+  if (error.Fail())
+    return error;
+
+  return error;
+}
+
+bool NativeRegisterContextLinux_riscv64::IsGPR(unsigned reg) const {
+  return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+         RegisterInfoPOSIX_riscv64::GPRegSet;
+}
+
+bool NativeRegisterContextLinux_riscv64::IsFPR(unsigned reg) const {
+  return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+         RegisterInfoPOSIX_riscv64::FPRegSet;
+}
+
+Status NativeRegisterContextLinux_riscv64::ReadGPR() {
+  Status error;
+
+  if (m_gpr_is_valid)
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetGPRBuffer();
+  ioVec.iov_len = GetGPRBufferSize();
+
+  error = ReadRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
+
+  if (error.Success())
+    m_gpr_is_valid = true;
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteGPR() {
+  Status error = ReadGPR();
+  if (error.Fail())
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetGPRBuffer();
+  ioVec.iov_len = GetGPRBufferSize();
+
+  m_gpr_is_valid = false;
+
+  return WriteRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
+}
+
+Status NativeRegisterContextLinux_riscv64::ReadFPR() {
+  Status error;
+
+  if (m_fpu_is_valid)
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetFPRBuffer();
+  ioVec.iov_len = GetFPRSize();
+
+  error = ReadRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
+
+  if (error.Success())
+    m_fpu_is_valid = true;
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteFPR() {
+  Status error = ReadFPR();
+  if (error.Fail())
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetFPRBuffer();
+  ioVec.iov_len = GetFPRSize();
+
+  m_fpu_is_valid = false;
+
+  return WriteRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
+}
+
+void NativeRegisterContextLinux_riscv64::InvalidateAllRegisters() {
+  m_gpr_is_valid = false;
+  m_fpu_is_valid = false;
+}
+
+uint32_t NativeRegisterContextLinux_riscv64::CalculateFprOffset(
+    const RegisterInfo *reg_info) const {
+  return reg_info->byte_offset - GetGPRSize();
+}
+
+std::vector<uint32_t> NativeRegisterContextLinux_riscv64::GetExpeditedRegisters(
+    ExpeditedRegs expType) const {
+  std::vector<uint32_t> expedited_reg_nums =
+      NativeRegisterContext::GetExpeditedRegisters(expType);
+
+  return expedited_reg_nums;
+}
+
+#endif // defined (__riscv) && __riscv_xlen == 64

lldb/source/Plugins/Process/Utility/CMakeLists.txt

   RegisterContextPOSIX_mips64.cpp
   RegisterContextPOSIX_powerpc.cpp
   RegisterContextPOSIX_ppc64le.cpp
+  RegisterContextPOSIX_riscv64.cpp
   RegisterContextPOSIX_s390x.cpp
   RegisterContextPOSIX_x86.cpp
   RegisterContextThreadMemory.cpp

   RegisterInfoPOSIX_arm.cpp
   RegisterInfoPOSIX_arm64.cpp
   RegisterInfoPOSIX_ppc64le.cpp
+  RegisterInfoPOSIX_riscv64.cpp
   StopInfoMachException.cpp
   ThreadMemory.cpp
 

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h

+//===-- RegisterContextPOSIX_riscv64.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
+
+#include "RegisterInfoInterface.h"
+#include "RegisterInfoPOSIX_riscv64.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Log.h"
+
+class RegisterContextPOSIX_riscv64 : public lldb_private::RegisterContext {
+public:
+  RegisterContextPOSIX_riscv64(
+      lldb_private::Thread &thread,
+      std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info);
+
+  ~RegisterContextPOSIX_riscv64() override;
+
+  void invalidate();
+
+  void InvalidateAllRegisters() override;
+
+  size_t GetRegisterCount() override;
+
+  virtual size_t GetGPRSize();
+
+  virtual unsigned GetRegisterSize(unsigned reg);
+
+  virtual unsigned GetRegisterOffset(unsigned reg);
+
+  const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
+
+  size_t GetRegisterSetCount() override;
+
+  const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
+
+protected:
+  std::unique_ptr<RegisterInfoPOSIX_riscv64> m_register_info_up;
+
+  virtual const lldb_private::RegisterInfo *GetRegisterInfo();
+
+  bool IsGPR(unsigned reg);
+
+  bool IsFPR(unsigned reg);
+
+  size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_riscv64::FPR); }
+
+  uint32_t GetRegNumFCSR() const { return m_register_info_up->GetRegNumFCSR(); }
+
+  virtual bool ReadGPR() = 0;
+  virtual bool ReadFPR() = 0;
+  virtual bool WriteGPR() = 0;
+  virtual bool WriteFPR() = 0;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp

+//===-- RegisterContextPOSIX_riscv64.cpp ------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "lldb/Target/Process.h"
+#include "lldb/Target/Target.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataBufferHeap.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/Endian.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/Utility/Scalar.h"
+#include "llvm/Support/Compiler.h"
+
+#include "RegisterContextPOSIX_riscv64.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+RegisterContextPOSIX_riscv64::RegisterContextPOSIX_riscv64(
+    lldb_private::Thread &thread,
+    std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info)
+    : lldb_private::RegisterContext(thread, 0),
+      m_register_info_up(std::move(register_info)) {}
+
+RegisterContextPOSIX_riscv64::~RegisterContextPOSIX_riscv64() = default;
+
+void RegisterContextPOSIX_riscv64::invalidate() {}
+
+void RegisterContextPOSIX_riscv64::InvalidateAllRegisters() {}
+
+size_t RegisterContextPOSIX_riscv64::GetRegisterCount() {
+  return m_register_info_up->GetRegisterCount();
+}
+
+size_t RegisterContextPOSIX_riscv64::GetGPRSize() {
+  return m_register_info_up->GetGPRSize();
+}
+
+unsigned RegisterContextPOSIX_riscv64::GetRegisterSize(unsigned int reg) {
+  return m_register_info_up->GetRegisterInfo()[reg].byte_size;
+}
+
+unsigned RegisterContextPOSIX_riscv64::GetRegisterOffset(unsigned int reg) {
+  return m_register_info_up->GetRegisterInfo()[reg].byte_offset;
+}
+
+const lldb_private::RegisterInfo *
+RegisterContextPOSIX_riscv64::GetRegisterInfoAtIndex(size_t reg) {
+  if (reg < GetRegisterCount())
+    return &GetRegisterInfo()[reg];
+
+  return nullptr;
+}
+
+size_t RegisterContextPOSIX_riscv64::GetRegisterSetCount() {
+  return m_register_info_up->GetRegisterCount();
+}
+
+const lldb_private::RegisterSet *
+RegisterContextPOSIX_riscv64::GetRegisterSet(size_t set) {
+  return m_register_info_up->GetRegisterSet(set);
+}
+
+const lldb_private::RegisterInfo *
+RegisterContextPOSIX_riscv64::GetRegisterInfo() {
+  return m_register_info_up->GetRegisterInfo();
+}
+
+bool RegisterContextPOSIX_riscv64::IsGPR(unsigned int reg) {
+  return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+         RegisterInfoPOSIX_riscv64::GPRegSet;
+}
+
+bool RegisterContextPOSIX_riscv64::IsFPR(unsigned int reg) {
+  return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+         RegisterInfoPOSIX_riscv64::FPRegSet;
+}

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h

+//===-- RegisterInfoPOSIX_riscv64.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV64_H
+
+#include "RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+#include <map>
+
+class RegisterInfoPOSIX_riscv64
+    : public lldb_private::RegisterInfoAndSetInterface {
+public:
+  enum { GPRegSet = 0, FPRegSet };
+
+  struct GPR {
+    uint64_t x[32];
+    uint64_t pc;
+  };
+
+  struct FPR {
+    uint64_t f[32];
+    uint32_t fflags;
+    uint32_t frm;
+    uint32_t fcsr;
+  };
+
+  RegisterInfoPOSIX_riscv64(const lldb_private::ArchSpec &target_arch,
+                            lldb_private::Flags flags);
+
+  size_t GetGPRSize() const override;
+
+  size_t GetFPRSize() const override;
+
+  const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+  uint32_t GetRegisterCount() const override;
+
+  const lldb_private::RegisterSet *
+  GetRegisterSet(size_t reg_set) const override;
+
+  size_t GetRegisterSetCount() const override;
+
+  size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+  uint32_t GetRegNumFCSR() const;
+
+private:
+  const lldb_private::RegisterInfo *m_register_info_p;
+  uint32_t m_register_info_count;
+};
+
+#endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp

+//===-- RegisterInfoPOSIX_riscv64.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <cassert>
+#include <lldb/Utility/Flags.h>
+#include <stddef.h>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "RegisterInfoPOSIX_riscv64.h"
+
+#define GPR_OFFSET(idx) ((idx)*8)
+#define GPR_OFFSET_NAME(reg)                                                   \
+  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_riscv64::GPR, reg))
+
+#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoPOSIX_riscv64::GPR))
+#define FPR_OFFSET_NAME(reg)                                                   \
+  (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_riscv64::FPR, reg) +              \
+   sizeof(RegisterInfoPOSIX_riscv64::GPR))
+
+#define REG_CONTEXT_SIZE                                                       \
+  (sizeof(RegisterInfoPOSIX_riscv64::GPR) +                                    \
+   sizeof(RegisterInfoPOSIX_riscv64::FPR))
+
+#define DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+#include "RegisterInfos_riscv64.h"
+#undef DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+
+static const lldb_private::RegisterInfo *
+GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+  switch (target_arch.GetMachine()) {
+  case llvm::Triple::riscv64:
+    return g_register_infos_riscv64_le;
+  default:
+    assert(false && "Unhandled target architecture.");
+    return nullptr;
+  }
+}
+
+// Number of register sets provided by this context.
+enum {
+  k_num_gpr_registers = gpr_pc - gpr_x0 + 1,
+  k_num_fpr_registers = fpr_fcsr - fpr_f0 + 1,
+  k_num_register_sets = 2
+};
+
+// RISC-V64 general purpose registers.
+static const uint32_t g_gpr_regnums_riscv64[] = {gpr_x0,  gpr_ra,
+                                                 gpr_sp,  gpr_x3,
+                                                 gpr_x4,  gpr_x5,
+                                                 gpr_x6,  gpr_x7,
+                                                 gpr_fp,  gpr_x9,
+                                                 gpr_x10, gpr_x11,
+                                                 gpr_x12, gpr_x13,
+                                                 gpr_x14, gpr_x15,
+                                                 gpr_x16, gpr_x17,
+                                                 gpr_x18, gpr_x19,
+                                                 gpr_x20, gpr_x21,
+                                                 gpr_x22, gpr_x23,
+                                                 gpr_x24, gpr_x25,
+                                                 gpr_x26, gpr_x27,
+                                                 gpr_x28, gpr_x29,
+                                                 gpr_x30, gpr_x31,
+                                                 gpr_pc,  LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_riscv64 /
+                sizeof g_gpr_regnums_riscv64[0]) -
+               1) == k_num_gpr_registers,
+              "g_gpr_regnums_riscv64 has wrong number of register infos");
+
+// RISC-V64 floating point registers.
+static const uint32_t g_fpr_regnums_riscv64[] = {
+    fpr_f0,  fpr_f1,  fpr_f2,     fpr_f3,  fpr_f4,   fpr_f5,
+    fpr_f6,  fpr_f7,  fpr_f8,     fpr_f9,  fpr_f10,  fpr_f11,
+    fpr_f12, fpr_f13, fpr_f14,    fpr_f15, fpr_f16,  fpr_f17,
+    fpr_f18, fpr_f19, fpr_f20,    fpr_f21, fpr_f22,  fpr_f23,
+    fpr_f24, fpr_f25, fpr_f26,    fpr_f27, fpr_f28,  fpr_f29,
+    fpr_f30, fpr_f31, fpr_fflags, fpr_frm, fpr_fcsr, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_fpr_regnums_riscv64 /
+                sizeof g_fpr_regnums_riscv64[0]) -
+               1) == k_num_fpr_registers,
+              "g_fpr_regnums_riscv64 has wrong number of register infos");
+
+// Register sets for RISC-V64.
+static const lldb_private::RegisterSet g_reg_sets_riscv64[k_num_register_sets] =
+    {{"General Purpose Registers", "gpr", k_num_gpr_registers,
+      g_gpr_regnums_riscv64},
+     {"Floating Point Registers", "fpr", k_num_fpr_registers,
+      g_fpr_regnums_riscv64}};
+
+static uint32_t
+GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
+  switch (target_arch.GetMachine()) {
+  case llvm::Triple::riscv64:
+    return static_cast<uint32_t>(sizeof(g_register_infos_riscv64_le) /
+                                 sizeof(g_register_infos_riscv64_le[0]));
+  default:
+    assert(false && "Unhandled target architecture.");
+    return 0;
+  }
+}
+
+RegisterInfoPOSIX_riscv64::RegisterInfoPOSIX_riscv64(
+    const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags)
+    : lldb_private::RegisterInfoAndSetInterface(target_arch),
+      m_register_info_p(GetRegisterInfoPtr(target_arch)),
+      m_register_info_count(GetRegisterInfoCount(target_arch)) {}
+
+uint32_t RegisterInfoPOSIX_riscv64::GetRegisterCount() const {
+  return k_num_gpr_registers;
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetGPRSize() const {
+  return sizeof(struct RegisterInfoPOSIX_riscv64::GPR);
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetFPRSize() const {
+  return sizeof(struct RegisterInfoPOSIX_riscv64::FPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoPOSIX_riscv64::GetRegisterInfo() const {
+  return m_register_info_p;
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetRegisterSetCount() const {
+  return k_num_register_sets - 1;
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetRegisterSetFromRegisterIndex(
+    uint32_t reg_index) const {
+  if (reg_index <= gpr_pc)
+    return GPRegSet;
+  if (reg_index >= fpr_f0 && reg_index <= fpr_fcsr)
+    return FPRegSet;
+  return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoPOSIX_riscv64::GetRegisterSet(size_t set_index) const {
+  if (set_index < GetRegisterSetCount())
+    return &g_reg_sets_riscv64[set_index];
+  return nullptr;
+}
+uint32_t RegisterInfoPOSIX_riscv64::GetRegNumFCSR() const { return fpr_fcsr; }

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

+//===-- RegisterInfos_riscv64.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+
+#include <stddef.h>
+
+#include "lldb/lldb-defines.h"
+#include "lldb/lldb-enumerations.h"
+#include "lldb/lldb-private.h"
+
+#ifndef GPR_OFFSET
+#error GPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef GPR_OFFSET_NAME
+#error GPR_OFFSET_NAME must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET
+#error FPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET_NAME
+#error FPR_OFFSET_NAME must be defined before including this header file
+#endif
+
+enum {
+  gpr_x0 = 0,
+  gpr_x1,
+  gpr_x2,
+  gpr_x3,
+  gpr_x4,
+  gpr_x5,
+  gpr_x6,
+  gpr_x7,
+  gpr_x8,
+  gpr_x9,
+  gpr_x10,
+  gpr_x11,
+  gpr_x12,
+  gpr_x13,
+  gpr_x14,
+  gpr_x15,
+  gpr_x16,
+  gpr_x17,
+  gpr_x18,
+  gpr_x19,
+  gpr_x20,
+  gpr_x21,
+  gpr_x22,
+  gpr_x23,
+  gpr_x24,
+  gpr_x25,
+  gpr_x26,
+  gpr_x27,
+  gpr_x28,
+  gpr_x29,
+  gpr_x30,
+  gpr_x31,
+  gpr_ra = gpr_x1,
+  gpr_sp = gpr_x2,
+  gpr_fp = gpr_x8,
+
+  gpr_pc = 32,
+
+  fpr_f0 = 33,
+  fpr_f1,
+  fpr_f2,
+  fpr_f3,
+  fpr_f4,
+  fpr_f5,
+  fpr_f6,
+  fpr_f7,
+  fpr_f8,
+  fpr_f9,
+  fpr_f10,
+  fpr_f11,
+  fpr_f12,
+  fpr_f13,
+  fpr_f14,
+  fpr_f15,
+  fpr_f16,
+  fpr_f17,
+  fpr_f18,
+  fpr_f19,
+  fpr_f20,
+  fpr_f21,
+  fpr_f22,
+  fpr_f23,
+  fpr_f24,
+  fpr_f25,
+  fpr_f26,
+  fpr_f27,
+  fpr_f28,
+  fpr_f29,
+  fpr_f30,
+  fpr_f31,
+
+  fpr_fflags,
+  fpr_frm,
+  fpr_fcsr,
+
+  k_num_registers
+};
+
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MISC_KIND(reg, type, generic_kind)                                     \
+  { reg, reg, generic_kind, LLDB_INVALID_REGNUM, reg }
+
+// Generates register kinds array for registers with only lldb kind
+#define LLDB_KIND(lldb_kind)                                                   \
+  {                                                                            \
+    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,             \
+        LLDB_INVALID_REGNUM, lldb_kind                                         \
+  }
+
+// Generates register kinds array for vector registers
+#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
+
+// FPR register kinds array for vector registers
+#define FPR64_KIND(reg, generic_kind) MISC_KIND(reg, fpr, generic_kind)
+
+#define MISC_FPR_KIND(lldb_kind) LLDB_KIND(lldb_kind)
+
+// Defines a 64-bit general purpose register
+#define DEFINE_GPR64(reg, generic_kind)                                        \
+  {                                                                            \
+#reg, nullptr, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint,              \
+        lldb::eFormatHex, GPR64_KIND(gpr_##reg, generic_kind), nullptr,        \
+        nullptr                                                                \
+  }
+
+// Defines a 64-bit general purpose register
+#define DEFINE_GPR64_ALT(reg, alt, generic_kind)                               \
+  {                                                                            \
+#reg, #alt, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint,                 \
+        lldb::eFormatHex, GPR64_KIND(gpr_##reg, generic_kind), nullptr,        \
+        nullptr                                                                \
+  }
+
+#define DEFINE_FPR64(reg, generic_kind)                                        \
+  {                                                                            \
+#reg, nullptr, 8, FPR_OFFSET(fpr_##reg - fpr_f0), lldb::eEncodingUint,     \
+        lldb::eFormatHex, FPR64_KIND(fpr_##reg, generic_kind), nullptr,        \
+        nullptr                                                                \
+  }
+
+// Defines miscellaneous status and control registers like fcsr
+#define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind)                           \
+  {                                                                            \
+#reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint,         \
+        lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr      \
+  }
+
+static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = {
+    // DEFINE_GPR64(name, GENERIC KIND)
+    DEFINE_GPR64(x0, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+    DEFINE_GPR64_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+    DEFINE_GPR64(x3, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x4, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x5, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x6, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x7, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+    DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x10, LLDB_REGNUM_GENERIC_ARG1),
+    DEFINE_GPR64(x11, LLDB_REGNUM_GENERIC_ARG2),
+    DEFINE_GPR64(x12, LLDB_REGNUM_GENERIC_ARG3),
+    DEFINE_GPR64(x13, LLDB_REGNUM_GENERIC_ARG4),
+    DEFINE_GPR64(x14, LLDB_REGNUM_GENERIC_ARG5),
+    DEFINE_GPR64(x15, LLDB_REGNUM_GENERIC_ARG6),
+    DEFINE_GPR64(x16, LLDB_REGNUM_GENERIC_ARG7),
+    DEFINE_GPR64(x17, LLDB_REGNUM_GENERIC_ARG8),
+    DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x29, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x30, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x31, LLDB_INVALID_REGNUM),
+
+    DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
+
+    DEFINE_FPR64(f0, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f1, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f2, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f3, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f4, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f5, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f6, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f7, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f8, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f9, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f10, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f11, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f12, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f13, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f14, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f15, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f16, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f17, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f18, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f19, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f20, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f21, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f22, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f23, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f24, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f25, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f26, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f27, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f28, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f29, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f30, LLDB_INVALID_REGNUM),
+    DEFINE_FPR64(f31, LLDB_INVALID_REGNUM),
+
+    DEFINE_MISC_REGS(fflags, 4, FPR, fpr_fflags),
+    DEFINE_MISC_REGS(frm, 4, FPR, fpr_frm),
+    DEFINE_MISC_REGS(fcsr, 4, FPR, fpr_fcsr),
+
+    // clang-format on
+};
+
+#endif // DECLARE_REGISTER_INFOS_RISCV64_STRUCT

lldb/source/Utility/ArchSpec.cpp

   case llvm::Triple::systemz:
   case llvm::Triple::xcore:
   case llvm::Triple::arc:
+  case llvm::Triple::riscv64:
     return false;
   }
 }

     }
     break;
 
+  case ArchSpec::eCore_riscv64:
+    if (!enforce_exact_match) {
+      if (core2 == ArchSpec::eCore_riscv64)
+        return true;
+    }
+    break;
+
   default:
     break;
   }