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Differential D129463

[RISCV][test] Precommit test for D129179.
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Authored by jacquesguan on Jul 10 2022, 11:47 PM.

Details

Reviewers
reames
craig.topper
asb
luismarques
frasercrmck
benshi001
Commits
rG557a471ab353: [RISCV][test] Precommit test for D129179.

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Event Timeline

jacquesguan created this revision.Jul 10 2022, 11:47 PM
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jacquesguan requested review of this revision.Jul 10 2022, 11:47 PM
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jacquesguan added a child revision: D129179: [RISCV] Extend use of SHXADD instructions in RVV spill/reload code..Jul 10 2022, 11:52 PM
Harbormaster completed remote builds in B174609: Diff 443562.Jul 11 2022, 12:36 AM
craig.topper accepted this revision.Jul 11 2022, 9:45 AM

LGTM

This revision is now accepted and ready to land.Jul 11 2022, 9:45 AM
This revision was landed with ongoing or failed builds.Jul 17 2022, 7:51 PM
Closed by commit rG557a471ab353: [RISCV][test] Precommit test for D129179. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rG557a471ab353: [RISCV][test] Precommit test for D129179..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
54 lines

Diff 445378

llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll

Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v1 = alloca <vscale x 1 x i1> %v1 = alloca <vscale x 1 x i1>
%v2 = alloca <vscale x 2 x i1> %v2 = alloca <vscale x 2 x i1>
%v4 = alloca <vscale x 4 x i1> %v4 = alloca <vscale x 4 x i1>
%v8 = alloca <vscale x 8 x i1> %v8 = alloca <vscale x 8 x i1>
ret void ret void
} }
define void @lmul_8_x5() nounwind {
; CHECK-LABEL: lmul_8_x5:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -80
; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 80
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 40
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -80
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 80
; CHECK-NEXT: ret
%v1 = alloca <vscale x 8 x i64>
%v2 = alloca <vscale x 8 x i64>
%v3 = alloca <vscale x 8 x i64>
%v4 = alloca <vscale x 8 x i64>
%v5 = alloca <vscale x 8 x i64>
ret void
}
define void @lmul_8_x9() nounwind {
; CHECK-LABEL: lmul_8_x9:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -80
; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 80
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 72
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -80
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 80
; CHECK-NEXT: ret
%v1 = alloca <vscale x 8 x i64>
%v2 = alloca <vscale x 8 x i64>
%v3 = alloca <vscale x 8 x i64>
%v4 = alloca <vscale x 8 x i64>
%v5 = alloca <vscale x 8 x i64>
%v6 = alloca <vscale x 8 x i64>
%v7 = alloca <vscale x 8 x i64>
%v8 = alloca <vscale x 8 x i64>
%v9 = alloca <vscale x 8 x i64>
ret void
}