[AArch64] Make FeatureFuseAdrpAdd a tune feature

[MaskRay]

Summary

Update D120104 to add FeatureFuseAdrpAdd to Processor#TuneFeatures
instead of Processor#Features, similar to FeatureFuseAES, and matching
Tune*.

This enable FeatureFuseAdrpAdd for clang -mcpu=xxx -mtune=generic even
if xxx does not set FeatureFuseAdrpAdd.

[peter.smith]

I think it makes sense to move this to the Tune part as it is micro-architectural rather than architectural.

llvm/lib/Target/AArch64/AArch64.td

1093

Is it worth moving the comment for FeatureFuseAdrpAdd to the ProcessorModel

[MaskRay]

move a comment

[peter.smith]

Thanks for the update LGTM.

llvm/lib/Target/AArch64/AArch64.td

list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                    FeatureNEON, FeaturePerfMon, FeatureSPE,
                                    FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
   list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
                                     FeatureMTE, FeatureSSBS];
 
   // ETE and TRBE are future architecture extensions. We temporarily enable them
   // by default for users targeting generic AArch64. The extensions do not
   // affect code generated by the compiler and can be used only by explicitly
   // mentioning the new system register names in assembly. FeatureFuseAdrpAdd is
   // enabled under Generic to allow linker merging optimizations.
-  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE,
-                                    FeatureFuseAdrpAdd];
+  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
 }
 
 def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic,
-                     [FeatureFuseAES, FeaturePostRAScheduler]>;
+                     [FeatureFuseAdrpAdd, FeatureFuseAES, FeaturePostRAScheduler]>;
 def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
                      [TuneA35]>;
 def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
                      [TuneA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
                      [TuneA53]>;
 def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,
                      [TuneA55]>;

llvm/test/CodeGen/AArch64/misched-fusion-lit.ll

entry:
   store i8* %add.ptr, i8** @g, align 8
   ret i8* %add.ptr
 
 ; CHECK-LABEL: litp:
 ; CHECK: adrp [[R:x[0-9]+]], litp
 ; CHECKFUSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp
 }
 
+define dso_local i8* @litp_tune_generic(i32 %a, i32 %b) "tune-cpu"="generic" {
+entry:
+  %add = add nsw i32 %b, %a
+  %idx.ext = sext i32 %add to i64
+  %add.ptr = getelementptr i8, i8* bitcast (i8* (i32, i32)* @litp_tune_generic to i8*), i64 %idx.ext
+  store i8* %add.ptr, i8** @g, align 8
+  ret i8* %add.ptr
+
+; CHECK-LABEL: litp_tune_generic:
+; CHECK:         adrp [[R:x[0-9]+]], litp_tune_generic
+; CHECK-NEXT:    add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic
+}
+
 define dso_local i32 @liti(i32 %a, i32 %b) {
 entry:
   %add = add i32 %a, -262095121
   %add1 = add i32 %add, %b
   ret i32 %add1
 
 ; CHECK-LABEL: liti:
 ; CHECK: mov [[R:w[0-9]+]], {{#[0-9]+}}