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Differential D128778

[RISCV] Precommit test for D128717
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Authored by Jimerlife on Jun 28 2022, 7:24 PM.

Details

Reviewers
craig.topper
reames
frasercrmck
benshi001
Commits
rG99da3115d1f5: [RISCV] Recommit test for D128717
rGb3b37f3ecfd6: [RISCV] Precommit test for D128717
Summary

Precommit test for D128717. In this precommit test, I set Imm = -1 for vector_spilce. If Imm >= 0, tests will crash.

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Event Timeline

Jimerlife created this revision.Jun 28 2022, 7:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 28 2022, 7:24 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
Jimerlife requested review of this revision.Jun 28 2022, 7:24 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptJun 28 2022, 7:24 PM
Jimerlife mentioned this in D128717: [RISCV] Change VECTOR_SPLICE mask operation from expand to promote.Jun 28 2022, 7:26 PM
Harbormaster completed remote builds in B172626: Diff 440825.Jun 28 2022, 8:15 PM
Jimerlife edited the summary of this revision. (Show Details)Jun 28 2022, 8:23 PM
Jimerlife added a comment.Jul 6 2022, 9:08 AM

gentle ping

Jimerlife added a comment.Jul 7 2022, 8:44 AM

Can I commit this test? Is this test ok?

craig.topper added a comment.Jul 7 2022, 9:28 AM

LGTM

craig.topper accepted this revision.Jul 7 2022, 9:28 AM
This revision is now accepted and ready to land.Jul 7 2022, 9:28 AM
This revision was landed with ongoing or failed builds.Jul 7 2022, 6:47 PM
Closed by commit rGb3b37f3ecfd6: [RISCV] Precommit test for D128717 (authored by Jimerlife). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jimerlife added a commit: rGb3b37f3ecfd6: [RISCV] Precommit test for D128717.
Jimerlife added a reverting change: rGab9e8a3a6f28: Revert "[RISCV] Precommit test for D128717".Jul 7 2022, 6:57 PM
jrtc27 added a comment.Jul 7 2022, 7:06 PM

From https://llvm.org/docs/DeveloperPolicy.html:

  • The commit message for the reverting commit should explain why patch is being reverted.
Jimerlife added a comment.Jul 7 2022, 7:14 PM
In D128778#3637651, @jrtc27 wrote:

From https://llvm.org/docs/DeveloperPolicy.html:

  • The commit message for the reverting commit should explain why patch is being reverted.

OK, Thank you. After I rebase main, I forgot to run update_llc_check_tests.py.

Jimerlife added a commit: rG99da3115d1f5: [RISCV] Recommit test for D128717.Jul 7 2022, 7:24 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
203 lines

Diff 443106

llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+m,+f,+d,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+m,+f,+d,+v,+zfh,+experimental-zvfh < %s | FileCheck %s ; RUN: llc -mtriple riscv64 -mattr=+m,+f,+d,+v,+zfh,+experimental-zvfh < %s | FileCheck %s
; Tests assume VLEN=128 or vscale_range_min=2. ; Tests assume VLEN=128 or vscale_range_min=2.
declare <vscale x 1 x i1> @llvm.experimental.vector.splice.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, i32)
define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv1i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 1 x i1> @llvm.experimental.vector.splice.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i32 -1)
ret <vscale x 1 x i1> %res
}
declare <vscale x 2 x i1> @llvm.experimental.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv2i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 -1)
ret <vscale x 2 x i1> %res
}
declare <vscale x 4 x i1> @llvm.experimental.vector.splice.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, i32)
define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv4i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 -1)
ret <vscale x 4 x i1> %res
}
declare <vscale x 8 x i1> @llvm.experimental.vector.splice.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, i32)
define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv8i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 -1)
ret <vscale x 8 x i1> %res
}
declare <vscale x 16 x i1> @llvm.experimental.vector.splice.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)
define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv16i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 16 x i1> @llvm.experimental.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 -1)
ret <vscale x 16 x i1> %res
}
declare <vscale x 32 x i1> @llvm.experimental.vector.splice.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, i32)
define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv32i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.experimental.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 -1)
ret <vscale x 32 x i1> %res
}
declare <vscale x 64 x i1> @llvm.experimental.vector.splice.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, i32)
define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) #0 {
; CHECK-LABEL: splice_nxv64i1_offset_negone:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.experimental.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1)
ret <vscale x 64 x i1> %res
}
declare <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, i32) declare <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, i32)
define <vscale x 1 x i8> @splice_nxv1i8_offset_zero(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { define <vscale x 1 x i8> @splice_nxv1i8_offset_zero(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv1i8_offset_zero: ; CHECK-LABEL: splice_nxv1i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 0) %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 0)
ret <vscale x 1 x i8> %res ret <vscale x 1 x i8> %res
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