[RISCV] Fold (add X, [-4096, -2049]) or (add X, [2048,4096]) into load/store address during isel.

[craig.topper]

Summary

Previously we iseled this to a pair of ADDIs and relied on a post
isel peephole to fold one of the ADDIs into the load/store. Now
we split the immediate in two parts the same way isel does and fold
one of the pieces. If the add has a non-memory use it will emit
two isels and larger one will CSE with the ADDI we created for the
the memory use.

[reames]

Code is fine, but no tests?

[craig.topper]

In D128741#3616256, @reames wrote:

Code is fine, but no tests?

I don't have a good way to show the change. The post-isel peephole already cleans this up. This is matching it earlier. I'm trying to remove the post-isel peephole.

[asb]

In D128741#3616350, @craig.topper wrote:

In D128741#3616256, @reames wrote:

Code is fine, but no tests?

I don't have a good way to show the change. The post-isel peephole already cleans this up. This is matching it earlier. I'm trying to remove the post-isel peephole.

So is this patch going to be updated to also remove the peephole? (just checking I'm following the planned staging of changes here!)

[craig.topper]

In D128741#3616395, @asb wrote:

In D128741#3616350, @craig.topper wrote:

In D128741#3616256, @reames wrote:

Code is fine, but no tests?

I don't have a good way to show the change. The post-isel peephole already cleans this up. This is matching it earlier. I'm trying to remove the post-isel peephole.

So is this patch going to be updated to also remove the peephole? (just checking I'm following the planned staging of changes here!)

We also have custom isel code for (add X, C) used by memory operations where C isn't a simm12 or suitable for addi pair. That code generates an (addi (X, C1-LoC), LoC) and relies on the peephole to fold the addi. We need to move that into the SelectRegAddrImm too. Then the peephole can be removed.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

if (isInt<12>(CVal)) {
         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
                                            Subtarget->getXLenVT());
       Offset = CurDAG->getTargetConstant(CVal, SDLoc(Addr),
                                          Subtarget->getXLenVT());
       return true;
     }
   }
 
+  // Handle ADD with large immediates.
+  if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Addr.getOperand(1))) {
+    int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+    assert(!isInt<12>(CVal) && "simm12 not already handled?");
+
+    if (isInt<12>(CVal / 2) && isInt<12>(CVal - CVal / 2)) {
+      // We can use an ADDI for part of the offset and fold the rest into the
+      // load/store. This mirrors the AddiPair PatFrag in RISCVInstrInfo.td.
+      int64_t Adj = CVal < 0 ? -2048 : 2047;
+      SDLoc DL(Addr);
+      MVT VT = Addr.getSimpleValueType();
+      Base = SDValue(
+          CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
+                                 CurDAG->getTargetConstant(Adj, DL, VT)),
+          0);
+      Offset = CurDAG->getTargetConstant(CVal - Adj, DL, VT);
+      return true;
+    }
+  }
+
   Base = Addr;
   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Subtarget->getXLenVT());
   return true;
 }
 
 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
                                         SDValue &ShAmt) {
   // Shift instructions on RISCV only read the lower 5 or 6 bits of the shift