Previously we iseled this to a pair of ADDIs and relied on a post
isel peephole to fold one of the ADDIs into the load/store. Now
we split the immediate in two parts the same way isel does and fold
one of the pieces. If the add has a non-memory use it will emit
two isels and larger one will CSE with the ADDI we created for the
the memory use.
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I don't have a good way to show the change. The post-isel peephole already cleans this up. This is matching it earlier. I'm trying to remove the post-isel peephole.
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So is this patch going to be updated to also remove the peephole? (just checking I'm following the planned staging of changes here!)
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We also have custom isel code for (add X, C) used by memory operations where C isn't a simm12 or suitable for addi pair. That code generates an (addi (X, C1-LoC), LoC) and relies on the peephole to fold the addi. We need to move that into the SelectRegAddrImm too. Then the peephole can be removed.