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[AMDGPU] gfx11 VINTERP intrinsics and ISel support
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Authored by Joe_Nash on Jun 14 2022, 8:53 AM.

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Depends on D127664

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Joe_Nash created this revision.Jun 14 2022, 8:53 AM
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Joe_Nash requested review of this revision.Jun 14 2022, 8:53 AM
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Joe_Nash added reviewers: piotr, Restricted Project.Jun 14 2022, 8:53 AM
rampitec added inline comments.Jun 14 2022, 11:18 AM
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
1508

Are you going to submit these builtins separately?

Joe_Nash updated this revision to Diff 437152.Jun 15 2022, 7:14 AM

removed builtins

This revision is now accepted and ready to land.Jun 15 2022, 11:42 AM
This revision was landed with ongoing or failed builds.Jun 17 2022, 6:46 AM
This revision was automatically updated to reflect the committed changes.
foad added inline comments.Jun 17 2022, 7:40 AM
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
1508

The __int_* prefix doesn't make much sense. I would suggest either using the tablegen name (int_amdgcn_interp_inreg_p10) or preferably the LLVM IR name (llvm.amdgcn.interp.inreg.p10).

Joe_Nash added inline comments.Jun 17 2022, 10:00 AM
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
1508

Are you going to submit these builtins separately?

I will remove the builtin and it can be added later if needed.

1508
kosarev added inline comments.Mar 24 2023, 4:29 AM
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
1524

Wouldn't it be more natural to declare p and p0 to be llvm_v2f16_ty?

foad added inline comments.Mar 24 2023, 4:51 AM
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
1524

Yes, I think so, but it would require coordinated changes in Mesa and LLPC, and we should probably also provide a v2f16 version of llvm.amdgcn.lds.param.load which currently always returns a float.