[RISCV] Fix a few corner case bugs in RISCVMergeBaseOffsetOpt::matchLargeOffset

[craig.topper]

Summary

The immediate for LUI is stored as 20-bit unsigned value. We need
to sign extend if after shifting by 12 to match the instruction
behavior.

If we find an LUI+ADDI on RV64, it means the constant isn't a
simm32. If it was we would have emitted LUI+ADDIW from constant
materialization. Make sure the constant is a simm32 before folding.
This appears to match gcc.

A future patch will add support for LUI+ADDIW on RV64.

Test cases have not been committd yet. Patch shows the diffs

[luismarques]

LGTM.

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

217–229

I'm surprised this issue wasn't noticed before.

[craig.topper]

Forgot to put the Differential line in the commit.

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

 //===----- RISCVMergeBaseOffset.cpp - Optimise address calculations  ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include <set>
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-merge-base-offset"
 #define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
 namespace {
 
 struct RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
+private:
+  const RISCVSubtarget *ST = nullptr;
+
+public:
   static char ID;
   bool runOnMachineFunction(MachineFunction &Fn) override;
   bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
 
   bool detectAndFoldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI);
   void foldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI, MachineInstr &Tail,
                   int64_t Offset);
   bool matchLargeOffset(MachineInstr &TailAdd, Register GSReg, int64_t &Offset);

 }
 
 // Update the offset in HiLUI and LoADDI instructions.
 // Delete the tail instruction and update all the uses to use the
 // output from LoADDI.
 void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &HiLUI,
                                          MachineInstr &LoADDI,
                                          MachineInstr &Tail, int64_t Offset) {
+  assert(isInt<32>(Offset) && "Unexpected offset");
   // Put the offset back in HiLUI and the LoADDI
   HiLUI.getOperand(1).setOffset(Offset);
   LoADDI.getOperand(2).setOffset(Offset);
   // Delete the tail instruction.
   DeadInstrs.insert(&Tail);
   MRI->replaceRegWith(Tail.getOperand(0).getReg(),
                       LoADDI.getOperand(0).getReg());
   LLVM_DEBUG(dbgs() << "  Merged offset " << Offset << " into base.\n"
if (OffsetTail.getOpcode() == RISCV::ADDI) {
     int64_t OffLo = AddiImmOp.getImm();
     MachineInstr &OffsetLui =
         *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
     MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
     if (OffsetLui.getOpcode() != RISCV::LUI ||
         LuiImmOp.getTargetFlags() != RISCVII::MO_None ||
         !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
       return false;
-    int64_t OffHi = OffsetLui.getOperand(1).getImm();
-    Offset = (OffHi << 12) + OffLo;
+    Offset = SignExtend64<32>(LuiImmOp.getImm() << 12);
+    Offset += OffLo;
+    // RV32 ignores the upper 32 bits.
+    if (!ST->is64Bit())
+       Offset = SignExtend64<32>(Offset);
+    // We can only fold simm32 offsets.
+    if (!isInt<32>(Offset))
+      return false;
     LLVM_DEBUG(dbgs() << "  Offset Instrs: " << OffsetTail
                       << "                 " << OffsetLui);
     DeadInstrs.insert(&OffsetTail);
     DeadInstrs.insert(&OffsetLui);
     return true;
   } else if (OffsetTail.getOpcode() == RISCV::LUI) {
     // The offset value has all zero bits in the lower 12 bits. Only LUI
     // exists.
     LLVM_DEBUG(dbgs() << "  Offset Instr: " << OffsetTail);
-    Offset = OffsetTail.getOperand(1).getImm() << 12;
+    Offset = SignExtend64<32>(OffsetTail.getOperand(1).getImm() << 12);
     DeadInstrs.insert(&OffsetTail);
     return true;
   }
   return false;
 }
 
 bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
                                                   MachineInstr &LoADDI) {
bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
   }
   return false;
 }
 
 bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
   if (skipFunction(Fn.getFunction()))
     return false;
 
+  ST = &Fn.getSubtarget<RISCVSubtarget>();
+
   bool MadeChange = false;
   DeadInstrs.clear();
   MRI = &Fn.getRegInfo();
   for (MachineBasicBlock &MBB : Fn) {
     LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
     for (MachineInstr &HiLUI : MBB) {
       MachineInstr *LoADDI = nullptr;
       if (!detectLuiAddiGlobal(HiLUI, LoADDI))

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

 ; CHECK-NEXT:    addi a0, a0, %lo(g+524288)
 ; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 524288)
 }
 
 define i8* @big_offset_neg_lui_tail() {
 ; CHECK-LABEL: big_offset_neg_lui_tail:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(bar+4294959104)
-; CHECK-NEXT:    addi a0, a0, %lo(bar+4294959104)
+; CHECK-NEXT:    lui a0, %hi(bar-8192)
+; CHECK-NEXT:    addi a0, a0, %lo(bar-8192)
 ; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i32 -8192)
 }
 
 define dso_local i32* @big_offset_one_use() local_unnamed_addr nounwind {
 ; RV32-LABEL: big_offset_one_use:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    lui a0, %hi(s+16572)

 entry:
   store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
   ret void
 }
 
 define i8* @neg_offset() {
 ; RV32-LABEL: neg_offset:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, %hi(bar+4294959105)
-; RV32-NEXT:    addi a0, a0, %lo(bar+4294959105)
+; RV32-NEXT:    lui a0, %hi(bar-8191)
+; RV32-NEXT:    addi a0, a0, %lo(bar-8191)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: neg_offset:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a0, %hi(bar)
 ; RV64-NEXT:    addi a0, a0, %lo(bar)
 ; RV64-NEXT:    lui a1, 1048574
 ; RV64-NEXT:    addiw a1, a1, 1
 ; RV64-NEXT:    add a0, a0, a1
 ; RV64-NEXT:    ret
   ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i32 -8191)
 }
 
-; This uses an LUI+ADDI on RV64 that does not produce a simm32.
+; This uses an LUI+ADDI on RV64 that does not produce a simm32. For RV32, we'll
+; truncate the offset.
 define i8* @neg_offset_not_simm32() {
-; CHECK-LABEL: neg_offset_not_simm32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(bar+2147482283)
-; CHECK-NEXT:    addi a0, a0, %lo(bar+2147482283)
-; CHECK-NEXT:    ret
+; RV32-LABEL: neg_offset_not_simm32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a0, %hi(bar+2147482283)
+; RV32-NEXT:    addi a0, a0, %lo(bar+2147482283)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: neg_offset_not_simm32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    lui a0, %hi(bar)
+; RV64-NEXT:    addi a0, a0, %lo(bar)
+; RV64-NEXT:    lui a1, 524288
+; RV64-NEXT:    addi a1, a1, -1365
+; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    ret
   ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i64 -2147485013)
 }