[RISCV] Extract and store new vl of vleff/vlsegff iff new_vl output pointer isn't null

[• pcwang-thead]

Summary

Store to null will be changed to unreachable, so all instructions
after a vleff/vlsegff intrinsic call with a null new_vl output pointer
will be deleted and will cause runtime errors. With this patch, if new_vl
output pointer is null, we won't extract and store the new vl.

We will generate IR like the following pseudocode:

if (new_vl_ptr != null) {
  *new_vl_ptr = new_vl;
}
// do something.

If new_vl output pointer is known to be null or not null, the code can be
optimized and there is no impact on performance.

[craig.topper]

What if it isn't known to be null at compile time but gets optimized to it. Are we trying to make passing a null pointer defined behavior for these intrinsics?

[• pcwang-thead]

• Generate IRs to compare destination and null. Only extract and store new vl iff destination is not null.
• Add a test to show optimized code.

[• pcwang-thead]

In D126461#3541577, @craig.topper wrote:

What if it isn't known to be null at compile time but gets optimized to it.

Thanks, I haven't thought it clearly and I just wanted to solve found bugs. :-)
I changed it to generate IRs to do the check. It is the same as GCC implementation now I think.
https://github.com/riscv-collab/riscv-gcc/blob/riscv-gcc-10.1-rvv-dev/gcc/config/riscv/riscv_vector.h#L289

if (new_vl)								\
    {									\
    if (__riscv_xlen == 32)						\
      *new_vl = __builtin_riscv_vreadvlsi ();				\
    else								\
      *new_vl = __builtin_riscv_vreadvldi ();				\
    }

Are we trying to make passing a null pointer defined behavior for these intrinsics?

Yes, but only for vleff instructions, since it has two outputs actually. And this behavior is compatible with GCC.
If necessary, I will propose it to rvv-intrinsic-doc.

[• pcwang-thead]

Ping. :-)

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

650

I don't think we usually use capital letters in basic block names.

651

newvl.isNull doesn't make sense since isNotNull eventually jumps to it.

Maybe use "store_newvl" and "store_newvl_end"?

651

I changed my mind. How about "newvl_store" and "newvl_end"?

[khchen]

Store to null will be changed to unreachable, so all instructions after vleff intrinsic call will be deleted and it causes runtime errors. If destination to store is null, we won't extract and store the new vl.

Yes, but only for vleff instructions, since it has two outputs actually. And this behavior is compatible with GCC. If necessary, I will propose it to rvv-intrinsic-doc.

Compiling with -O0, I didn't see this behavior, so are you trying to make the optimized code behavior is compatible with GCC?

In addition, it seems this behavior also exist in scalar code, do we also need to make the scalar result is compatible with GCC?
ex.

int foo (int j){
    int *k = nullptr;
    *k = 10;
    return 100;
}

compiling with -O3, llvm generates empty function but gcc generates

foo(int):
        sw      zero,0(zero)
        ebreak

https://godbolt.org/z/46vGrzs49

Please correct me if I misunderstand something, thanks.

[• pcwang-thead]

Rename BasicBlocks.

[• pcwang-thead]

In D126461#3565305, @khchen wrote:

Store to null will be changed to unreachable, so all instructions after vleff intrinsic call will be deleted and it causes runtime errors. If destination to store is null, we won't extract and store the new vl.

Yes, but only for vleff instructions, since it has two outputs actually. And this behavior is compatible with GCC. If necessary, I will propose it to rvv-intrinsic-doc.

Compiling with -O0, I didn't see this behavior, so are you trying to make the optimized code behavior is compatible with GCC?
In addition, it seems this behavior also exist in scalar code, do we also need to make the scalar result is compatible with GCC?

Store to nullptr is UB and it seems that LLVM and GCC have different behaviors. As shown in https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/Utils/Local.cpp#L2317, LLVM (simplifycfg in particular) will turn stores to nullptr into unreachable. When compiling with -O0, no optimization is done, so we can't see this behavior.
What I am doing in this patch is not making store to nullptr a defined behavior, but changing the way to store the new vl in vleff intrinsics (only do it if destination to store is not null).
Before:

new_vl = vleff(...)
*dst = new_vl;

Now:

new_vl = vleff(...)
if (dst) {
  *dst = new_vl;
}

So that we won't generate store to nullptr if we pass a nullptr to vleff intrinsics. This behavior is compatible with GCC.

As for the difference when compiling with -O3, it is because GCC handles this UB (store to nullptr) in other way. But as you can see, sw zero,0(zero) will cause interruption (runtime errors). I don't know if we should make LLVM and GCC with the same behavior to handle stores to null, which is beyond this patch.

ex.

int foo (int j){
    int *k = nullptr;
    *k = 10;
    return 100;
}

compiling with -O3, llvm generates empty function but gcc generates

foo(int):
        sw      zero,0(zero)
        ebreak

https://godbolt.org/z/46vGrzs49

Please correct me if I misunderstand something, thanks.

[khchen]

IMO, if I'm an user, I would not expected intrinsic function will generate the condition code to impact the performance, maybe we need to raise a issue in rvv-intrinsic-doc.

maybe another way is adding a note in intrinsic document to address that the vl could not be a null pointer.

How about the segment load? Does it make sense to add null pointer checking for all argument v0~vN?

[• pcwang-thead]

Add a test to show optimizaion of store to destination known to be not null.

[• pcwang-thead]

In D126461#3566626, @khchen wrote:

IMO, if I'm an user, I would not expected intrinsic function will generate the condition code to impact the performance, maybe we need to raise a issue in rvv-intrinsic-doc.
maybe another way is adding a note in intrinsic document to address that the vl could not be a null pointer.

I understand your concern about impact on performance and I added a test to show that the comparison and branch instruction can be optimized if destination is known to be not null (which is common in most scenarios using vleff).
For example:

size_t new_vl;
v=vleff(..., &new_vl, vl);
//usage of new_vl.

When doing instsimplify, LLVM knows new_vl won't be null. Comparison is evaluated to be true and branch instruction will be changed to unconditional branch (which will be simplified by simplifycfg).
So I think there is no impact on performance for most scenarios. For some cases that we don't know whether destination is null or not (like using destination passed by argument in vleff.c, but I think it is not normal usage and IPO may help), it is a potential risk that we may end in program crashing if we don't do null pointer checking.

How about the segment load? Does it make sense to add null pointer checking for all argument v0~vN?

That's a good point and I have thought it before. Here is my point but we can have more discussion.
I think we don't need null pointer checking for non-tuple segment loads. One of the reason is that we have said (but not documented?) that pointers can't be null in https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/95. Besides, I think we should treat the output of segment loads as whole structure though we have non-tuple intrinsics for now. The reason why we add null pointer checking for vleff is because the outputs of vleff are of two different types and we just want to ignore the output new vl.

[• pcwang-thead]

Add null pointer checking for vlsegff.

[• pcwang-thead]

Update test rvv-intrinsics-overloaded/vlsegff.c.

[• pcwang-thead]

Ping. Any comments?

[reames]

Despite the comments above, the purpose of this patch remains unclear.

Per the draft spec, the relevant wording is:
"These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception
on element 0. If element 0 raises an exception, vl is not modied, and the trap is taken. If an element > 0 raises an
exception, the corresponding trap is not taken, and the vector length vl is reduced to the index of the element that would
have raised an exception."

Working through the scenario in this patch with the destination being null, the expected result is for a trap to be generated (provided null is unmapped of course), and VL not to be modified. In order for this change to make any difference in runtime behavior, the value passed must be null (or otherwise guaranteed to fault). It seems very odd to me that we are modifying code which only runs after an instruction which is guaranteed to fault. Is there an assumed runtime here which is e.g. restarting execution?

Presumably, the actual IR instruction returns the unmodified VL in the faulting first access case. (If it doesn't, that's a bug we should fix.)

The last point, and it's a critical one, is that the outparam for new_vl does not have to be null if dest is. Given that, I think the entire prior discussion on motivation here is off base. Unless you can point to something in the intrinsic docs which says *explicitly* that the new_vl param to the intrinsic can be null when the dest is known to fault, I think we should strongly reject this patch. Even if you can, I think we should first ask if that's a bug in the intrinsic spec.

[khchen]

Could you please purpose this implement in rvv-intrinsc-doc first?
I think this feature need to have discussion because store to nullptr is UB but we are making it as defined behavior only for these intrinsics.
Personally I like they have consistent behavior and in document side we just make a note for users that vl should not be a null pointer.

[craig.topper]

In D126461#3596761, @reames wrote:

Despite the comments above, the purpose of this patch remains unclear.

Per the draft spec, the relevant wording is:
"These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception
on element 0. If element 0 raises an exception, vl is not modied, and the trap is taken. If an element > 0 raises an
exception, the corresponding trap is not taken, and the vector length vl is reduced to the index of the element that would
have raised an exception."

Working through the scenario in this patch with the destination being null, the expected result is for a trap to be generated (provided null is unmapped of course), and VL not to be modified. In order for this change to make any difference in runtime behavior, the value passed must be null (or otherwise guaranteed to fault). It seems very odd to me that we are modifying code which only runs after an instruction which is guaranteed to fault. Is there an assumed runtime here which is e.g. restarting execution?

dst in the patch description is not the pointer being loaded, it's the pointer of where to store the new_vl. That is only thing being checked for null in this patch.

[• pcwang-thead]

In D126461#3596769, @khchen wrote:

Could you please purpose this implement in rvv-intrinsc-doc first?
I think this feature need to have discussion because store to nullptr is UB but we are making it as defined behavior only for these intrinsics.
Personally I like they have consistent behavior and in document side we just make a note for users that vl should not be a null pointer.

https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/153

[• pcwang-thead]

In D126461#3597862, @craig.topper wrote:

In D126461#3596761, @reames wrote:

Despite the comments above, the purpose of this patch remains unclear.

Per the draft spec, the relevant wording is:
"These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception
on element 0. If element 0 raises an exception, vl is not modied, and the trap is taken. If an element > 0 raises an
exception, the corresponding trap is not taken, and the vector length vl is reduced to the index of the element that would
have raised an exception."

Working through the scenario in this patch with the destination being null, the expected result is for a trap to be generated (provided null is unmapped of course), and VL not to be modified. In order for this change to make any difference in runtime behavior, the value passed must be null (or otherwise guaranteed to fault). It seems very odd to me that we are modifying code which only runs after an instruction which is guaranteed to fault. Is there an assumed runtime here which is e.g. restarting execution?

dst in the patch description is not the pointer being loaded, it's the pointer of where to store the new_vl. That is only thing being checked for null in this patch.

Thanks for your kind explanation! @craig.topper
I did this change just because previous GCC implementation have done null pointer checking. Some of our codebases crashed when we switched to LLVM because new_vl is set to NULL to ignore output new vl. : ) @reames

[reames]

In D126461#3597862, @craig.topper wrote:

dst in the patch description is not the pointer being loaded, it's the pointer of where to store the new_vl. That is only thing being checked for null in this patch.

I agree this is a possible interpretation, but it's also inconsistent with some of the other review discussion above.

@pcwang-thead Please consider clarifying the patch description a blocking item for future review or potential approval.

[craig.topper]

In D126461#3599122, @reames wrote:

In D126461#3597862, @craig.topper wrote:

dst in the patch description is not the pointer being loaded, it's the pointer of where to store the new_vl. That is only thing being checked for null in this patch.

I agree this is a possible interpretation, but it's also inconsistent with some of the other review discussion above.

@pcwang-thead Please consider clarifying the patch description a blocking item for future review or potential approval.

I don't believe it was meant to be inconsistent, but I agree it could be confusing. All of the prior discussion is talking about the C intrinsic interface which has two pointers, the pointer to load from, and the outparam pointer for new_vl. All mentions of a pointer being null were only ever meant to refer to the outparam pointer.

[craig.topper]

I have attempted to revise the title and description. Please take a look @pcwang-thead and @reames

[reames]

@craig.topper Much clearer, thank you.

[reames]

Ok, with the revised description, let me start anew in my response.

I don't have any particular problem with this change. I do think it would be good to explicitly update the docs to indicate whether the param can be null or not, but given a) gcc has allowed it, and b) the performance impact should be minimal, I would see no concerns with just documenting the current gcc state and implementing it in clang. That seems like the path of least resistance here and is a reasonable outcome.

I'm not worried about perf impact from the null check as idiomatic usage is likely to involve taking the address of a local variable which will be trivially non-null.

[• pcwang-thead]

After discussion, we decide to not change anything right now.

clang/include/clang/Basic/riscv_vector.td

let Name = NAME # "_v",
         Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
         Value *NewVL = Ops[1];
         Ops.erase(Ops.begin() + 1);
         Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
         llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
         llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
         llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
         // Store new_vl.
+        llvm::Value *Cmp =
+            Builder.CreateCmp(llvm::CmpInst::ICMP_NE, NewVL,
+                              ConstantPointerNull::get(
+                                  cast<llvm::PointerType>(NewVL->getType())));
+        BasicBlock *NewVLStore = createBasicBlock("newvl_store", this->CurFn);
+        BasicBlock *NewVLEnd = createBasicBlock("newvl_end", this->CurFn);
+        Builder.CreateCondBr(Cmp, NewVLStore, NewVLEnd);
+        Builder.SetInsertPoint(NewVLStore);
         clang::CharUnits Align =
             CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
         Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+        Builder.CreateBr(NewVLEnd);
+        Builder.SetInsertPoint(NewVLEnd);
         return V;
       }
       }],
       MaskedManualCodegen = [{
       {
         // Move mask to right before vl.
         std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
         Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
         IntrinsicTypes = {ResultType, Ops[4]->getType()};
         Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
         Value *NewVL = Ops[2];
         Ops.erase(Ops.begin() + 2);
         llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
         llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
         llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
         // Store new_vl.
+        llvm::Value *Cmp =
+            Builder.CreateCmp(llvm::CmpInst::ICMP_NE, NewVL,
+                              ConstantPointerNull::get(
+                                  cast<llvm::PointerType>(NewVL->getType())));
+        BasicBlock *NewVLStore = createBasicBlock("newvl_store", this->CurFn);
+        BasicBlock *NewVLEnd = createBasicBlock("newvl_end", this->CurFn);
+        Builder.CreateCondBr(Cmp, NewVLStore, NewVLEnd);
+        Builder.SetInsertPoint(NewVLStore);
         clang::CharUnits Align =
             CGM.getNaturalPointeeTypeAlignment(E->getArg(3)->getType());
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
         Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+        Builder.CreateBr(NewVLEnd);
+        Builder.SetInsertPoint(NewVLEnd);
         return V;
       }
       }] in {
     foreach type = types in {
       def : RVVBuiltin<"v", "vPCePz", type>;
       // Skip floating types for unsigned versions.
       if !not(IsFloat<type>.val) then {
         def : RVVBuiltin<"Uv", "UvPCUePz", type>;
defvar eew = !cond(!eq(type, "c") : "8",
       llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
       clang::CharUnits Align =
           CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
       for (unsigned I = 0; I < NF; ++I) {
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
         Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
       }
       // Store new_vl.
+      llvm::Value *Cmp = Builder.CreateCmp(
+          llvm::CmpInst::ICMP_NE, NewVL,
+          ConstantPointerNull::get(cast<llvm::PointerType>(NewVL->getType())));
+      BasicBlock *NewVLStore = createBasicBlock("newvl_store", this->CurFn);
+      BasicBlock *NewVLEnd = createBasicBlock("newvl_end", this->CurFn);
+      Builder.CreateCondBr(Cmp, NewVLStore, NewVLEnd);
+      Builder.SetInsertPoint(NewVLStore);
       llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {NF});
-      return Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+      llvm::Value *StoreNewVL =
+          Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+      Builder.CreateBr(NewVLEnd);
+      Builder.SetInsertPoint(NewVLEnd);
+      return StoreNewVL;
     }
             }],
             MaskedManualCodegen = [{
     {
       // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, new_vl, vl)
       // intrinsic: (maskedoff0, ..., ptr, mask, vl)
       IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()),
                         Ops[2 * NF + 3]->getType()};
defvar eew = !cond(!eq(type, "c") : "8",
       llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
       clang::CharUnits Align =
           CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
       for (unsigned I = 0; I < NF; ++I) {
         llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
         Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
       }
       // Store new_vl.
+      llvm::Value *Cmp = Builder.CreateCmp(
+          llvm::CmpInst::ICMP_NE, NewVL,
+          ConstantPointerNull::get(cast<llvm::PointerType>(NewVL->getType())));
+      BasicBlock *NewVLStore = createBasicBlock("newvl_store", this->CurFn);
+      BasicBlock *NewVLEnd = createBasicBlock("newvl_end", this->CurFn);
+      Builder.CreateCondBr(Cmp, NewVLStore, NewVLEnd);
+      Builder.SetInsertPoint(NewVLStore);
       llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {NF});
-      return Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+      llvm::Value *StoreNewVL =
+          Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+      Builder.CreateBr(NewVLEnd);
+      Builder.SetInsertPoint(NewVLEnd);
+      return StoreNewVL;
     }
             }] in {
           defvar PV = PVString<nf, /*signed=*/true>.S;
           defvar PUV = PVString<nf, /*signed=*/false>.S;
           def : RVVBuiltin<"v", "0" # PV # "PCe" # "Pz", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "Pz", type>;
         }

clang/test/CodeGen/RISCV/rvv-intrinsics/vleff-optimized.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64-O0 %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -O2 | FileCheck --check-prefix=CHECK-RV64-O2 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-O0-LABEL: @func_return_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    ret i64* null
+//
+// CHECK-RV64-O2-LABEL: @func_return_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    ret i64* null
+//
+size_t *__attribute__((noinline)) func_return_nullptr() {
+  return NULL;
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_not_null(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_not_null(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[DOTNOT:%.*]] = icmp eq i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O2-NEXT:    br i1 [[DOTNOT]], label [[NEWVL_END:%.*]], label [[NEWVL_STORE:%.*]]
+// CHECK-RV64-O2:       newvl_store:
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP2]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-O2-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O2:       newvl_end:
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP3]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_not_null(const int8_t *base, size_t *new_vl, size_t vl) {
+  return vle8ff_v_i8mf8(base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_not_null_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_not_null_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[DOTNOT:%.*]] = icmp eq i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O2-NEXT:    br i1 [[DOTNOT]], label [[NEWVL_END:%.*]], label [[NEWVL_STORE:%.*]]
+// CHECK-RV64-O2:       newvl_store:
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP2]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-O2-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O2:       newvl_end:
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP3]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_not_null_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+  return vle8ff_v_i8mf8_m(mask, maskedoff, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_direct_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    br i1 false, label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP3]], i64* null, align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_direct_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_direct_nullptr(const int8_t *base, size_t vl) {
+  return vle8ff_v_i8mf8(base, NULL, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_direct_nullptr_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    br i1 false, label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP3]], i64* null, align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_direct_nullptr_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_direct_nullptr_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t vl) {
+  return vle8ff_v_i8mf8_m(mask, maskedoff, base, NULL, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_indirect_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* null, null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* null, align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_indirect_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_indirect_nullptr(const int8_t *base, size_t vl) {
+  size_t *new_vl = NULL;
+  return vle8ff_v_i8mf8(base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_indirect_nullptr_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* null, null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* null, align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_indirect_nullptr_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_indirect_nullptr_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t vl) {
+  size_t *new_vl = NULL;
+  return vle8ff_v_i8mf8_m(mask, maskedoff, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_cross_func_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[CALL:%.*]] = call i64* @func_return_nullptr()
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[CALL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[CALL]], align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_cross_func_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_cross_func_nullptr(const int8_t *base, size_t vl) {
+  size_t *new_vl = func_return_nullptr();
+  return vle8ff_v_i8mf8(base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_cross_func_nullptr_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[CALL:%.*]] = call i64* @func_return_nullptr()
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[CALL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[CALL]], align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_cross_func_nullptr_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_cross_func_nullptr_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t vl) {
+  size_t *new_vl = func_return_nullptr();
+  return vle8ff_v_i8mf8_m(mask, maskedoff, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_known_not_null(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[NEW_VL:%.*]] = alloca i64, align 8
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    [[TMP5:%.*]] = load i64, i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP5]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_known_not_null(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP2]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP3]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_known_not_null(const int8_t *base, size_t vl, size_t *out_new_vl) {
+  size_t new_vl;
+  vint8mf8_t v = vle8ff_v_i8mf8(base, &new_vl, vl);
+  *out_new_vl = new_vl;
+  return v;
+}
+
+// CHECK-RV64-O0-LABEL: @test_vleff_save_new_vl_to_known_not_null_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[NEW_VL:%.*]] = alloca i64, align 8
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    [[TMP5:%.*]] = load i64, i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP5]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O0-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
+//
+// CHECK-RV64-O2-LABEL: @test_vleff_save_new_vl_to_known_not_null_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = tail call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP2]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP3]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_known_not_null_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t vl, size_t *out_new_vl) {
+  size_t new_vl;
+  vint8mf8_t v = vle8ff_v_i8mf8_m(mask, maskedoff, base, &new_vl, vl);
+  *out_new_vl = new_vl;
+  return v;
+}

clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
 // RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
 //
 vint8mf8_t test_vle8ff_v_i8mf8 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8mf8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP2]]
 //
 vint8mf4_t test_vle8ff_v_i8mf4 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8mf4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP2]]
 //
 vint8mf2_t test_vle8ff_v_i8mf2 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP2]]
 //
 vint8m1_t test_vle8ff_v_i8m1 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP2]]
 //
 vint8m2_t test_vle8ff_v_i8m2 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP2]]
 //
 vint8m4_t test_vle8ff_v_i8m4 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP2]]
 //
 vint8m8_t test_vle8ff_v_i8m8 (const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
 //
 vuint8mf8_t test_vle8ff_v_u8mf8 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8mf8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP2]]
 //
 vuint8mf4_t test_vle8ff_v_u8mf4 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8mf4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP2]]
 //
 vuint8mf2_t test_vle8ff_v_u8mf2 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP2]]
 //
 vuint8m1_t test_vle8ff_v_u8m1 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP2]]
 //
 vuint8m2_t test_vle8ff_v_u8m2 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP2]]
 //
 vuint8m4_t test_vle8ff_v_u8m4 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP2]]
 //
 vuint8m8_t test_vle8ff_v_u8m8 (const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
 //
 vint8mf8_t test_vle8ff_v_i8mf8_m (vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8mf8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP2]]
 //
 vint8mf4_t test_vle8ff_v_i8mf4_m (vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8mf4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP2]]
 //
 vint8mf2_t test_vle8ff_v_i8mf2_m (vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP2]]
 //
 vint8m1_t test_vle8ff_v_i8m1_m (vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP2]]
 //
 vint8m2_t test_vle8ff_v_i8m2_m (vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP2]]
 //
 vint8m4_t test_vle8ff_v_i8m4_m (vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP2]]
 //
 vint8m8_t test_vle8ff_v_i8m8_m (vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_i8m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP2]]
 //
 vuint8mf8_t test_vle8ff_v_u8mf8_m (vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8mf8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP2]]
 //
 vuint8mf4_t test_vle8ff_v_u8mf4_m (vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8mf4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP2]]
 //
 vuint8mf2_t test_vle8ff_v_u8mf2_m (vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP2]]
 //
 vuint8m1_t test_vle8ff_v_u8m1_m (vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP2]]
 //
 vuint8m2_t test_vle8ff_v_u8m2_m (vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP2]]
 //
 vuint8m4_t test_vle8ff_v_u8m4_m (vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle8ff_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP2]]
 //
 vuint8m8_t test_vle8ff_v_u8m8_m (vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
   return vle8ff_v_u8m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP2]]
 //
 vint16mf4_t test_vle16ff_v_i16mf4 (const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16mf4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP2]]
 //
 vint16mf2_t test_vle16ff_v_i16mf2 (const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP2]]
 //
 vint16m1_t test_vle16ff_v_i16m1 (const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 //
 vint16m2_t test_vle16ff_v_i16m2 (const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP2]]
 //
 vint16m4_t test_vle16ff_v_i16m4 (const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP2]]
 //
 vint16m8_t test_vle16ff_v_i16m8 (const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP2]]
 //
 vuint16mf4_t test_vle16ff_v_u16mf4 (const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16mf4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP2]]
 //
 vuint16mf2_t test_vle16ff_v_u16mf2 (const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP2]]
 //
 vuint16m1_t test_vle16ff_v_u16m1 (const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 //
 vuint16m2_t test_vle16ff_v_u16m2 (const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP2]]
 //
 vuint16m4_t test_vle16ff_v_u16m4 (const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP2]]
 //
 vuint16m8_t test_vle16ff_v_u16m8 (const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP2]]
 //
 vint16mf4_t test_vle16ff_v_i16mf4_m (vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16mf4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP2]]
 //
 vint16mf2_t test_vle16ff_v_i16mf2_m (vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP2]]
 //
 vint16m1_t test_vle16ff_v_i16m1_m (vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 //
 vint16m2_t test_vle16ff_v_i16m2_m (vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP2]]
 //
 vint16m4_t test_vle16ff_v_i16m4_m (vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_i16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP2]]
 //
 vint16m8_t test_vle16ff_v_i16m8_m (vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_i16m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP2]]
 //
 vuint16mf4_t test_vle16ff_v_u16mf4_m (vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16mf4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP2]]
 //
 vuint16mf2_t test_vle16ff_v_u16mf2_m (vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP2]]
 //
 vuint16m1_t test_vle16ff_v_u16m1_m (vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 //
 vuint16m2_t test_vle16ff_v_u16m2_m (vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP2]]
 //
 vuint16m4_t test_vle16ff_v_u16m4_m (vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_u16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP2]]
 //
 vuint16m8_t test_vle16ff_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_u16m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP2]]
 //
 vint32mf2_t test_vle32ff_v_i32mf2 (const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP2]]
 //
 vint32m1_t test_vle32ff_v_i32m1 (const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 //
 vint32m2_t test_vle32ff_v_i32m2 (const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP2]]
 //
 vint32m4_t test_vle32ff_v_i32m4 (const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP2]]
 //
 vint32m8_t test_vle32ff_v_i32m8 (const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP2]]
 //
 vuint32mf2_t test_vle32ff_v_u32mf2 (const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP2]]
 //
 vuint32m1_t test_vle32ff_v_u32m1 (const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 //
 vuint32m2_t test_vle32ff_v_u32m2 (const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP2]]
 //
 vuint32m4_t test_vle32ff_v_u32m4 (const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP2]]
 //
 vuint32m8_t test_vle32ff_v_u32m8 (const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP2]]
 //
 vfloat32mf2_t test_vle32ff_v_f32mf2 (const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32mf2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP2]]
 //
 vfloat32m1_t test_vle32ff_v_f32m1 (const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP2]]
 //
 vfloat32m2_t test_vle32ff_v_f32m2 (const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP2]]
 //
 vfloat32m4_t test_vle32ff_v_f32m4 (const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP2]]
 //
 vfloat32m8_t test_vle32ff_v_f32m8 (const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP2]]
 //
 vint32mf2_t test_vle32ff_v_i32mf2_m (vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP2]]
 //
 vint32m1_t test_vle32ff_v_i32m1_m (vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 //
 vint32m2_t test_vle32ff_v_i32m2_m (vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP2]]
 //
 vint32m4_t test_vle32ff_v_i32m4_m (vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_i32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP2]]
 //
 vint32m8_t test_vle32ff_v_i32m8_m (vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_i32m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP2]]
 //
 vuint32mf2_t test_vle32ff_v_u32mf2_m (vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP2]]
 //
 vuint32m1_t test_vle32ff_v_u32m1_m (vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 //
 vuint32m2_t test_vle32ff_v_u32m2_m (vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP2]]
 //
 vuint32m4_t test_vle32ff_v_u32m4_m (vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_u32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP2]]
 //
 vuint32m8_t test_vle32ff_v_u32m8_m (vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_u32m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP2]]
 //
 vfloat32mf2_t test_vle32ff_v_f32mf2_m (vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32mf2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP2]]
 //
 vfloat32m1_t test_vle32ff_v_f32m1_m (vbool32_t mask, vfloat32m1_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP2]]
 //
 vfloat32m2_t test_vle32ff_v_f32m2_m (vbool16_t mask, vfloat32m2_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP2]]
 //
 vfloat32m4_t test_vle32ff_v_f32m4_m (vbool8_t mask, vfloat32m4_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle32ff_v_f32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP2]]
 //
 vfloat32m8_t test_vle32ff_v_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
   return vle32ff_v_f32m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP2]]
 //
 vint64m1_t test_vle64ff_v_i64m1 (const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 //
 vint64m2_t test_vle64ff_v_i64m2 (const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP2]]
 //
 vint64m4_t test_vle64ff_v_i64m4 (const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP2]]
 //
 vint64m8_t test_vle64ff_v_i64m8 (const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP2]]
 //
 vuint64m1_t test_vle64ff_v_u64m1 (const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 //
 vuint64m2_t test_vle64ff_v_u64m2 (const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP2]]
 //
 vuint64m4_t test_vle64ff_v_u64m4 (const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP2]]
 //
 vuint64m8_t test_vle64ff_v_u64m8 (const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP2]]
 //
 vfloat64m1_t test_vle64ff_v_f64m1 (const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m1(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP2]]
 //
 vfloat64m2_t test_vle64ff_v_f64m2 (const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m2(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP2]]
 //
 vfloat64m4_t test_vle64ff_v_f64m4 (const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m4(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP2]]
 //
 vfloat64m8_t test_vle64ff_v_f64m8 (const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m8(base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP2]]
 //
 vint64m1_t test_vle64ff_v_i64m1_m (vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 //
 vint64m2_t test_vle64ff_v_i64m2_m (vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP2]]
 //
 vint64m4_t test_vle64ff_v_i64m4_m (vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_i64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP2]]
 //
 vint64m8_t test_vle64ff_v_i64m8_m (vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_i64m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP2]]
 //
 vuint64m1_t test_vle64ff_v_u64m1_m (vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 //
 vuint64m2_t test_vle64ff_v_u64m2_m (vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP2]]
 //
 vuint64m4_t test_vle64ff_v_u64m4_m (vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_u64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP2]]
 //
 vuint64m8_t test_vle64ff_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_u64m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP2]]
 //
 vfloat64m1_t test_vle64ff_v_f64m1_m (vbool64_t mask, vfloat64m1_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m1_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP2]]
 //
 vfloat64m2_t test_vle64ff_v_f64m2_m (vbool32_t mask, vfloat64m2_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m2_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP2]]
 //
 vfloat64m4_t test_vle64ff_v_f64m4_m (vbool16_t mask, vfloat64m4_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m4_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle64ff_v_f64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP2]]
 //
 vfloat64m8_t test_vle64ff_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
   return vle64ff_v_f64m8_m(mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP2]]
 //
 vfloat16mf4_t test_vle16ff_v_f16mf4 (const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16mf4 (base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP2]]
 //
 vfloat16mf2_t test_vle16ff_v_f16mf2 (const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16mf2 (base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP2]]
 //
 vfloat16m1_t test_vle16ff_v_f16m1 (const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m1 (base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP2]]
 //
 vfloat16m2_t test_vle16ff_v_f16m2 (const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m2 (base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP2]]
 //
 vfloat16m4_t test_vle16ff_v_f16m4 (const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m4 (base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP2]]
 //
 vfloat16m8_t test_vle16ff_v_f16m8 (const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m8 (base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP2]]
 //
 vfloat16mf4_t test_vle16ff_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16mf4_m (mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP2]]
 //
 vfloat16mf2_t test_vle16ff_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16mf2_m (mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP2]]
 //
 vfloat16m1_t test_vle16ff_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m1_m (mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP2]]
 //
 vfloat16m2_t test_vle16ff_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m2_m (mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP2]]
 //
 vfloat16m4_t test_vle16ff_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m4_m (mask, maskedoff, base, new_vl, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vle16ff_v_f16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 0
-// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 1
-// CHECK-RV64-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64:       newvl_store:
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 8
+// CHECK-RV64-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64:       newvl_end:
 // CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP2]]
 //
 vfloat16m8_t test_vle16ff_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vle16ff_v_f16m8_m (mask, maskedoff, base, new_vl, vl);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff-optimized.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64-O0 %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -O2 | FileCheck --check-prefix=CHECK-RV64-O2 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-O0-LABEL: @func_return_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    ret i64* null
+//
+// CHECK-RV64-O2-LABEL: @func_return_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    ret i64* null
+//
+size_t *__attribute__((noinline)) func_return_nullptr() {
+  return NULL;
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_not_null(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_not_null(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[DOTNOT:%.*]] = icmp eq i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O2-NEXT:    br i1 [[DOTNOT]], label [[NEWVL_END:%.*]], label [[NEWVL_STORE:%.*]]
+// CHECK-RV64-O2:       newvl_store:
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL]], align 1
+// CHECK-RV64-O2-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O2:       newvl_end:
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_not_null(vint8mf8_t *v0, vint8mf8_t *v1, const int8_t *base, size_t *new_vl, size_t vl) {
+  return vlseg2e8ff_v_i8mf8(v0, v1, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_not_null_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_not_null_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[DOTNOT:%.*]] = icmp eq i64* [[NEW_VL:%.*]], null
+// CHECK-RV64-O2-NEXT:    br i1 [[DOTNOT]], label [[NEWVL_END:%.*]], label [[NEWVL_STORE:%.*]]
+// CHECK-RV64-O2:       newvl_store:
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP3]], i64* [[NEW_VL]], align 1
+// CHECK-RV64-O2-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O2:       newvl_end:
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_not_null_m(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) {
+  return vlseg2e8ff_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_direct_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    br i1 false, label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP3]], i64* null, align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_direct_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_direct_nullptr(vint8mf8_t *v0, vint8mf8_t *v1, const int8_t *base, size_t vl) {
+  return vlseg2e8ff_v_i8mf8(v0, v1, base, NULL, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_direct_nullptr_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    br i1 false, label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP3]], i64* null, align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_direct_nullptr_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_direct_nullptr_m(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t vl) {
+  return vlseg2e8ff_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, NULL, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_indirect_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* null, null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* null, align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_indirect_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_indirect_nullptr(vint8mf8_t *v0, vint8mf8_t *v1, const int8_t *base, size_t vl) {
+  size_t *new_vl = NULL;
+  return vlseg2e8ff_v_i8mf8(v0, v1, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_indirect_nullptr_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* null, null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* null, align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_indirect_nullptr_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_indirect_nullptr_m(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t vl) {
+  size_t *new_vl = NULL;
+  return vlseg2e8ff_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_cross_func_nullptr(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[CALL:%.*]] = call i64* @func_return_nullptr()
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[CALL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[CALL]], align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_cross_func_nullptr(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_cross_func_nullptr(vint8mf8_t *v0, vint8mf8_t *v1, const int8_t *base, size_t vl) {
+  size_t *new_vl = func_return_nullptr();
+  return vlseg2e8ff_v_i8mf8(v0, v1, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_cross_func_nullptr_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[CALL:%.*]] = call i64* @func_return_nullptr()
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[CALL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[CALL]], align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_cross_func_nullptr_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_cross_func_nullptr_m(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t vl) {
+  size_t *new_vl = func_return_nullptr();
+  return vlseg2e8ff_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl);
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_known_not_null(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[NEW_VL:%.*]] = alloca i64, align 8
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    [[TMP5:%.*]] = load i64, i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP5]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_known_not_null(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP3]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_known_not_null(vint8mf8_t *v0, vint8mf8_t *v1, const int8_t *base, size_t vl, size_t *out_new_vl) {
+  size_t new_vl;
+  vlseg2e8ff_v_i8mf8(v0, v1, base, &new_vl, vl);
+  *out_new_vl = new_vl;
+}
+
+// CHECK-RV64-O0-LABEL: @test_vlsegff_save_new_vl_to_known_not_null_m(
+// CHECK-RV64-O0-NEXT:  entry:
+// CHECK-RV64-O0-NEXT:    [[NEW_VL:%.*]] = alloca i64, align 8
+// CHECK-RV64-O0-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O0-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O0-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O0-NEXT:    [[TMP3:%.*]] = icmp ne i64* [[NEW_VL]], null
+// CHECK-RV64-O0-NEXT:    br i1 [[TMP3]], label [[NEWVL_STORE:%.*]], label [[NEWVL_END:%.*]]
+// CHECK-RV64-O0:       newvl_store:
+// CHECK-RV64-O0-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP4]], i64* [[NEW_VL]], align 1
+// CHECK-RV64-O0-NEXT:    br label [[NEWVL_END]]
+// CHECK-RV64-O0:       newvl_end:
+// CHECK-RV64-O0-NEXT:    [[TMP5:%.*]] = load i64, i64* [[NEW_VL]], align 8
+// CHECK-RV64-O0-NEXT:    store i64 [[TMP5]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O0-NEXT:    ret void
+//
+// CHECK-RV64-O2-LABEL: @test_vlsegff_save_new_vl_to_known_not_null_m(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.*]], <vscale x 1 x i8> [[MASKEDOFF1:%.*]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-O2-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 0
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP1]], <vscale x 1 x i8>* [[V0:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 1
+// CHECK-RV64-O2-NEXT:    store <vscale x 1 x i8> [[TMP2]], <vscale x 1 x i8>* [[V1:%.*]], align 1
+// CHECK-RV64-O2-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, i64 } [[TMP0]], 2
+// CHECK-RV64-O2-NEXT:    store i64 [[TMP3]], i64* [[OUT_NEW_VL:%.*]], align 8
+// CHECK-RV64-O2-NEXT:    ret void
+//
+void test_vlsegff_save_new_vl_to_known_not_null_m(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t vl, size_t *out_new_vl) {
+  size_t new_vl;
+  vlseg2e8ff_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, &new_vl, vl);
+  *out_new_vl = new_vl;
+}