[DAGCombiner][AArch64] Don't fold (smulo x, 2) -> (saddo x, x) if VT is i2.

[craig.topper]

Summary

If the VT is i2, then 2 is really -2.

Test has not been commited yet, but diff shows the change.

Fixes PR55644.

[spatel]

LGTM - I don't think we'd see this problem in IR with the example test because we'd reduce the intrinsic if there's no use of the multiply result. We probably don't have the corresponding fold here because we don't expect to create these ops in SDAG?

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
     return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
 
   // fold (mulo x, 0) -> 0 + no carry out
   if (isNullOrNullSplat(N1))
     return CombineTo(N, DAG.getConstant(0, DL, VT),
                      DAG.getConstant(0, DL, CarryVT));
 
   // (mulo x, 2) -> (addo x, x)
-  if (N1C && N1C->getAPIntValue() == 2)
+  // FIXME: This needs a freeze.
+  if (N1C && N1C->getAPIntValue() == 2 &&
+      (!IsSigned || VT.getScalarSizeInBits() > 2))
     return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
                        N->getVTList(), N0, N0);
 
   if (IsSigned) {
     // A 1 bit SMULO overflows if both inputs are 1.
     if (VT.getScalarSizeInBits() == 1) {
       SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, N1);
       return CombineTo(N, And,

llvm/test/CodeGen/AArch64/pr55644.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s
 
 define i1 @f(i2 %0) {
 ; CHECK-LABEL: f:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sbfx w8, w0, #0, #2
-; CHECK-NEXT:    add w8, w8, w8
-; CHECK-NEXT:    lsl w9, w8, #30
-; CHECK-NEXT:    cmp w8, w9, asr #30
+; CHECK-NEXT:    lsl w8, w8, #1
+; CHECK-NEXT:    neg w9, w8
+; CHECK-NEXT:    lsl w9, w9, #30
+; CHECK-NEXT:    cmn w8, w9, asr #30
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %2 = call { i2, i1 } @llvm.smul.with.overflow.i2(i2 %0, i2 -2)
   %3 = extractvalue { i2, i1 } %2, 1
   ret i1 %3
 }
 
 declare { i2, i1 } @llvm.smul.with.overflow.i2(i2, i2)