[MSVC, ARM64] Add __writex18 intrinsics

[steplong]

Summary

https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-170

void __writex18byte(unsigned long, unsigned char)
void __writex18word(unsigned long, unsigned short)
void __writex18dword(unsigned long, unsigned long)
void __writex18qword(unsigned long, unsigned __int64)

Given the lack of documentation of the intrinsics, we chose to align the offset with just
CharUnits::One() when calling IRBuilderBase::CreateAlignedStore().

[steplong]

The generated assembly is a little different from MSVC's:

MSVC                                                                          LLVM
__writex18byte:
                          strb    w1, [x18, x0]                             strb    w1, [x18, w0, uxtw]
__writex18word:
                          strh    w1, [x18, x0]                             strh    w1, [x18, w0, uxtw #1]
__writex18dword:
                          str     w1, [x18, x0]                              str     w1, [x18, w0, uxtw #2]
__writex18qword:
                          str     x1, [x18, x0]                              str     x1, [x18, w0, uxtw #3]

[steplong]

• Rebased it on top of main instead of D126024

[efriedma]

uxtw #3 makes me think you're not generating the right code... the zero-extension hopefully doesn't matter, but the shift is significant. Maybe should be generating getelementptr i8?

[steplong]

The assembly for LLVM now looks like:

__writex18byte:
                        strb    w1, [x18, w0, uxtw]
                        ret

__writex18word:
                        strh    w1, [x18, w0, uxtw]
                        ret

__writex18dword:
                        str     w1, [x18, w0, uxtw]
                        ret

__writex18qword:
                        str     x1, [x18, w0, uxtw]
                        ret

[rnk]

I was unable to find any documentation for the meaning of AArch64 addrspace(256), and I wasn't able to figure it out after studying the code in llvm/lib/Target/AArch64 for ten minutes or so. The change seems fine, but please add some documentation as a follow-up. X86 has some of its address spaces documented here, not that this is the best place:
https://llvm.org/docs/CodeGenerator.html#x86-address-spaces-supported

[steplong]

In D126023#3528077, @rnk wrote:

I was unable to find any documentation for the meaning of AArch64 addrspace(256), and I wasn't able to figure it out after studying the code in llvm/lib/Target/AArch64 for ten minutes or so. The change seems fine, but please add some documentation as a follow-up. X86 has some of its address spaces documented here, not that this is the best place:
https://llvm.org/docs/CodeGenerator.html#x86-address-spaces-supported

Hmm yea I don't think addrspace(256) is correct. I was using D31248 as a reference and addrspace(256) makes sense for that patch.

[steplong]

• Changed addrspace(256) to the default addrspace 0

[efriedma]

clang/lib/CodeGen/CGBuiltin.cpp

9977

I think I'd prefer just "CharUnits::One()", rather than getTypeAlignInChars(); given the lack of documentation, it's not clear if the offset is required to be properly aligned.

[steplong]

• Switch to CharUnits::One() instead of getContext().getTypeInChars()

[efriedma]

LGTM

clang/include/clang/Basic/BuiltinsAArch64.def

 TARGET_HEADER_BUILTIN(_WriteStatusReg, "viLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_AddressOfReturnAddress, "v*", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(__mulh,  "SLLiSLLiSLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(__umulh, "ULLiULLiULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(__break, "vi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
+TARGET_HEADER_BUILTIN(__writex18byte,  "vULiUc", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__writex18word,  "vULiUs", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__writex18dword, "vULiULi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__writex18qword, "vULiULLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+
 #undef BUILTIN
 #undef LANGBUILTIN
 #undef TARGET_HEADER_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

if (IsSigned) {
       MulResult = Builder.CreateNUWMul(LHS, RHS);
       HigherBits = Builder.CreateLShr(MulResult, 64);
     }
     HigherBits = Builder.CreateIntCast(HigherBits, ResType, IsSigned);
 
     return HigherBits;
   }
 
+  if (BuiltinID == AArch64::BI__writex18byte ||
+      BuiltinID == AArch64::BI__writex18word ||
+      BuiltinID == AArch64::BI__writex18dword ||
+      BuiltinID == AArch64::BI__writex18qword) {
+    llvm::Type *IntTy = ConvertType(E->getArg(1)->getType());
+
+    // Read x18 as byte ptr, word ptr, dword ptr, or qword ptr
+    LLVMContext &Context = CGM.getLLVMContext();
+    llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "x18")};
+    llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+    llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+    llvm::Function *F =
+        CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+    llvm::Value *X18 = Builder.CreateCall(F, Metadata);
+    X18 = Builder.CreateIntToPtr(X18, llvm::PointerType::get(IntTy, 256));
+
+    // Store val at x18 + offset
+    Value *Offset = Builder.CreateZExt(EmitScalarExpr(E->getArg(0)), Int64Ty);
+    Value *Ptr = Builder.CreateGEP(IntTy, X18, Offset);
+    Value *Val = EmitScalarExpr(E->getArg(1));
+    StoreInst *Store = Builder.CreateAlignedStore(
+        Val, Ptr, getContext().getTypeAlignInChars(E->getType()));
+    return Store;
+  }
+
   // Handle MSVC intrinsics before argument evaluation to prevent double
   // evaluation.
   if (Optional<MSVCIntrin> MsvcIntId = translateAarch64ToMsvcIntrin(BuiltinID))
     return EmitMSVCBuiltinExpr(*MsvcIntId, E);
 
   // Find out if any arguments are required to be integer constant
   // expressions.
   unsigned ICEArguments = 0;

clang/lib/Headers/intrin.h

 unsigned short __cdecl _byteswap_ushort(unsigned short val);
 unsigned long __cdecl _byteswap_ulong (unsigned long val);
 unsigned __int64 __cdecl _byteswap_uint64(unsigned __int64 val);
 
 __int64 __mulh(__int64 __a, __int64 __b);
 unsigned __int64 __umulh(unsigned __int64 __a, unsigned __int64 __b);
 
 void __break(int);
+
+void __writex18byte(unsigned long offset, unsigned char data);
+void __writex18word(unsigned long offset, unsigned short data);
+void __writex18dword(unsigned long offset, unsigned long data);
+void __writex18qword(unsigned long offset, unsigned __int64 data);
 #endif
 
 /*----------------------------------------------------------------------------*\
 |* Privileged intrinsics
 \*----------------------------------------------------------------------------*/
 #if defined(__i386__) || defined(__x86_64__)
 static __inline__ unsigned __int64 __DEFAULT_FN_ATTRS
 __readmsr(unsigned long __register) {

clang/test/CodeGen/arm64-microsoft-intrinsics.c

unsigned __int64 check__getReg(void) {
   unsigned volatile __int64 reg;
   reg = __getReg(18);
   reg = __getReg(31);
   return reg;
 }
 
 // CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
 // CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+
+void check__writex18byte(unsigned long offset, unsigned char data) {
+  __writex18byte(offset, data);
+}
+
+// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i8, align 1
+// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSVC: store i8 %data, i8* %[[DATA_ADDR]], align 1
+// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i8 addrspace(256)*
+// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, i8 addrspace(256)* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSVC: %[[DATA:.*]] = load i8, i8* %[[DATA_ADDR]], align 1
+// CHECK-MSVC: store i8 %[[DATA]], i8 addrspace(256)* %[[PTR]], align 1
+
+void check__writex18word(unsigned long offset, unsigned short data) {
+  __writex18word(offset, data);
+}
+
+// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i16, align 2
+// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSVC: store i16 %data, i16* %[[DATA_ADDR]], align 2
+// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i16 addrspace(256)*
+// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSVC: %[[PTR:.*]] = getelementptr i16, i16 addrspace(256)* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSVC: %[[DATA:.*]] = load i16, i16* %[[DATA_ADDR]], align 2
+// CHECK-MSVC: store i16 %[[DATA]], i16 addrspace(256)* %[[PTR]], align 1
+
+void check__writex18dword(unsigned long offset, unsigned long data) {
+  __writex18dword(offset, data);
+}
+
+// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSVC: store i32 %data, i32* %[[DATA_ADDR]], align 4
+// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i32 addrspace(256)*
+// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSVC: %[[PTR:.*]] = getelementptr i32, i32 addrspace(256)* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSVC: %[[DATA:.*]] = load i32, i32* %[[DATA_ADDR]], align 4
+// CHECK-MSVC: store i32 %[[DATA]], i32 addrspace(256)* %[[PTR]], align 1
+
+void check__writex18qword(unsigned long offset, unsigned __int64 data) {
+  __writex18qword(offset, data);
+}
+
+// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i64, align 8
+// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSVC: store i64 %data, i64* %[[DATA_ADDR]], align 8
+// CHECK-MSVC: store i32 %offset, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to i64 addrspace(256)*
+// CHECK-MSVC: %[[OFFSET:.*]] = load i32, i32* %[[OFFSET_ADDR]], align 4
+// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSVC: %[[PTR:.*]] = getelementptr i64, i64 addrspace(256)* %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSVC: %[[DATA:.*]] = load i64, i64* %[[DATA_ADDR]], align 8
+// CHECK-MSVC: store i64 %[[DATA]], i64 addrspace(256)* %[[PTR]], align 1
+
 // CHECK-MSVC: ![[MD2]] = !{!"x18"}
 // CHECK-MSVC: ![[MD3]] = !{!"sp"}