[RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[• pcwang-thead]

Summary

These two functions are described in RVV intrinsics doc
to read/write RVV CSRs. This matches what GCC does.

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

1511

Do we need gnu_inline and artificial? The only intrinsics headers that have them in clang are in ppc_wrappers. X86 uses __attribute__((__always_inline__, __nodebug__

1512

X86 and arm_neon.h uses double underscore prefixes on all variables in intrinsic headers to reduce the chance of a collision with a user having a macro with the same name.

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1511

I just made it the same as GCC.

1512

The function prototypes have already been defined in RVV intrinsics doc (https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-api.md#readwrite-urw-vector-csrs).

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

1512

I'm only refering to csr, rv and value. Those don't need to match the intrinsics doc. They aren't visible to code using the header.

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1512

Oh I get it.

[• pcwang-thead]

Add double underscore to all variables.

[khchen]

please move those tests to test/CodeGen/RISCV/rvv-intrinsics and rename them without rvv- prefix.

clang/include/clang/Basic/riscv_vector.td

1511

Why do you think making it same as GCC is better than same as other targets in clang?

[• pcwang-thead]

• Rebase.
• move tests to test/CodeGen/RISCV/rvv-intrinsics.
• Update functions' attrs.

[• pcwang-thead]

Gentle ping.

[• pcwang-thead]

Ping.

[craig.topper]

LGTM

[• pcwang-thead]

Add REQUIRES to tests.

clang/include/clang/Basic/riscv_vector.td

let Name = NAME,
       }
       }] in {
         foreach s_p = suffixes_prototypes in {
           def : RVVBuiltin<s_p[0], s_p[1], type_range>;
         }
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vread_csr(enum RVV_CSR __csr) {
+  unsigned long __rv = 0;
+  switch (__csr) {
+    case RVV_VSTART:
+      __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
+      break;
+    case RVV_VXSAT:
+      __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
+      break;
+    case RVV_VXRM:
+      __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
+      break;
+    case RVV_VCSR:
+      __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
+      break;
+  }
+  return __rv;
+}
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
+  switch (__csr) {
+    case RVV_VSTART:
+      __asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ"(__value) : "memory");
+      break;
+    case RVV_VXSAT:
+      __asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
+      break;
+    case RVV_VXRM:
+      __asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
+      break;
+    case RVV_VCSR:
+      __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
+      break;
+  }
+}
+}] in
+def vread_vwrite_csr: RVVHeader;
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 
 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
 // and LMUL.
 let HeaderCode =
 [{
 #define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)

clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN:     | opt -S -O2 | FileCheck  %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}

clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN:     | opt -S -O2 | FileCheck  %s
+
+#include <riscv_vector.h>
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:    ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:    ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:    ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:    ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}