[InstCombine] Optimize and of icmps with power-of-2 and contiguous masks

[jmciver]

Summary

Add an instance combine optimization for expressions of the form:

(%arg u< C1) & ((%arg & C2) != C2) -> %arg u< C2

Where C1 is a power-of-2 and C2 is a contiguous mask starting 1 bit below C1.

This commit resolves GitHub missed-optimization issue #54856.

All test have been verified with alive2.

Scalar tests:

• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_1610612736 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_2147483647 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_805306368 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1073741824_1073741823 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_7 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_6 + swapped

Vector tests:

• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147483647 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1610612736_2147483647 + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_2147483648_1610612736_2147483647
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_others + swapped
• @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_64_others + swapped

[jmciver]

All six reported failing tests (due to timeouts) are passing locally in my build/test environment.

[jmciver]

Fix capitzalation of function names containing ICMP

[jmciver]

Based on functionality of the optimization I believe foldLogOpOfMaskedICmps to be a reasonable location. However, it maybe better to create a new function and call it from InstCombinerImpl::foldAndOrOfICmps based on the following.

The placement of the call to foldLogOpOfMaskedICmps_AllZeros_BMask_NotMixed_and_NotAllOnes in the function foldLogOpOfMaskedICmps breaks the consistency of the conditional testing based on the conjunction of left and right mask (see variable Mask line 586). It is possible to place calls to foldLogOpOfMaskedICmps_AllZeros_BMask_NotMixed_and_NotAllOnes in two locations in foldLogOpOfMaskedICmps:

• In function foldLogOpOfMaskedIcmpsAsymmetric called from conditional block Mask == 0 (line 593)
• In conditional block Mask & (Mask_NotAllZeros | BMask_NotAllOnes (line 655)

I opted against this due to readability.

Thanks in advance for any feedback!

[jmciver]

To reduce performance impact I am thinking that the call to foldLogOpOfMaskedICmps_AllZeros_BMask_NotMixed_and_NotAllOnes should be moved into a new function, foldPowerOf2AndWithLesserContinuous, and then call this function from foldAndOrOfICmps. This will help to keep the purpose of foldLogOpOfMaskedICmps clear and reduce the overhead by not testing for a less probable optimization early.

[RKSimon]

Please can you add vector test coverage - uniform / non-uniform cases and cases containing undef / poison elements

[jmciver]

Thanks @RKSimon! I will work on adding the additional tests.

[jmciver]

As per @RKSimon's feedback I have discovered a number of vector deficiencies in my implementation.

From reading https://developers.redhat.com/articles/2022/12/20/how-contribute-llvm# (which is excellent) I have a better understanding of how to structure this patch. I am currently working on further vector test case generation and will post it as a parent to this patch in the next day or so.

[jmciver]

Add support for vectors:

• C1 supports splat vectors with poison/undef.
• C2 supports vectors with unique elements.

[jmciver]

Fix no change test case updated in D143044

[jmciver]

Update icmp-logical.ll test names as per recommendation in D143044

[jmciver]

ping

[goldstein.w.n]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

502

Its a bit hard to follow the cases, can you add a comment specifying the transformation being done at each non nullptr return.

535

remove empty line.

[jmciver]

Add comments to each non nullptr conditional.

Refactor leading ones and zeros comparison to use equality operator.

[jmciver]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

502

Thanks for taking the time to review. Let me know if you think the comments help.

[jmciver]

Rebase onto latest main.

[jmciver]

Added Alive2 URLs to patch summary.

[goldstein.w.n]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

484

Can you be explicit about what you are transforming this into (ult).

Also shouldn't it be (icmp (A & B) == 0) & (icmp (A & D) != E)?

489

C is unused AFAICT.

494

As a TODO (or here if you want to) you could also do:

`(icmp (A & B) == B) & (icmp (A & D) == D)` -> `(icmp (A & (B | D) == (B | D)`

https://alive2.llvm.org/ce/z/sFcvJP

543

Can you add some tests with undef elements.

Also if undef is allowed in the non-vec case as well, this check and the scalar one could be done with a lambda.

[jmciver]

Resolving feedback items identified by @goldstein.w.n

In function foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous:

• Improved explicitness of target transformation in function comment
• Removed unused function parameter
• Added splat vector test using undef
• Refactored test for compatibility into a lambda function

[jmciver]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

494

This maybe already handled, but let me know if I am missing something:

https://godbolt.org/z/WqnveefxP

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp#L577

543

I added tests using undef splat vectors.

The conversion to a lambda is much cleaner. I have enabled support for undef/poison support in the scalar case. However, testing of this transformation using scalar undef or poison enables an earlier optimization path:

https://godbolt.org/z/7c87ba45v

The following Alive2 output show the scalar use of undef and poison with this transformation to be correct:

https://alive2.llvm.org/ce/z/9_eQny

[goldstein.w.n]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

494

You're right, for some reason thought it wasn't being handled.

535

nit(style): i -> I

543

Thanks. Just FYI, you can do multiple proofs in the same link by postfixing 'src' with either '\d+' or '_<desc>' i.e:
https://godbolt.org/z/M5eK16Ess

549

I think it would be clearer to organize this as follows:

if(IsVec) {
foreach(B, D, E) {
if(!isReducible) { return nullptr; }
}
}
else {
if(!isReducible) { return nullptr; }
}
return ICmpInst(ULT, A, D);

[jmciver]

Refactor scalar and vector tests to emit icmp from one location

Prior to this update foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous
returned icmp expressions from two locations. Acceptance is now handled at the
end of the function resulting in a single location for icmp emission.

[jmciver]

Refactor scalar and vector tests to emit icmp from one location

Prior to this update foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous
returned icmp expressions from two locations. Acceptance is now handled at the
end of the function resulting in a single location for icmp emission.

[jmciver]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

543

Thanks for the Godbolt pointer!

549

I agree that is much cleaner. I have refactored accordingly. I added a comment to the function header stating that parameter B supports masking.

[goldstein.w.n]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

520

When do we transform to A & X eq/ne Y? I don't see that code.

543

nit: maybe:

} 
// Test scalar type arguments for conversion.    
else if (!isReducible(B, D, E)) {
     return nullptr;
}

Although given the LLVM style of '}' and 'else' on the same line its a bit out of place. No strong feelings so update if you see fit.

llvm/test/Transforms/InstCombine/icmp-logical.ll

2553 ↗

(On Diff #523192)

One more thing. Can you put the "fail" keyword somewhere in the tests that you expect no change in. Think it helps make it crystal clear exact what the is meant to happen.

[jmciver]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

520

That is a great question. The A & X eq/ne Y is emitted by the other transformations in foldLogOpOfMaskedICmps. When I started developing this patch I picked this location as the classifier function getMaskedTypeForICmpPair converted the source to the form:
(icmp ne (A & B), C) | (icmp qe (A & D), E). This is violation of the original intended use foldLogOpOfMaskedICmps at it is targetting ICMPs of the same operator, which fold to (icmp(A & X) ==/!= Y).

My current thinking is to move this fold into one of the other called functions in foldAndOrOfICmps (option 1) or create its own function and then call that from foldAndOrOfICmps (option 2).

Option 1: One possible function is foldIsPowerOf2, but it is specific to ctpop based expressions so I am hesitant to expand functionality.

Option 2: Create a function called foldIsNegativePowerOf2 (open to other names), which will attempt the transform X <u 2^n to (X & ~(2^n-1)) == 0 and then perform the subsequent tests for folding as seen in foldLogOpOfMaskedICmpsAllZerosBMaskNeqMixedOrContiguous. This removes the need for verbose aforementioned function name and provides a concise "does one thing well" function.

I think option 2 is probably the best path. I'll go ahead and implement and see what it looks like. If you have other ideas let me know!

llvm/test/Transforms/InstCombine/icmp-logical.ll

2553 ↗

(On Diff #523192)

I updated the names of tests that intentionally result in no change with a "_fail" postfix, see D143044.

[jmciver]

Add foldPowerOf2AndShiftedMask(...) and call from InstCombinerImpl::foldAndOrOfICmps(...)

Place the folding of ((icmp X u< P) & (icmp(X & M) != M)) or ((icmp X s> -1) &
(icmp(X & M) != M)) into (icmp X u< M) in foldPowerOf2AndShiftedMask(...). This
function attempts the transform of (X <u 2^n) into (X & ~(2^n-1)) == 0 or (icmp
X s> -1) into (icmp (X & SignMask) == 0) and then performs additional checks in
foldNegativePower2AndShiftedMask(...).

This patch delta removes prior implementation work from
foldLogOpOfMaskedICmps(...).

[goldstein.w.n]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

520

Bah, I had left reply unsent. Agree option 2 is better (and looks like thats what you did so great)

[goldstein.w.n]

LGTM. I'm not a maintainer so please wait 1/2 days to push so others may take a look.

[jmciver]

@goldstein.w.n thanks for taking the time to review.

I'll hold for a maintainers approval.

[goldstein.w.n]

In D125717#4358964, @jmciver wrote:

@goldstein.w.n thanks for taking the time to review.

I'll hold for a maintainers approval.

you probably want @nikic, hes the defacto maintainer of instcombine

[jmciver]

@nikic this patch is for #54856, which originated from @erikdesjardins.

This refinment is not triggered by building LLVM or anything of the components of the llvm-test-suite.

What are the appropriate next steps to gain InstCombine maintainer sign off?

Thanks in advance for your feedback.

[goldstein.w.n]

In D125717#4385553, @jmciver wrote:

@nikic this patch is for #54856, which originated from @erikdesjardins.

This refinment is not triggered by building LLVM or anything of the components of the llvm-test-suite.

What are the appropriate next steps to gain InstCombine maintainer sign off?

Thanks in advance for your feedback.

you might try @RKSimon.

Also to be fair I do end-to-end reviews (just not a maintainer) and believe this is okay to go out as is. If you don't hear back
soon I don't think it would be an issue to push.
I can run the zorg buildbot tests on this for you if it would help you feel more comfortable about it, or of course you can
wait as you see fit.

[jmciver]

@goldstein.w.n thanks for the reply.

I'll wait until Monday and then proceed to land the patch.

Is it customary to get approval for preceding NFC patches? If yes, can you please take a look at D143044?

Thanks,
John

[goldstein.w.n]

In D125717#4389718, @jmciver wrote:

@goldstein.w.n thanks for the reply.

I'll wait until Monday and then proceed to land the patch.

Is it customary to get approval for preceding NFC patches? If yes, can you please take a look at D143044?

No (ish). If you have push access I think its generally fine to push them with the implementation unless someone posts feedback on it.

Thanks,
John

llvm/include/llvm/IR/PatternMatch.h

struct is_any_apint {
   bool isValue(const APInt &C) { return true; }
 };
 /// Match an integer or vector with any integral constant.
 /// For vectors, this includes constants with undefined elements.
 inline cst_pred_ty<is_any_apint> m_AnyIntegralConstant() {
   return cst_pred_ty<is_any_apint>();
 }
 
+struct is_shifted_mask {
+  bool isValue(const APInt &C) { return C.isShiftedMask(); }
+};
+
+inline cst_pred_ty<is_shifted_mask> m_ShiftedMask() {
+  return cst_pred_ty<is_shifted_mask>();
+}
+
 struct is_all_ones {
   bool isValue(const APInt &C) { return C.isAllOnes(); }
 };
 /// Match an integer or vector with all bits set.
 /// For vectors, this includes constants with undefined elements.
 inline cst_pred_ty<is_all_ones> m_AllOnes() {
   return cst_pred_ty<is_all_ones>();
 }

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

if ((*BCst & ECst) != 0)
     return RHS;
   // Otherwise, LHS and RHS contradict and the whole expression becomes false
   // (or true if negated.) For example,
   // (icmp ne (A & 7), 0) & (icmp eq (A & 15), 8) -> false.
   // (icmp ne (A & 6), 0) & (icmp eq (A & 15), 8) -> false.
   return ConstantInt::get(LHS->getType(), !IsAnd);
 }
 
 /// Try to fold (icmp(A & B) ==/!= 0) &/| (icmp(A & D) ==/!= E) into a single
 /// (icmp(A & X) ==/!= Y), where the left-hand side and the right hand side
 /// aren't of the common mask pattern type.
 /// Also used for logical and/or, must be poison safe.
 static Value *foldLogOpOfMaskedICmpsAsymmetric(
     ICmpInst *LHS, ICmpInst *RHS, bool IsAnd, Value *A, Value *B, Value *C,
     Value *D, Value *E, ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
     unsigned LHSMask, unsigned RHSMask, InstCombiner::BuilderTy &Builder) {
   assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
          "Expected equality predicates for masked type of icmps.");
   // Handle Mask_NotAllZeros-BMask_Mixed cases.
   // (icmp ne/eq (A & B), C) &/| (icmp eq/ne (A & D), E), or
   // (icmp eq/ne (A & B), C) &/| (icmp ne/eq (A & D), E)
   //    which gets swapped to
   //    (icmp ne/eq (A & D), E) &/| (icmp eq/ne (A & B), C).
   if (!IsAnd) {
     LHSMask = conjugateICmpMask(LHSMask);
     RHSMask = conjugateICmpMask(RHSMask);
   }
   if ((LHSMask & Mask_NotAllZeros) && (RHSMask & BMask_Mixed)) {
     if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
             LHS, RHS, IsAnd, A, B, C, D, E,
             PredL, PredR, Builder)) {
       return V;
     }
   } else if ((LHSMask & BMask_Mixed) && (RHSMask & Mask_NotAllZeros)) {
     if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
             RHS, LHS, IsAnd, A, D, E, B, C,
             PredR, PredL, Builder)) {
       return V;
     }
   }
   return nullptr;
 }
 
 /// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E)
 /// into a single (icmp(A & X) ==/!= Y).
 static Value *foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
                                      bool IsLogical,
                                      InstCombiner::BuilderTy &Builder) {
   Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr, *E = nullptr;
   ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate();
   std::optional<std::pair<unsigned, unsigned>> MaskPair =
       getMaskedTypeForICmpPair(A, B, C, D, E, LHS, RHS, PredL, PredR);
   if (!MaskPair)
     return nullptr;
   assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
          "Expected equality predicates for masked type of icmps.");
   unsigned LHSMask = MaskPair->first;
   unsigned RHSMask = MaskPair->second;
   unsigned Mask = LHSMask & RHSMask;
   if (Mask == 0) {
     // Even if the two sides don't share a common pattern, check if folding can
     // still happen.
     if (Value *V = foldLogOpOfMaskedICmpsAsymmetric(
             LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask,
             Builder))
       return V;
     return nullptr;
   }
 
   // In full generality:
   //     (icmp (A & B) Op C) | (icmp (A & D) Op E)
   // ==  ![ (icmp (A & B) !Op C) & (icmp (A & D) !Op E) ]
   //
   // If the latter can be converted into (icmp (A & X) Op Y) then the former is
   // equivalent to (icmp (A & X) !Op Y).
   //
   // Therefore, we can pretend for the rest of this function that we're dealing
   // with the conjunction, provided we flip the sense of any comparisons (both
   // input and output).
 
   // In most cases we're going to produce an EQ for the "&&" case.
   ICmpInst::Predicate NewCC = IsAnd ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE;
if (!JoinedByAnd && match(Cmp0, m_ICmp(Pred0, m_Value(X), m_ZeroInt())) &&
                          m_SpecificInt(1))) &&
       Pred0 == ICmpInst::ICMP_EQ && Pred1 == ICmpInst::ICMP_UGT) {
     Value *CtPop = Cmp1->getOperand(0);
     return Builder.CreateICmpNE(CtPop, ConstantInt::get(CtPop->getType(), 1));
   }
   return nullptr;
 }
 
+/// Try to fold (icmp(A & B) == 0) & (icmp(A & D) != E) into (icmp A u< D) iff
+/// B is a contiguous set of ones starting from the most significant bit
+/// (negative power of 2), D and E are equal, and D is a contiguous set of ones
+/// starting at the most significant zero bit in B. Parameter B supports masking
+/// using undef/poison in either scalar or vector values.
+static Value *foldNegativePower2AndShiftedMask(
+    Value *A, Value *B, Value *D, Value *E, ICmpInst::Predicate PredL,
+    ICmpInst::Predicate PredR, InstCombiner::BuilderTy &Builder) {
+  assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
+         "Expected equality predicates for masked type of icmps.");
+  if (PredL != ICmpInst::ICMP_EQ || PredR != ICmpInst::ICMP_NE)
+    return nullptr;
+
+  if (!match(B, m_NegatedPower2()) || !match(D, m_ShiftedMask()) ||
+      !match(E, m_ShiftedMask()))
+    return nullptr;
+
+  // Test scalar arguments for conversion. B has been validated earlier to be a
+  // negative power of two and thus is guaranteed to have one or more contiguous
+  // ones starting from the MSB followed by zero or more contiguous zeros. D has
+  // been validated earlier to be a shifted set of one or more contiguous ones.
+  // In order to match, B leading ones and D leading zeros should be equal. The
+  // predicate that B be a negative power of 2 prevents the condition of there
+  // ever being zero leading ones. Thus 0 == 0 cannot occur. The predicate that
+  // D always be a shifted mask prevents the condition of D equaling 0. This
+  // prevents matching the condition where B contains the maximum number of
+  // leading one bits (-1) and D contains the maximum number of leading zero
+  // bits (0).
+  auto isReducible = [](const Value *B, const Value *D, const Value *E) {
+    const APInt *BCst, *DCst, *ECst;
+    return match(B, m_APIntAllowUndef(BCst)) && match(D, m_APInt(DCst)) &&
+           match(E, m_APInt(ECst)) && *DCst == *ECst &&
+           (isa<UndefValue>(B) ||
+            (BCst->countLeadingOnes() == DCst->countLeadingZeros()));
+  };
+
+  // Test vector type arguments for conversion.
+  if (const auto *BVTy = dyn_cast<VectorType>(B->getType())) {
+    const auto *BFVTy = dyn_cast<FixedVectorType>(BVTy);
+    const auto *BConst = dyn_cast<Constant>(B);
+    const auto *DConst = dyn_cast<Constant>(D);
+    const auto *EConst = dyn_cast<Constant>(E);
+
+    if (!BFVTy || !BConst || !DConst || !EConst)
+      return nullptr;
+
+    for (unsigned I = 0; I != BFVTy->getNumElements(); ++I) {
+      const auto *BElt = BConst->getAggregateElement(I);
+      const auto *DElt = DConst->getAggregateElement(I);
+      const auto *EElt = EConst->getAggregateElement(I);
+
+      if (!BElt || !DElt || !EElt)
+        return nullptr;
+      if (!isReducible(BElt, DElt, EElt))
+        return nullptr;
+    }
+  } else {
+    // Test scalar type arguments for conversion.
+    if (!isReducible(B, D, E))
+      return nullptr;
+  }
+  return Builder.CreateICmp(ICmpInst::ICMP_ULT, A, D);
+}
+
+/// Try to fold ((icmp X u< P) & (icmp(X & M) != M)) or ((icmp X s> -1) &
+/// (icmp(X & M) != M)) into (icmp X u< M). Where P is a power of 2, M < P, and
+/// M is a contiguous shifted mask starting at the right most significant zero
+/// bit in P. SGT is supported as when P is the largest representable power of
+/// 2, an earlier optimization converts the expression into (icmp X s> -1).
+/// Parameter P supports masking using undef/poison in either scalar or vector
+/// values.
+static Value *foldPowerOf2AndShiftedMask(ICmpInst *Cmp0, ICmpInst *Cmp1,
+                                         bool JoinedByAnd,
+                                         InstCombiner::BuilderTy &Builder) {
+  if (!JoinedByAnd)
+    return nullptr;
+  Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr, *E = nullptr;
+  ICmpInst::Predicate CmpPred0 = Cmp0->getPredicate(),
+                      CmpPred1 = Cmp1->getPredicate();
+  // Assuming P is a 2^n, getMaskedTypeForICmpPair will normalize (icmp X u<
+  // 2^n) into (icmp (X & ~(2^n-1)) == 0) and (icmp X s> -1) into (icmp (X &
+  // SignMask) == 0).
+  std::optional<std::pair<unsigned, unsigned>> MaskPair =
+      getMaskedTypeForICmpPair(A, B, C, D, E, Cmp0, Cmp1, CmpPred0, CmpPred1);
+  if (!MaskPair)
+    return nullptr;
+
+  const auto compareBMask = BMask_NotMixed | BMask_NotAllOnes;
+  unsigned CmpMask0 = MaskPair->first;
+  unsigned CmpMask1 = MaskPair->second;
+  if ((CmpMask0 & Mask_AllZeros) && (CmpMask1 == compareBMask)) {
+    if (Value *V = foldNegativePower2AndShiftedMask(A, B, D, E, CmpPred0,
+                                                    CmpPred1, Builder))
+      return V;
+  } else if ((CmpMask0 == compareBMask) && (CmpMask1 & Mask_AllZeros)) {
+    if (Value *V = foldNegativePower2AndShiftedMask(A, D, B, C, CmpPred1,
+                                                    CmpPred0, Builder))
+      return V;
+  }
+  return nullptr;
+}
+
 /// Commuted variants are assumed to be handled by calling this function again
 /// with the parameters swapped.
 static Value *foldUnsignedUnderflowCheck(ICmpInst *ZeroICmp,
                                          ICmpInst *UnsignedICmp, bool IsAnd,
                                          const SimplifyQuery &Q,
                                          InstCombiner::BuilderTy &Builder) {
   Value *ZeroCmpOp;
   ICmpInst::Predicate EqPred;
Value *InstCombinerImpl::foldAndOrOfICmps(ICmpInst *LHS, ICmpInst *RHS,
   // TODO: Add conjugated or fold, check whether it is safe for logical and/or.
   if (IsAnd && !IsLogical)
     if (Value *V = foldSignedTruncationCheck(LHS, RHS, I, Builder))
       return V;
 
   if (Value *V = foldIsPowerOf2(LHS, RHS, IsAnd, Builder))
     return V;
 
+  if (Value *V = foldPowerOf2AndShiftedMask(LHS, RHS, IsAnd, Builder))
+    return V;
+
   // TODO: Verify whether this is safe for logical and/or.
   if (!IsLogical) {
     if (Value *X = foldUnsignedUnderflowCheck(LHS, RHS, IsAnd, Q, Builder))
       return X;
     if (Value *X = foldUnsignedUnderflowCheck(RHS, LHS, IsAnd, Q, Builder))
       return X;
   }
 

llvm/test/Transforms/InstCombine/icmp-power2-and-icmp-shifted-mask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes=instcombine -S -o - %s | FileCheck %s
 
 ; Issue #54856
 
 ; ((X u< 0x8000000) & ((X & 0x60000000) != 0x60000000)) -> X u< 0x60000000
 define i1 @icmp_power2_and_icmp_shifted_mask_2147483648_1610612736(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_2147483648_1610612736(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 1610612736
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1610612736
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 2147483648
   %t2 = and i32 %x, 1610612736
   %t3 = icmp ne i32 %t2, 1610612736
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_1610612736(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_1610612736(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 1610612736
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1610612736
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 2147483648
   %t2 = and i32 %x, 1610612736
   %t3 = icmp ne i32 %t2, 1610612736
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
 
 ; ((X u< 0x8000000) & ((X & 0x7FFFFFFF) != 0x7FFFFFFF)) -> X u< 0x7FFFFFFF
 define i1 @icmp_power2_and_icmp_shifted_mask_2147483648_2147483647(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_2147483648_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 2147483647
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 2147483647
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 2147483648
   %t2 = and i32 %x, 2147483647
   %t3 = icmp ne i32 %t2, 2147483647
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_2147483647(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 2147483647
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 2147483647
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 2147483648
   %t2 = and i32 %x, 2147483647
   %t3 = icmp ne i32 %t2, 2147483647
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
 
 ; ((X u< 0x4000000) & ((X & 0x30000000) != 0x30000000)) -> X u< 0x30000000
 define i1 @icmp_power2_and_icmp_shifted_mask_2147483648_805306368(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_2147483648_805306368(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 805306368
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 805306368
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 805306368
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 1073741824
   %t2 = and i32 %x, 805306368
   %t3 = icmp ne i32 %t2, 805306368
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_805306368(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_805306368(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 805306368
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 805306368
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 805306368
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 1073741824
   %t2 = and i32 %x, 805306368
   %t3 = icmp ne i32 %t2, 805306368
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
 
 ; ((X u< 0x40000000) & ((X & 0x3FFFFFFF) != 0x3FFFFFFF)) -> X u< 0x3FFFFFFF
 define i1 @icmp_power2_and_icmp_shifted_mask_1073741824_1073741823(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_1073741824_1073741823(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 1073741823
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1073741823
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 1073741824
   %t2 = and i32 %x, 1073741823
   %t3 = icmp ne i32 %t2, 1073741823
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @icmp_power2_and_icmp_shifted_mask_swapped_1073741824_1073741823(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_1073741824_1073741823(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 1073741823
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 1073741823
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 1073741824
   %t2 = and i32 %x, 1073741823
   %t3 = icmp ne i32 %t2, 1073741823
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
 
 ; ((X u< 8) & ((X & 7) != 7)) -> X u< 7
 define i1 @icmp_power2_and_icmp_shifted_mask_8_7(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_7(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 7
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 7
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 8
   %t2 = and i32 %x, 7
   %t3 = icmp ne i32 %t2, 7
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_7(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_7(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 7
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 7
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 8
   %t2 = and i32 %x, 7
   %t3 = icmp ne i32 %t2, 7
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
 
 ; ((X u< 8) & ((X & 6) != 6)) -> X u< 6
 define i1 @icmp_power2_and_icmp_shifted_mask_8_6(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_6(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 6
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 6
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 8
   %t2 = and i32 %x, 6
   %t3 = icmp ne i32 %t2, 6
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_6(i32 %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_6(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[T2:%.*]] = and i32 [[X]], 6
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne i32 [[T2]], 6
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6
 ; CHECK-NEXT:    ret i1 [[T4]]
 ;
   %t1 = icmp ult i32 %x, 8
   %t2 = and i32 %x, 6
   %t3 = icmp ne i32 %t2, 6
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
;
   %t3 = icmp ne i32 %t2, 12
   %t4 = and i1 %t3, %t1
   ret i1 %t4
 }
 
 ; Vector of 1 reduction
 define <1 x i1> @icmp_power2_and_icmp_shifted_mask_vector_2147483648_2147483647(<1 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_2147483648_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], <i32 -1>
-; CHECK-NEXT:    [[T2:%.*]] = and <1 x i32> [[X]], <i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <1 x i32> [[T2]], <i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <1 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], <i32 2147483647>
 ; CHECK-NEXT:    ret <1 x i1> [[T4]]
 ;
   %t1 = icmp ult <1 x i32> %x, <i32 2147483648>
   %t2 = and <1 x i32> %x, <i32 2147483647>
   %t3 = icmp ne <1 x i32> %t2, <i32 2147483647>
   %t4 = and <1 x i1> %t1, %t3
   ret <1 x i1> %t4
 }
 
 define <1 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_2147483647(<1 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], <i32 -1>
-; CHECK-NEXT:    [[T2:%.*]] = and <1 x i32> [[X]], <i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <1 x i32> [[T2]], <i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <1 x i1> [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], <i32 2147483647>
 ; CHECK-NEXT:    ret <1 x i1> [[T4]]
 ;
   %t1 = icmp ult <1 x i32> %x, <i32 2147483648>
   %t2 = and <1 x i32> %x, <i32 2147483647>
   %t3 = icmp ne <1 x i32> %t2, <i32 2147483647>
   %t4 = and <1 x i1> %t3, %t1
   ret <1 x i1> %t4
 }
 
 ; Vector of 2 reduction
 define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_2147483648_1610612736_2147483647(<2 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_2147483648_1610612736_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i1> [[T4]]
 ;
   %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>
   %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
   %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
   %t4 = and <2 x i1> %t1, %t3
   ret <2 x i1> %t4
 }
 
 define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_1610612736_2147483647(<2 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_1610612736_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i1> [[T4]]
 ;
   %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>
   %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
   %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
   %t4 = and <2 x i1> %t3, %t1
   ret <2 x i1> %t4
 }
 
 ; Vector of 2 reduction with splat containing poison
 define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_splat_poison_2147483648_1610612736_2147483647(<2 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_splat_poison_2147483648_1610612736_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 poison>
-; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i1> [[T4]]
 ;
   %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 poison>
   %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
   %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
   %t4 = and <2 x i1> %t1, %t3
   ret <2 x i1> %t4
 }
 
 define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_poison_2147483648_1610612736_2147483647(<2 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_poison_2147483648_1610612736_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 poison>
-; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i1> [[T4]]
 ;
   %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 poison>
   %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
   %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
   %t4 = and <2 x i1> %t3, %t1
   ret <2 x i1> %t4
 }
 
 ; Vector of 2 reduction with splat containing undef
 define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_splat_undef_2147483648_1610612736_2147483647(<2 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_splat_undef_2147483648_1610612736_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 undef>
-; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i1> [[T4]]
 ;
   %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 undef>
   %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
   %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
   %t4 = and <2 x i1> %t1, %t3
   ret <2 x i1> %t4
 }
 
 define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_undef_2147483648_1610612736_2147483647(<2 x i32> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_undef_2147483648_1610612736_2147483647(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 undef>
-; CHECK-NEXT:    [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i1> [[T4]]
 ;
   %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 undef>
   %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
   %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
   %t4 = and <2 x i1> %t3, %t1
   ret <2 x i1> %t4
 }
 
 ; Vector of 7 reduction
 define <7 x i1> @icmp_power2_and_icmp_shifted_mask_vector_128_others(<7 x i8> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_128_others(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
-; CHECK-NEXT:    [[T2:%.*]] = and <7 x i8> [[X]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
-; CHECK-NEXT:    [[T4:%.*]] = and <7 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
 ; CHECK-NEXT:    ret <7 x i1> [[T4]]
 ;
   %t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
   %t2 = and <7 x i8> %x, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
   %t3 = icmp ne <7 x i8> %t2, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
   %t4 = and <7 x i1> %t1, %t3
   ret <7 x i1> %t4
 }
 
 define <7 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_others(<7 x i8> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_others(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
-; CHECK-NEXT:    [[T2:%.*]] = and <7 x i8> [[X]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
-; CHECK-NEXT:    [[T4:%.*]] = and <7 x i1> [[T3]], [[T1]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
 ; CHECK-NEXT:    ret <7 x i1> [[T4]]
 ;
   %t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
   %t2 = and <7 x i8> %x, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
   %t3 = icmp ne <7 x i8> %t2, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
   %t4 = and <7 x i1> %t3, %t1
   ret <7 x i1> %t4
 }
 
 ; Vector of 6 reduction
 define <6 x i1> @icmp_power2_and_icmp_shifted_mask_vector_64_others(<6 x i8> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_64_others(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
-; CHECK-NEXT:    [[T2:%.*]] = and <6 x i8> [[X]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
-; CHECK-NEXT:    [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
 ; CHECK-NEXT:    ret <6 x i1> [[T4]]
 ;
   %t1 = icmp ult <6 x i8> %x, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
   %t2 = and <6 x i8> %x, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
   %t3 = icmp ne <6 x i8> %t2, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
   %t4 = and <6 x i1> %t1, %t3
   ret <6 x i1> %t4
 }
 
 define <6 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_64_others(<6 x i8> %x) {
 ; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_64_others(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
-; CHECK-NEXT:    [[T2:%.*]] = and <6 x i8> [[X]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
-; CHECK-NEXT:    [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]]
+; CHECK-NEXT:    [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
 ; CHECK-NEXT:    ret <6 x i1> [[T4]]
 ;
   %t1 = icmp ult <6 x i8> %x, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
   %t2 = and <6 x i8> %x, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
   %t3 = icmp ne <6 x i8> %t2, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
   %t4 = and <6 x i1> %t1, %t3
   ret <6 x i1> %t4
 }