[AArch64] Add missing HasNEON predicates to int->float patterns

[arichardson]

Summary

I was trying to compile code with -march=+nosimd and hit various
instruction predicate verification errors, this patch should address the
ones I saw in integer to floating-pointer conversions.

I noticed that for signed conversions, some non-NEON instruction sequences
are shorter. I don't know if the longer one is still faster on current
architectures (the patterns date back to the initial backend import)

[dmgreen]

I noticed that for signed conversions, some non-NEON instruction sequences are shorter. I don't know if the longer one is still faster on current architectures (the patterns date back to the initial backend import)

Yeah I believe the general idea was that going GRP->FPR is slower than keeping everything inside FPR registers. I was recently informed that those patterns should probably be guarded using the UseAlternateSExtLoadCVTF32 in the same way as other related patterns are.

This change LGTM though, in terms of NEON support. Thanks.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

5027–5028

Perhaps just extend the previous HasNeon block? I'm not sure that's clearer though.

5114

Having a comment, // Predicates = [HasNEON] might be useful.

[arichardson]

Regen with D125405

[arichardson]

Drop --asm-show-inst

[arichardson]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

5027–5028

Oh yes that is much better, somehow missed that..

[dmgreen]

Cheers

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : Pat<(f32 (any_uint_to_fp (i32 (any_fp_to_uint f32:$Rn)))),
           (UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>;
 
 let Predicates = [HasFullFP16] in {
 def : Pat<(f16 (any_sint_to_fp (i32 (any_fp_to_sint f16:$Rn)))),
           (SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>;
 def : Pat<(f16 (any_uint_to_fp (i32 (any_fp_to_uint f16:$Rn)))),
           (UCVTFv1i16 (f16 (FCVTZUv1f16 f16:$Rn)))>;
 }
-}
-
 // If an integer is about to be converted to a floating point value,
 // just load it on the floating point unit.
 // Here are the patterns for 8 and 16-bits to float.
 // 8-bits -> float.
 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
                              SDPatternOperator loadop, Instruction UCVTF,
                              ROAddrMode ro, Instruction LDRW, Instruction LDRX,
                              SubRegIndex sub> {
   def : Pat<(DstTy (uint_to_fp (SrcTy
def : Pat <(f64 (uint_to_fp (i32
            (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
                           (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
 def : Pat <(f64 (uint_to_fp (i32
                   (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
            (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
                           (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
 // 64-bits -> double are handled in target specific dag combine:
 // performIntToFpCombine.
+} // let Predicates = [HasNEON]
 
 //===----------------------------------------------------------------------===//
 // Advanced SIMD three different-sized vector instructions.
 //===----------------------------------------------------------------------===//
 
 defm ADDHN  : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
 defm SUBHN  : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
: Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
                                   (SSHLLv8i8_shift
                                     (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
                                         INST,
                                         bsub),
                                     0),
                                   dsub)),
                                0),
                              ssub)))>,
-    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
+    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;
 
 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
                           (LDRBroW  GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
                           (LDRBroX  GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
                           (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
                           (LDURBi GPR64sp:$Rn, simm9:$offset)>;
 
 // 16-bits -> float. 1 size step-up.
 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
   : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
         (SCVTFv1i32 (f32 (EXTRACT_SUBREG
                             (SSHLLv4i16_shift
                                 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
                                   INST,
                                   hsub),
                                 0),
-                            ssub)))>, Requires<[NotForCodeSize]>;
+                            ssub)))>, Requires<[NotForCodeSize, HasNEON]>;
 
 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
                            (LDRHroW   GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
                            (LDRHroX   GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
                            (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
: Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
                                     (SSHLLv4i16_shift
                                       (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
                                         INST,
                                         hsub),
                                      0),
                                    dsub)),
                                0),
                              dsub)))>,
-    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
+    Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;
 
 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
                            (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
                            (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
                            (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
                            (LDURHi GPR64sp:$Rn, simm9:$offset)>;
 // 32-bits -> double. 1 size step-up.
 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
   : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
            (SCVTFv1i64 (f64 (EXTRACT_SUBREG
                               (SSHLLv2i32_shift
                                 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
                                   INST,
                                   ssub),
                                0),
-                             dsub)))>, Requires<[NotForCodeSize]>;
+                             dsub)))>, Requires<[NotForCodeSize, HasNEON]>;
 
 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
                            (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
                            (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
                            (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),

llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;; These test functions previously triggered the following error when emitting machine code:
 ;; LLVM ERROR: Attempting to emit UCVTFv1i64 instruction but the Feature_HasNEON predicate(s) are not met
 ; RUN: llc -mtriple=aarch64 -mattr=+neon,+fullfp16 < %s | FileCheck %s --check-prefixes=CHECK,NEON-ENABLED
 ; RUN: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 < %s | FileCheck %s --check-prefixes=CHECK,NEON-DISABLED
 ;; Emit an object file so that verifyPredicates is called (it is not used for ASM output).
-; RUNTODO: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 -o /dev/null %s --asm-show-inst -filetype=obj
+; RUN: llc -mtriple=aarch64 -mattr=-neon,+fullfp16 -o /dev/null %s --asm-show-inst -filetype=obj
 
 define double @ui8_to_double(i8* %i, float* %f) {
-; CHECK-LABEL: ui8_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr b0, [x0]
-; CHECK-NEXT:    ucvtf d0, d0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: ui8_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr b0, [x0]
+; NEON-ENABLED-NEXT:    ucvtf d0, d0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: ui8_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrb w8, [x0]
+; NEON-DISABLED-NEXT:    ucvtf d0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i8, i8* %i, align 1
   %conv = uitofp i8 %ld to double
   ret double %conv
 }
 
 define float @ui8_to_float(i8* %i, float* %f) {
-; CHECK-LABEL: ui8_to_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr b0, [x0]
-; CHECK-NEXT:    ucvtf s0, s0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: ui8_to_float:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr b0, [x0]
+; NEON-ENABLED-NEXT:    ucvtf s0, s0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: ui8_to_float:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrb w8, [x0]
+; NEON-DISABLED-NEXT:    ucvtf s0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i8, i8* %i, align 1
   %conv = uitofp i8 %ld to float
   ret float %conv
 }
 
 define half @ui8_to_half(i8* %i, half* %f) {
 ; CHECK-LABEL: ui8_to_half:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldrb w8, [x0]
 ; CHECK-NEXT:    ucvtf h0, w8
 ; CHECK-NEXT:    ret
 entry:
   %ld = load i8, i8* %i, align 1
   %conv = uitofp i8 %ld to half
   ret half %conv
 }
 
 define double @ui16_to_double(i16* %i, float* %f) {
-; CHECK-LABEL: ui16_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr h0, [x0]
-; CHECK-NEXT:    ucvtf d0, d0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: ui16_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr h0, [x0]
+; NEON-ENABLED-NEXT:    ucvtf d0, d0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: ui16_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrh w8, [x0]
+; NEON-DISABLED-NEXT:    ucvtf d0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = uitofp i16 %ld to double
   ret double %conv
 }
 
 define float @ui16_to_float(i16* %i, float* %f) {
-; CHECK-LABEL: ui16_to_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr h0, [x0]
-; CHECK-NEXT:    ucvtf s0, s0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: ui16_to_float:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr h0, [x0]
+; NEON-ENABLED-NEXT:    ucvtf s0, s0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: ui16_to_float:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrh w8, [x0]
+; NEON-DISABLED-NEXT:    ucvtf s0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = uitofp i16 %ld to float
   ret float %conv
 }
 
 define half @ui16_to_half(i16* %i, half* %f) {
 ; CHECK-LABEL: ui16_to_half:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldrh w8, [x0]
 ; CHECK-NEXT:    ucvtf h0, w8
 ; CHECK-NEXT:    ret
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = uitofp i16 %ld to half
   ret half %conv
 }
 
 define double @ui32_to_double(i32* %i, float* %f) {
-; CHECK-LABEL: ui32_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr s0, [x0]
-; CHECK-NEXT:    ucvtf d0, d0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: ui32_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr s0, [x0]
+; NEON-ENABLED-NEXT:    ucvtf d0, d0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: ui32_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldr w8, [x0]
+; NEON-DISABLED-NEXT:    ucvtf d0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i32, i32* %i, align 1
   %conv = uitofp i32 %ld to double
   ret double %conv
 }
 
 define float @ui32_to_float(i32* %i, float* %f) {
 ; NEON-ENABLED-LABEL: ui32_to_float:

 ; CHECK-NEXT:    ret
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = sitofp i16 %ld to double
   ret double %conv
 }
 
 define float @si16_to_float(i16* %i, float* %f) {
-; CHECK-LABEL: si16_to_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr h0, [x0]
-; CHECK-NEXT:    sshll v0.4s, v0.4h, #0
-; CHECK-NEXT:    scvtf s0, s0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: si16_to_float:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr h0, [x0]
+; NEON-ENABLED-NEXT:    sshll v0.4s, v0.4h, #0
+; NEON-ENABLED-NEXT:    scvtf s0, s0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: si16_to_float:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldrsh w8, [x0]
+; NEON-DISABLED-NEXT:    scvtf s0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = sitofp i16 %ld to float
   ret float %conv
 }
 
 define half @si16_to_half(i16* %i, half* %f) {
 ; CHECK-LABEL: si16_to_half:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldrsh w8, [x0]
 ; CHECK-NEXT:    scvtf h0, w8
 ; CHECK-NEXT:    ret
 entry:
   %ld = load i16, i16* %i, align 1
   %conv = sitofp i16 %ld to half
   ret half %conv
 }
 
 define double @si32_to_double(i32* %i, float* %f) {
-; CHECK-LABEL: si32_to_double:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldr s0, [x0]
-; CHECK-NEXT:    sshll v0.2d, v0.2s, #0
-; CHECK-NEXT:    scvtf d0, d0
-; CHECK-NEXT:    ret
+; NEON-ENABLED-LABEL: si32_to_double:
+; NEON-ENABLED:       // %bb.0: // %entry
+; NEON-ENABLED-NEXT:    ldr s0, [x0]
+; NEON-ENABLED-NEXT:    sshll v0.2d, v0.2s, #0
+; NEON-ENABLED-NEXT:    scvtf d0, d0
+; NEON-ENABLED-NEXT:    ret
+;
+; NEON-DISABLED-LABEL: si32_to_double:
+; NEON-DISABLED:       // %bb.0: // %entry
+; NEON-DISABLED-NEXT:    ldr w8, [x0]
+; NEON-DISABLED-NEXT:    scvtf d0, w8
+; NEON-DISABLED-NEXT:    ret
 entry:
   %ld = load i32, i32* %i, align 1
   %conv = sitofp i32 %ld to double
   ret double %conv
 }
 
 define float @si32_to_float(i32* %i, float* %f) {
 ; NEON-ENABLED-LABEL: si32_to_float: