[RISCV] Remove some TODOs in tests

[sunshaoce]

rebase

[asb]

LGTM - thanks for working through to remove these redundant comments (and fixing the missing fld/fsd/flw/fsw alias tests).

llvm/test/CodeGen/RISCV/double-br-fcmp.ll

 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uno(double %a, double %b) nounwind {
-; TODO: sltiu+bne -> beq
 ; RV32IFD-LABEL: br_fcmp_uno:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    feq.d a0, fa1, fa1
 ; RV32IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV32IFD-NEXT:    and a0, a1, a0
 ; RV32IFD-NEXT:    beqz a0, .LBB15_2

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uno(float %a, float %b) nounwind {
-; TODO: sltiu+bne -> beq
 ; RV32IF-LABEL: br_fcmp_uno:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    feq.s a0, fa1, fa1
 ; RV32IF-NEXT:    feq.s a1, fa0, fa0
 ; RV32IF-NEXT:    and a0, a1, a0
 ; RV32IF-NEXT:    beqz a0, .LBB15_2

 if.then:
   tail call void @abort()
   unreachable
 }
 
 ; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
 ; and RISCVInstrInfo::loadRegFromStackSlot
 define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
-; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
 ; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
 ; RV32IF:       # %bb.0: # %entry
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.w.x fs0, zero
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call dummy@plt

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uno(half %a, half %b) nounwind {
-; TODO: sltiu+bne -> beq
 ; RV32IZFH-LABEL: br_fcmp_uno:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV32IZFH-NEXT:    and a0, a1, a0
 ; RV32IZFH-NEXT:    beqz a0, .LBB15_2

llvm/test/MC/RISCV/rvd-aliases-valid.s

 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
 # RUN:     | llvm-objdump -d --mattr=+d - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 ##===----------------------------------------------------------------------===##
 ## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 ##===----------------------------------------------------------------------===##
 
-# TODO fld
-# TODO fsd
+# CHECK-INST: fld ft0, 0(a0)
+# CHECK-ALIAS:  fld ft0, 0(a0)
+fld f0, (a0)
+# CHECK-INST: fsd ft0, 0(a0)
+# CHECK-ALIAS: fsd ft0, 0(a0)
+fsd f0, (a0)
 
 # CHECK-INST: fsgnj.d ft0, ft1, ft1
 # CHECK-ALIAS: fmv.d ft0, ft1
 fmv.d f0, f1
 # CHECK-INST: fsgnjx.d ft1, ft2, ft2
 # CHECK-ALIAS: fabs.d ft1, ft2
 fabs.d f1, f2
 # CHECK-INST: fsgnjn.d ft2, ft3, ft3

llvm/test/MC/RISCV/rvf-aliases-valid.s

 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
 # RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 ##===----------------------------------------------------------------------===##
 ## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 ##===----------------------------------------------------------------------===##
 
-# TODO flw
-# TODO fsw
+# CHECK-INST: flw ft0, 0(a0)
+# CHECK-ALIAS:  flw ft0, 0(a0)
+flw f0, (a0)
+# CHECK-INST: fsw ft0, 0(a0)
+# CHECK-ALIAS: fsw ft0, 0(a0)
+fsw f0, (a0)
 
 # CHECK-INST: fsgnj.s ft0, ft1, ft1
 # CHECK-ALIAS: fmv.s ft0, ft1
 fmv.s f0, f1
 # CHECK-INST: fsgnjx.s ft1, ft2, ft2
 # CHECK-ALIAS: fabs.s ft1, ft2
 fabs.s f1, f2
 # CHECK-INST: fsgnjn.s ft2, ft3, ft3