[PowerPC] Fix PPCISD::STBRX selection issue on A2

[tingwang]

Summary

https://github.com/llvm/llvm-project/issues/55272 reported an error which appears to be one regression:

The troubled instruction was introduced for both P7 and A2 as below link shows:
https://github.com/llvm/llvm-project/commit/31d2956510b8484373fe244547b4f811430a28ff

However it seems below commit missed the A2 part and introduced the regression:
https://github.com/llvm/llvm-project/commit/fb4e44c4e7daaaa1d2776e76d43566b0db264f30

Referring to below page, it seems A2 should have FeatureISA2_06 in its feature list:
https://en.wikipedia.org/wiki/IBM_A2

Thus I'm proposing this fix. Please help comment, thanks!

[lkail]

The troubled instruction was introduced for both P7 and A2 as below link shows:
https://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20130325/169706.html

This link has been invalid.

[nemanjai]

In D125203#3499836, @lkail wrote:

The troubled instruction was introduced for both P7 and A2 as below link shows:
https://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20130325/169706.html

This link has been invalid.

Not sure what's going on there - the link works for me.

[nemanjai]

Why not also fix this in the front end so that we allow the builtin on the A2 CPU as well (since it's supported)?

[tingwang]

Update according to Nemanja's comment: add A2 to frontend isa-v206-instructions feature list, together with test case update.

[tingwang]

In D125203#3502433, @nemanjai wrote:

Why not also fix this in the front end so that we allow the builtin on the A2 CPU as well (since it's supported)?

Oh I missed that. Thank you for pointing out!

Just now updated the patch. However I didn't update the SemaFeatureCheck message to indicate the support on a2, since if people see this error message, it cannot be a2, and a2 does not easily fit into the message of err_ppc_builtin_only_on_arch. Hope this will not create problem.

[nemanjai]

In D125203#3502651, @tingwang wrote:

In D125203#3502433, @nemanjai wrote:

Why not also fix this in the front end so that we allow the builtin on the A2 CPU as well (since it's supported)?

Oh I missed that. Thank you for pointing out!

Just now updated the patch. However I didn't update the SemaFeatureCheck message to indicate the support on a2, since if people see this error message, it cannot be a2, and a2 does not easily fit into the message of err_ppc_builtin_only_on_arch. Hope this will not create problem.

I wouldn't worry about it. If we have to change this in the future because some implementation of the ISA that isn't pwr<N> needs to reference it, we can change it at that time.

LGTM.

clang/lib/Basic/Targets/PPC.cpp

Features["spe"] = llvm::StringSwitch<bool>(CPU)
                         .Case("e500", true)
                         .Default(false);
 
   Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
                                           .Case("ppc64le", true)
                                           .Case("pwr9", true)
                                           .Case("pwr8", true)
                                           .Case("pwr7", true)
+                                          .Case("a2", true)
                                           .Default(false);
 
   Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
                                           .Case("ppc64le", true)
                                           .Case("pwr9", true)
                                           .Case("pwr8", true)
                                           .Default(false);
 

clang/test/Driver/ppc-isa-features.cpp

 // RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr6 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR6
+// RUN: %clang -target powerpc64-unknown-unknown -mcpu=a2 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-A2
 // RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR7
 // RUN: %clang -target powerpc64le-unknown-unknown -mcpu=pwr8 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR8
 // RUN: %clang -target powerpc64-unknown-aix -mcpu=pwr9 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR9
 // RUN: %clang -target powerpc-unknown-aix -mcpu=pwr10 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR10
 
 // CHECK-PWR6: -isa-v206-instructions
 // CHECK-PWR6: -isa-v207-instructions
 // CHECK-PWR6: -isa-v30-instructions
 
+// CHECK-A2: +isa-v206-instructions
+// CHECK-A2: -isa-v207-instructions
+// CHECK-A2: -isa-v30-instructions
+
 // CHECK-PWR7: +isa-v206-instructions
 // CHECK-PWR7: -isa-v207-instructions
 // CHECK-PWR7: -isa-v30-instructions
 
 // CHECK-PWR8: +isa-v207-instructions
 // CHECK-PWR8: -isa-v30-instructions
 
 // CHECK-PWR9: +isa-v207-instructions

llvm/lib/Target/PowerPC/PPC.td

def : ProcessorModel<"e5500", PPCE5500Model,
                    FeatureISEL, FeatureMFTB]>;
 def : ProcessorModel<"a2", PPCA2Model,
                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
-                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
+                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
+                   FeatureISA2_06]>;
 def : ProcessorModel<"pwr3", G5Model,
                   [DirectivePwr3, FeatureAltivec,
                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
                    FeatureSTFIWX, Feature64Bit]>;
 def : ProcessorModel<"pwr4", G5Model,
                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;

llvm/test/CodeGen/PowerPC/bswap-load-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--     -mcpu=ppc32 | FileCheck %s --check-prefixes=X32
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--     -mcpu=pwr7  | FileCheck %s --check-prefixes=X32,PWR7_32
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=ppc64 | FileCheck %s --check-prefixes=X64
 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=pwr7  | FileCheck %s --check-prefixes=PWR7_64
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=a2    | FileCheck %s --check-prefixes=A2_64
 
 
 define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
 ; X32-LABEL: STWBRX:
 ; X32:       # %bb.0:
 ; X32-NEXT:    stwbrx r3, r4, r5
 ; X32-NEXT:    blr
 ;
 ; X64-LABEL: STWBRX:
 ; X64:       # %bb.0:
 ; X64-NEXT:    extsw r5, r5
 ; X64-NEXT:    stwbrx r3, r4, r5
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: STWBRX:
 ; PWR7_64:       # %bb.0:
 ; PWR7_64-NEXT:    extsw r5, r5
 ; PWR7_64-NEXT:    stwbrx r3, r4, r5
 ; PWR7_64-NEXT:    blr
+;
+; A2_64-LABEL: STWBRX:
+; A2_64:       # %bb.0:
+; A2_64-NEXT:    extsw r5, r5
+; A2_64-NEXT:    stwbrx r3, r4, r5
+; A2_64-NEXT:    blr
   %tmp1 = getelementptr i8, i8* %ptr, i32 %off
   %tmp1.upgrd.1 = bitcast i8* %tmp1 to i32*
   %tmp13 = tail call i32 @llvm.bswap.i32( i32 %i )
   store i32 %tmp13, i32* %tmp1.upgrd.1
   ret void
 }
 
 define i32 @LWBRX(i8* %ptr, i32 %off) {
 ; X32-LABEL: LWBRX:
 ; X32:       # %bb.0:
 ; X32-NEXT:    lwbrx r3, r3, r4
 ; X32-NEXT:    blr
 ;
 ; X64-LABEL: LWBRX:
 ; X64:       # %bb.0:
 ; X64-NEXT:    extsw r4, r4
 ; X64-NEXT:    lwbrx r3, r3, r4
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: LWBRX:
 ; PWR7_64:       # %bb.0:
 ; PWR7_64-NEXT:    extsw r4, r4
 ; PWR7_64-NEXT:    lwbrx r3, r3, r4
 ; PWR7_64-NEXT:    blr
+;
+; A2_64-LABEL: LWBRX:
+; A2_64:       # %bb.0:
+; A2_64-NEXT:    extsw r4, r4
+; A2_64-NEXT:    lwbrx r3, r3, r4
+; A2_64-NEXT:    blr
   %tmp1 = getelementptr i8, i8* %ptr, i32 %off
   %tmp1.upgrd.2 = bitcast i8* %tmp1 to i32*
   %tmp = load i32, i32* %tmp1.upgrd.2
   %tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp )
   ret i32 %tmp14
 }
 
 define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
 ; X32-LABEL: STHBRX:
 ; X32:       # %bb.0:
 ; X32-NEXT:    sthbrx r3, r4, r5
 ; X32-NEXT:    blr
 ;
 ; X64-LABEL: STHBRX:
 ; X64:       # %bb.0:
 ; X64-NEXT:    extsw r5, r5
 ; X64-NEXT:    sthbrx r3, r4, r5
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: STHBRX:
 ; PWR7_64:       # %bb.0:
 ; PWR7_64-NEXT:    extsw r5, r5
 ; PWR7_64-NEXT:    sthbrx r3, r4, r5
 ; PWR7_64-NEXT:    blr
+;
+; A2_64-LABEL: STHBRX:
+; A2_64:       # %bb.0:
+; A2_64-NEXT:    extsw r5, r5
+; A2_64-NEXT:    sthbrx r3, r4, r5
+; A2_64-NEXT:    blr
   %tmp1 = getelementptr i8, i8* %ptr, i32 %off
   %tmp1.upgrd.3 = bitcast i8* %tmp1 to i16*
   %tmp5 = call i16 @llvm.bswap.i16( i16 %s )
   store i16 %tmp5, i16* %tmp1.upgrd.3
   ret void
 }
 
 define i16 @LHBRX(i8* %ptr, i32 %off) {
 ; X32-LABEL: LHBRX:
 ; X32:       # %bb.0:
 ; X32-NEXT:    lhbrx r3, r3, r4
 ; X32-NEXT:    blr
 ;
 ; X64-LABEL: LHBRX:
 ; X64:       # %bb.0:
 ; X64-NEXT:    extsw r4, r4
 ; X64-NEXT:    lhbrx r3, r3, r4
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: LHBRX:
 ; PWR7_64:       # %bb.0:
 ; PWR7_64-NEXT:    extsw r4, r4
 ; PWR7_64-NEXT:    lhbrx r3, r3, r4
 ; PWR7_64-NEXT:    blr
+;
+; A2_64-LABEL: LHBRX:
+; A2_64:       # %bb.0:
+; A2_64-NEXT:    extsw r4, r4
+; A2_64-NEXT:    lhbrx r3, r3, r4
+; A2_64-NEXT:    blr
   %tmp1 = getelementptr i8, i8* %ptr, i32 %off
   %tmp1.upgrd.4 = bitcast i8* %tmp1 to i16*
   %tmp = load i16, i16* %tmp1.upgrd.4
   %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp )
   ret i16 %tmp6
 }
 
 ; TODO: combine the bswap feeding a store on subtargets

 ; X64-NEXT:    rldimi r7, r3, 56, 0
 ; X64-NEXT:    stdx r7, r4, r5
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: STDBRX:
 ; PWR7_64:       # %bb.0:
 ; PWR7_64-NEXT:    stdbrx r3, r4, r5
 ; PWR7_64-NEXT:    blr
+;
+; A2_64-LABEL: STDBRX:
+; A2_64:       # %bb.0:
+; A2_64-NEXT:    stdbrx r3, r4, r5
+; A2_64-NEXT:    blr
   %tmp1 = getelementptr i8, i8* %ptr, i64 %off
   %tmp1.upgrd.1 = bitcast i8* %tmp1 to i64*
   %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i )
   store i64 %tmp13, i64* %tmp1.upgrd.1
   ret void
 }
 
 define i64 @LDBRX(i8* %ptr, i64 %off) {

 ; X64-NEXT:    rldimi r5, r3, 32, 0
 ; X64-NEXT:    mr r3, r5
 ; X64-NEXT:    blr
 ;
 ; PWR7_64-LABEL: LDBRX:
 ; PWR7_64:       # %bb.0:
 ; PWR7_64-NEXT:    ldbrx r3, r3, r4
 ; PWR7_64-NEXT:    blr
+;
+; A2_64-LABEL: LDBRX:
+; A2_64:       # %bb.0:
+; A2_64-NEXT:    ldbrx r3, r3, r4
+; A2_64-NEXT:    blr
   %tmp1 = getelementptr i8, i8* %ptr, i64 %off
   %tmp1.upgrd.2 = bitcast i8* %tmp1 to i64*
   %tmp = load i64, i64* %tmp1.upgrd.2
   %tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp )
   ret i64 %tmp14
 }
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)
 declare i64 @llvm.bswap.i64(i64)