[AArch64] Improve multi-precision subtractions

[kazu]

Summary

This patch improves multi-precision subtractions by stripping away:

cset w_, lo
cmp wzr, w_

[efriedma]

Could you explain a bit why this patch works? The "ISD::AND" you're detecting isn't showing up in the final code. Is there some sort of ordering issue here, where we don't re-run this combine after the AND goes away?

[Kmeakin]

Solved by https://reviews.llvm.org/D125504

[kazu]

In D125190#3733832, @Kmeakin wrote:

Solved by https://reviews.llvm.org/D125504

Thanks!

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (IsAdd) {
     if (!isOneConstant(CmpOp.getOperand(1)))
       return SDValue();
   } else {
     if (!isNullConstant(CmpOp.getOperand(0)))
       return SDValue();
   }
 
   SDValue CsetOp = CmpOp->getOperand(IsAdd ? 0 : 1);
+
+  // Strip away AND with 1.
+  if (CsetOp.getOpcode() == ISD::AND && isOneConstant(CsetOp.getOperand(1)))
+    CsetOp = CsetOp.getOperand(0);
+
   auto CC = getCSETCondCode(CsetOp);
   if (CC != (IsAdd ? AArch64CC::HS : AArch64CC::LO))
     return SDValue();
 
   return DAG.getNode(Op->getOpcode(), SDLoc(Op), Op->getVTList(),
                      Op->getOperand(0), Op->getOperand(1),
                      CsetOp.getOperand(3));
 }

llvm/test/CodeGen/AArch64/i256-math.ll

; CHECK-NEXT:    ret
   ret i256 %1
 }
 
 define { i256, i8 } @u256_checked_sub(i256 %x, i256 %y) {
 ; CHECK-LABEL: u256_checked_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    subs x0, x0, x4
 ; CHECK-NEXT:    sbcs x1, x1, x5
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x2, x2, x6
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x3, x3, x7
 ; CHECK-NEXT:    cset w8, lo
 ; CHECK-NEXT:    eor w4, w8, #0x1
 ; CHECK-NEXT:    ret
   %1 = tail call { i256, i1 } @llvm.usub.with.overflow.i256(i256 %x, i256 %y)
   %2 = extractvalue { i256, i1 } %1, 0
   %3 = extractvalue { i256, i1 } %1, 1
   %4 = xor i1 %3, true
   %5 = zext i1 %4 to i8
   %6 = insertvalue { i256, i8 } undef, i256 %2, 0
   %7 = insertvalue { i256, i8 } %6, i8 %5, 1
   ret { i256, i8 } %7
 }
 
 define { i256, i8 } @u256_overflowing_sub(i256 %x, i256 %y) {
 ; CHECK-LABEL: u256_overflowing_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    subs x0, x0, x4
 ; CHECK-NEXT:    sbcs x1, x1, x5
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x2, x2, x6
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x3, x3, x7
 ; CHECK-NEXT:    cset w4, lo
 ; CHECK-NEXT:    ret
   %1 = tail call { i256, i1 } @llvm.usub.with.overflow.i256(i256 %x, i256 %y)
   %2 = extractvalue { i256, i1 } %1, 0
   %3 = extractvalue { i256, i1 } %1, 1
   %4 = zext i1 %3 to i8
   %5 = insertvalue { i256, i8 } undef, i256 %2, 0
; CHECK-NEXT:    ret
   ret i256 %1
 }
 
 define { i256, i8 } @i256_checked_sub(i256 %x, i256 %y) {
 ; CHECK-LABEL: i256_checked_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    subs x0, x0, x4
 ; CHECK-NEXT:    sbcs x1, x1, x5
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x2, x2, x6
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x3, x3, x7
 ; CHECK-NEXT:    cset w8, vs
 ; CHECK-NEXT:    eor w4, w8, #0x1
 ; CHECK-NEXT:    ret
   %1 = tail call { i256, i1 } @llvm.ssub.with.overflow.i256(i256 %x, i256 %y)
   %2 = extractvalue { i256, i1 } %1, 0
   %3 = extractvalue { i256, i1 } %1, 1
   %4 = xor i1 %3, true
   %5 = zext i1 %4 to i8
   %6 = insertvalue { i256, i8 } undef, i256 %2, 0
   %7 = insertvalue { i256, i8 } %6, i8 %5, 1
   ret { i256, i8 } %7
 }
 
 define { i256, i8 } @i256_overflowing_sub(i256 %x, i256 %y) {
 ; CHECK-LABEL: i256_overflowing_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    subs x0, x0, x4
 ; CHECK-NEXT:    sbcs x1, x1, x5
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x2, x2, x6
-; CHECK-NEXT:    cset w8, lo
-; CHECK-NEXT:    cmp wzr, w8
 ; CHECK-NEXT:    sbcs x3, x3, x7
 ; CHECK-NEXT:    cset w4, vs
 ; CHECK-NEXT:    ret
   %1 = tail call { i256, i1 } @llvm.ssub.with.overflow.i256(i256 %x, i256 %y)
   %2 = extractvalue { i256, i1 } %1, 0
   %3 = extractvalue { i256, i1 } %1, 1
   %4 = zext i1 %3 to i8
   %5 = insertvalue { i256, i8 } undef, i256 %2, 0