[PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

[lei]

Summary

XL considers different vector types to be incompatible with each other.
For example assignment between variables of types vector float and vector
long long or even vector signed int and vector unsigned int are diagnosed.
clang, however does not diagnose such cases and does a simple bitcast between
the two types. This could easily result in program errors. This patch is to
fix the implicit casts in altivec.h so that there is no incompatible vector
type errors whit -fno-lax-vector-conversions, this is the prerequisite patch
to switch the default to -fno-lax-vector-conversions later.

[maryammo]

[NFC] Fix the formatting

[nemanjai]

Also, please run clang-format on the changes.

clang/lib/Headers/altivec.h

19204

We should never cast anything to an integral vector type that doesn't include signed/unsigned/bool.

clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c

2156

This is not good. We are changing semantics here - turning a logical shift into an arithmetic shift.

clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c

10

Why is this addition needed? Seems like something is wrong if we need to force enable int128 in order to compile something with altivec.h.

[maryammo]

[PowerPC] Address the review comments

[amyk]

I was wondering where are the test cases in this patch. Did they get missed when updating the revision?

[maryammo]

In D124093#3528639, @amyk wrote:

I was wondering where are the test cases in this patch. Did they get missed when updating the revision?

The test case's modification were not needed as part of addressing Nemanja's comments.

[maryammo]

Updating test cases

[lei]

Add fix for vec_replace_elt and vec_replace_unaligned.

[lei]

rebase to ToT

[lei]

Move error checking for vec_replace_unaligned to during code gen.

[lei]

Simplify vec_replace_[elt|unaligned] code gen.

[nemanjai]

clang/lib/CodeGen/CGBuiltin.cpp

15635

This is strange. You don't need the ternary operator when you are simply setting a bool variable. This is simply:

bool isUnaligned = (BuiltinID == PPC::BI__builtin_altivec_vinsw ||
                    BuiltinID == PPC::BI__builtin_altivec_vinsd);

Same below.

Also, please be careful of the naming convention (i.e. variables start with upper case, functions with lowercase, etc.). I will not add further comments to this end but please apply this change to the entire patch.

15662

This is certainly concise, but trying to parse it puts my brain into an infinite loop. Please write it as:

int ValidMaxValue = 0;
if (IsUnaligned)
  ValidMaxValue = ... ? ... : ...
else
  ValidMaxValue = ...

15666

Since you are building a string from pieces here, might as well mention the value the user specified so it is something like:
byte number 44 is outside of the valid range [0, 12]

15710

Why not simplify the bitcasts below by just creating a pointer to the vector type (call it say, V1I128Ty) here? Same in the next case.

clang/lib/Headers/altivec.h

3211–3220

This is wrong. Please see the documentation for what the result type should be under XL compat. I believe it needs to be vector float regardless of the input.

clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c

8

I don't know why only one of the functions below has checks for this run line, but that needs to be fixed. Please add the NOCOMPAT checks on the other functions.

30

We compute a vector float but return a vector double. Something is wrong. Please see my comment regarding this in altivec.h.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

746

What happened here? Unrelated whitespace change. Please remove it before committing.

[lei]

Address review comments from Nemanja

[lei]

clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c

8

Can we address this on a followup patch? Since it's not related to the work here.

[nemanjai]

LGTM. Thanks.

clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c

8

Absolutely.

[amyk]

This patch also LGTM. Thank you Lei.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "")
 BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "")
 BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "")
 BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","")
 BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi","")
 BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","")
 BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc","")
+BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc","")
+BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc","")
+BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc","")
 
 BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "")
 BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "")
 BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "")
 BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","")
 BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi","")
 BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi","")
 BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc","")
+BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc","")
+BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc","")
+BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc","")
 
 BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "")
 BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "")
 BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "")
 BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "")
 

 BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "")
 BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "")
 
 // P10 Vector Parallel Bits built-ins.
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector String Isolate Built-ins.
-BUILTIN(__builtin_altivec_vstribr, "V16cV16c", "")
-BUILTIN(__builtin_altivec_vstribl, "V16cV16c", "")
+BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "")
+BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "")
 BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "")
-BUILTIN(__builtin_altivec_vstribr_p, "iiV16c", "")
-BUILTIN(__builtin_altivec_vstribl_p, "iiV16c", "")
+BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "")
+BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "")
 BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "")
 BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "")
 
 // P10 Vector Centrifuge built-in.
 BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Gather Every N-th Bit built-in.
 BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "")
 
 // P10 Vector Clear Bytes built-ins.
-BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
-BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
+BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "")
+BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "")
 
 // P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins.
 BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Shift built-ins.
 BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
 BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
 
 // P10 Vector Insert built-ins.
 BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "")
 BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "")
 BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "")
 BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "")
 BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "")
 BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "")
 BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "")
 BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "")
 BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "")
 BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "")
 BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "")
 BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "")
-BUILTIN(__builtin_altivec_vec_replace_elt, "V4UiV4UiUiIi", "t")
-BUILTIN(__builtin_altivec_vec_replace_unaligned, "V4UiV4UiUiIi", "t")
+BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "")
+BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "")
+BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "")
+BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "")
 
 // P10 Vector Extract built-ins.
 BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "")
 BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "")
 BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "")
 BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "")
 BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "")
 BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "")

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
   case PPC::BI__builtin_altivec_vctzw:
   case PPC::BI__builtin_altivec_vctzd: {
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *X = EmitScalarExpr(E->getArg(0));
     Value *Undef = ConstantInt::get(Builder.getInt1Ty(), false);
     Function *F = CGM.getIntrinsic(Intrinsic::cttz, ResultType);
     return Builder.CreateCall(F, {X, Undef});
   }
-  case PPC::BI__builtin_altivec_vec_replace_elt:
-  case PPC::BI__builtin_altivec_vec_replace_unaligned: {
+  case PPC::BI__builtin_altivec_vinsw_elt: {
+
+    llvm::Type *ResultType = ConvertType(E->getType());
     Value *Op0 = EmitScalarExpr(E->getArg(0));
     Value *Op1 = EmitScalarExpr(E->getArg(1));
     Value *Op2 = EmitScalarExpr(E->getArg(2));
-    // The third argument of vec_replace_elt and vec_replace_unaligned must
-    // be a compile time constant and will be emitted either to the vinsw
-    // or vinsd instruction.
+
+    // The third argument must be a compile time constant.
     ConstantInt *ArgCI = dyn_cast<ConstantInt>(Op2);
-    assert(ArgCI &&
-           "Third Arg to vinsw/vinsd intrinsic must be a constant integer!");
-    llvm::Type *ResultType = ConvertType(E->getType());
-    llvm::Function *F = nullptr;
-    Value *Call = nullptr;
+    assert(ArgCI && "Third Arg to vinsw intrinsic must be a constant integer!");
+
     int64_t ConstArg = ArgCI->getSExtValue();
-    unsigned ArgWidth = Op1->getType()->getPrimitiveSizeInBits();
-    bool Is32Bit = false;
-    assert((ArgWidth == 32 || ArgWidth == 64) && "Invalid argument width");
-    // The input to vec_replace_elt is an element index, not a byte index.
-    if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt)
-      ConstArg *= ArgWidth / 8;
-    if (ArgWidth == 32) {
-      Is32Bit = true;
-      // When the second argument is 32 bits, it can either be an integer or
-      // a float. The vinsw intrinsic is used in this case.
-      F = CGM.getIntrinsic(Intrinsic::ppc_altivec_vinsw);
-      // Fix the constant according to endianess.
-      if (getTarget().isLittleEndian())
-        ConstArg = 12 - ConstArg;
-    } else {
-      // When the second argument is 64 bits, it can either be a long long or
-      // a double. The vinsd intrinsic is used in this case.
-      F = CGM.getIntrinsic(Intrinsic::ppc_altivec_vinsd);
-      // Fix the constant for little endian.
-      if (getTarget().isLittleEndian())
-        ConstArg = 8 - ConstArg;
-    }
+    if (ConstArg < 0 or ConstArg > 3)
+      CGM.Error(E->getExprLoc(), "element number out of range [0..3]");
+
+    llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_altivec_vinsw);
+    // The input to vec_replace_elt is an element index, convert to byte index.
+    ConstArg *= 4;
+
+    Op2 = ConstantInt::getSigned(Int32Ty, ConstArg);
+    // Casting input to vector int as per intrinsic definition.
+    Op0 = Builder.CreateBitCast(Op0, llvm::FixedVectorType::get(Int32Ty, 4));
+    return Builder.CreateBitCast(Builder.CreateCall(F, {Op0, Op1, Op2}),
+                                 ResultType);
+  }
+  case PPC::BI__builtin_altivec_vinsd_elt: {
+
+    llvm::Type *ResultType = ConvertType(E->getType());
+    Value *Op0 = EmitScalarExpr(E->getArg(0));
+    Value *Op1 = EmitScalarExpr(E->getArg(1));
+    Value *Op2 = EmitScalarExpr(E->getArg(2));
+
+    // The third argument must be a compile time constant.
+    ConstantInt *ArgCI = dyn_cast<ConstantInt>(Op2);
+    assert(ArgCI && "Third Arg to vinsd intrinsic must be a constant integer!");
+
+    int64_t ConstArg = ArgCI->getSExtValue();
+    if (ConstArg < 0 or ConstArg > 1)
+      CGM.Error(E->getExprLoc(), "element number out of range [0..1]");
+
+    llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_altivec_vinsd);
+    // The input to vec_replace_elt is an element index, convert to byte index.
+    ConstArg *= 8;
+
     Op2 = ConstantInt::getSigned(Int32Ty, ConstArg);
-    // Depending on ArgWidth, the input vector could be a float or a double.
-    // If the input vector is a float type, bitcast the inputs to integers. Or,
-    // if the input vector is a double, bitcast the inputs to 64-bit integers.
-    if (!Op1->getType()->isIntegerTy(ArgWidth)) {
-      Op0 = Builder.CreateBitCast(
-          Op0, Is32Bit ? llvm::FixedVectorType::get(Int32Ty, 4)
-                       : llvm::FixedVectorType::get(Int64Ty, 2));
-      Op1 = Builder.CreateBitCast(Op1, Is32Bit ? Int32Ty : Int64Ty);
-    }
-    // Emit the call to vinsw or vinsd.
-    Call = Builder.CreateCall(F, {Op0, Op1, Op2});
-    // Depending on the builtin, bitcast to the approriate result type.
-    if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt &&
-        !Op1->getType()->isIntegerTy())
-      return Builder.CreateBitCast(Call, ResultType);
-    else if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt &&
-             Op1->getType()->isIntegerTy())
-      return Call;
-    else
-      return Builder.CreateBitCast(Call,
-                                   llvm::FixedVectorType::get(Int8Ty, 16));
+    // Casting input to vector long long as per intrinsic definition.
+    Op0 = Builder.CreateBitCast(Op0, llvm::FixedVectorType::get(Int64Ty, 2));
+    return Builder.CreateBitCast(Builder.CreateCall(F, {Op0, Op1, Op2}),
+                                 ResultType);
   }
   case PPC::BI__builtin_altivec_vpopcntb:
   case PPC::BI__builtin_altivec_vpopcnth:
   case PPC::BI__builtin_altivec_vpopcntw:
   case PPC::BI__builtin_altivec_vpopcntd: {
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *X = EmitScalarExpr(E->getArg(0));
     llvm::Function *F = CGM.getIntrinsic(Intrinsic::ctpop, ResultType);
     return Builder.CreateCall(F, X);
   }
   case PPC::BI__builtin_altivec_vadduqm:
   case PPC::BI__builtin_altivec_vsubuqm: {
     Value *Op0 = EmitScalarExpr(E->getArg(0));
     Value *Op1 = EmitScalarExpr(E->getArg(1));
     llvm::Type *Int128Ty = llvm::IntegerType::get(getLLVMContext(), 128);
     Op0 = Builder.CreateBitCast(Op0, llvm::FixedVectorType::get(Int128Ty, 1));
     Op1 = Builder.CreateBitCast(Op1, llvm::FixedVectorType::get(Int128Ty, 1));
     if (BuiltinID == PPC::BI__builtin_altivec_vadduqm)
       return Builder.CreateAdd(Op0, Op1, "vadduqm");
     else
       return Builder.CreateSub(Op0, Op1, "vsubuqm");
   }
+  case PPC::BI__builtin_altivec_vaddcuq_c:
+  case PPC::BI__builtin_altivec_vsubcuq_c: {
+    SmallVector<Value *, 2> Ops;
+    Value *Op0 = EmitScalarExpr(E->getArg(0));
+    Value *Op1 = EmitScalarExpr(E->getArg(1));
+    llvm::Type *Int128Ty = llvm::IntegerType::get(getLLVMContext(), 128);
+    Ops.push_back(
+        Builder.CreateBitCast(Op0, llvm::FixedVectorType::get(Int128Ty, 1)));
+    Ops.push_back(
+        Builder.CreateBitCast(Op1, llvm::FixedVectorType::get(Int128Ty, 1)));
+    if (BuiltinID == PPC::BI__builtin_altivec_vaddcuq_c)
+      ID = Intrinsic::ppc_altivec_vaddcuq;
+    else
+      ID = Intrinsic::ppc_altivec_vsubcuq;
+    llvm::Function *F = CGM.getIntrinsic(ID);
+    return Builder.CreateCall(F, Ops, "");
+  }
+  case PPC::BI__builtin_altivec_vaddeuqm_c:
+  case PPC::BI__builtin_altivec_vaddecuq_c:
+  case PPC::BI__builtin_altivec_vsubeuqm_c:
+  case PPC::BI__builtin_altivec_vsubecuq_c: {
+    SmallVector<Value *, 3> Ops;
+    Value *Op0 = EmitScalarExpr(E->getArg(0));
+    Value *Op1 = EmitScalarExpr(E->getArg(1));
+    Value *Op2 = EmitScalarExpr(E->getArg(2));
+    llvm::Type *Int128Ty = llvm::IntegerType::get(getLLVMContext(), 128);
+    Ops.push_back(
+        Builder.CreateBitCast(Op0, llvm::FixedVectorType::get(Int128Ty, 1)));
+    Ops.push_back(
+        Builder.CreateBitCast(Op1, llvm::FixedVectorType::get(Int128Ty, 1)));
+    Ops.push_back(
+        Builder.CreateBitCast(Op2, llvm::FixedVectorType::get(Int128Ty, 1)));
+    switch (BuiltinID) {
+    default:
+      llvm_unreachable("Unsupported intrinsic!");
+    case PPC::BI__builtin_altivec_vaddeuqm_c:
+      ID = Intrinsic::ppc_altivec_vaddeuqm;
+      break;
+    case PPC::BI__builtin_altivec_vaddecuq_c:
+      ID = Intrinsic::ppc_altivec_vaddecuq;
+      break;
+    case PPC::BI__builtin_altivec_vsubeuqm_c:
+      ID = Intrinsic::ppc_altivec_vsubeuqm;
+      break;
+    case PPC::BI__builtin_altivec_vsubecuq_c:
+      ID = Intrinsic::ppc_altivec_vsubecuq;
+      break;
+    }
+    llvm::Function *F = CGM.getIntrinsic(ID);
+    return Builder.CreateCall(F, Ops, "");
+  }
   // Rotate and insert under mask operation.
   // __rldimi(rs, is, shift, mask)
   // (rotl64(rs, shift) & mask) | (is & ~mask)
   // __rlwimi(rs, is, shift, mask)
   // (rotl(rs, shift) & mask) | (is & ~mask)
   case PPC::BI__builtin_ppc_rldimi:
   case PPC::BI__builtin_ppc_rlwimi: {
     Value *Op0 = EmitScalarExpr(E->getArg(0));

clang/lib/Headers/altivec.h

 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_add(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __a + __b;
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_add_u128(vector unsigned char __a, vector unsigned char __b) {
-  return __builtin_altivec_vadduqm(__a, __b);
+  return (vector unsigned char)__builtin_altivec_vadduqm(__a, __b);
 }
 #elif defined(__VSX__)
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_add(vector signed long long __a, vector signed long long __b) {
 #ifdef __LITTLE_ENDIAN__
   // Little endian systems on CPU's prior to Power8 don't really exist
   // so scalarizing is fine.
   return __a + __b;
 #else
   vector unsigned int __res =
       (vector unsigned int)__a + (vector unsigned int)__b;
   vector unsigned int __carry = __builtin_altivec_vaddcuw(
       (vector unsigned int)__a, (vector unsigned int)__b);
-  __carry = __builtin_shufflevector((vector unsigned char)__carry,
-                                    (vector unsigned char)__carry, 0, 0, 0, 7,
-                                    0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0);
+  __carry = (vector unsigned int)__builtin_shufflevector(
+      (vector unsigned char)__carry, (vector unsigned char)__carry, 0, 0, 0, 7,
   return (vector signed long long)(__res + __carry);
 #endif
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_add(vector unsigned long long __a, vector unsigned long long __b) {
   return (vector unsigned long long)vec_add((vector signed long long)__a,
                                             (vector signed long long)__b);

 
 /* vec_adde */
 
 #ifdef __POWER8_VECTOR__
 #ifdef __SIZEOF_INT128__
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_adde(vector signed __int128 __a, vector signed __int128 __b,
          vector signed __int128 __c) {
-  return __builtin_altivec_vaddeuqm(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vaddeuqm(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_adde(vector unsigned __int128 __a, vector unsigned __int128 __b,
          vector unsigned __int128 __c) {
   return __builtin_altivec_vaddeuqm(__a, __b, __c);
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_adde_u128(vector unsigned char __a, vector unsigned char __b,
               vector unsigned char __c) {
-  return (vector unsigned char)__builtin_altivec_vaddeuqm(__a, __b, __c);
+  return (vector unsigned char)__builtin_altivec_vaddeuqm_c(
+      (vector unsigned char)__a, (vector unsigned char)__b,
+      (vector unsigned char)__c);
 }
 #endif
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_adde(vector signed int __a, vector signed int __b,
          vector signed int __c) {
   vector signed int __mask = {1, 1, 1, 1};
   vector signed int __carry = __c & __mask;

 
 /* vec_addec */
 
 #ifdef __POWER8_VECTOR__
 #ifdef __SIZEOF_INT128__
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_addec(vector signed __int128 __a, vector signed __int128 __b,
           vector signed __int128 __c) {
-  return __builtin_altivec_vaddecuq(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vaddecuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_addec(vector unsigned __int128 __a, vector unsigned __int128 __b,
           vector unsigned __int128 __c) {
   return __builtin_altivec_vaddecuq(__a, __b, __c);
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_addec_u128(vector unsigned char __a, vector unsigned char __b,
                vector unsigned char __c) {
-  return (vector unsigned char)__builtin_altivec_vaddecuq(__a, __b, __c);
+  return (vector unsigned char)__builtin_altivec_vaddecuq_c(
+      (vector unsigned char)__a, (vector unsigned char)__b,
+      (vector unsigned char)__c);
 }
 
 #ifdef __powerpc64__
 static __inline__ vector signed int __ATTRS_o_ai
 vec_addec(vector signed int __a, vector signed int __b,
           vector signed int __c) {
 
   signed int __result[4];

 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_addc(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __builtin_altivec_vaddcuq(__a, __b);
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_addc_u128(vector unsigned char __a, vector unsigned char __b) {
-  return (vector unsigned char)__builtin_altivec_vaddcuq(__a, __b);
+  return (vector unsigned char)__builtin_altivec_vaddcuq_c(
+      (vector unsigned char)__a, (vector unsigned char)__b);
 }
 #endif // defined(__POWER8_VECTOR__) && defined(__powerpc64__)
 
 /* vec_vaddcuw */
 
 static __inline__ vector unsigned int __attribute__((__always_inline__))
 vec_vaddcuw(vector unsigned int __a, vector unsigned int __b) {
   return __builtin_altivec_vaddcuw(__a, __b);
vec_vadduqm(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __a + __b;
 }
 
 /* vec_vaddeuqm */
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_vaddeuqm(vector signed __int128 __a, vector signed __int128 __b,
              vector signed __int128 __c) {
-  return __builtin_altivec_vaddeuqm(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vaddeuqm(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vaddeuqm(vector unsigned __int128 __a, vector unsigned __int128 __b,
              vector unsigned __int128 __c) {
   return __builtin_altivec_vaddeuqm(__a, __b, __c);
 }
 
 /* vec_vaddcuq */
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_vaddcuq(vector signed __int128 __a, vector signed __int128 __b) {
-  return __builtin_altivec_vaddcuq(__a, __b);
+  return (vector signed __int128)__builtin_altivec_vaddcuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vaddcuq(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __builtin_altivec_vaddcuq(__a, __b);
 }
 
 /* vec_vaddecuq */
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_vaddecuq(vector signed __int128 __a, vector signed __int128 __b,
              vector signed __int128 __c) {
-  return __builtin_altivec_vaddecuq(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vaddecuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vaddecuq(vector unsigned __int128 __a, vector unsigned __int128 __b,
              vector unsigned __int128 __c) {
   return __builtin_altivec_vaddecuq(__a, __b, __c);
 }
 #endif // defined(__POWER8_VECTOR__) && defined(__powerpc64__)
vec_cmpeq(vector double __a, vector double __b) {
   return (vector bool long long)__builtin_vsx_xvcmpeqdp(__a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpeq(vector signed __int128 __a, vector signed __int128 __b) {
   return (vector bool __int128)__builtin_altivec_vcmpequq(
-      (vector bool __int128)__a, (vector bool __int128)__b);
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b);
 }
 
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpeq(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return (vector bool __int128)__builtin_altivec_vcmpequq(
-      (vector bool __int128)__a, (vector bool __int128)__b);
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b);
 }
 
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpeq(vector bool __int128 __a, vector bool  __int128 __b) {
-  return (vector bool __int128)__builtin_altivec_vcmpequq(__a, __b);
+  return (vector bool __int128)__builtin_altivec_vcmpequq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b);
 }
 #endif
 
 #ifdef __POWER9_VECTOR__
 /* vec_cmpne */
 
 static __inline__ vector bool char __ATTRS_o_ai
 vec_cmpne(vector bool char __a, vector bool char __b) {

 vec_cmpne(vector float __a, vector float __b) {
   return (vector bool int)__builtin_altivec_vcmpnew((vector int)__a,
                                                     (vector int)__b);
 }
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpne(vector unsigned __int128 __a, vector unsigned __int128 __b) {
-  return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
-      (vector bool __int128)__a, (vector bool __int128)__b));
+  return (vector bool __int128)~(__builtin_altivec_vcmpequq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b));
 }
 
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpne(vector signed __int128 __a, vector signed __int128 __b) {
-  return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
-      (vector bool __int128)__a, (vector bool __int128)__b));
+  return (vector bool __int128)~(__builtin_altivec_vcmpequq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b));
 }
 
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpne(vector bool __int128 __a, vector bool __int128 __b) {
-  return (vector bool __int128) ~(__builtin_altivec_vcmpequq(__a, __b));
+  return (vector bool __int128)~(__builtin_altivec_vcmpequq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b));
 }
 #endif
 
 /* vec_cmpnez */
 
 static __inline__ vector bool char __ATTRS_o_ai
 vec_cmpnez(vector signed char __a, vector signed char __b) {
   return (vector bool char)__builtin_altivec_vcmpnezb((vector char)__a,

 vec_cmpnez(vector unsigned int __a, vector unsigned int __b) {
   return (vector bool int)__builtin_altivec_vcmpnezw((vector int)__a,
                                                      (vector int)__b);
 }
 
 static __inline__ signed int __ATTRS_o_ai
 vec_cntlz_lsbb(vector signed char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vctzlsbb(__a);
+  return __builtin_altivec_vctzlsbb((vector unsigned char)__a);
 #else
-  return __builtin_altivec_vclzlsbb(__a);
+  return __builtin_altivec_vclzlsbb((vector unsigned char)__a);
 #endif
 }
 
 static __inline__ signed int __ATTRS_o_ai
 vec_cntlz_lsbb(vector unsigned char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vctzlsbb(__a);
+  return __builtin_altivec_vctzlsbb((vector unsigned char)__a);
 #else
   return __builtin_altivec_vclzlsbb(__a);
 #endif
 }
 
 static __inline__ signed int __ATTRS_o_ai
 vec_cnttz_lsbb(vector signed char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vclzlsbb(__a);
+  return __builtin_altivec_vclzlsbb((vector unsigned char)__a);
 #else
-  return __builtin_altivec_vctzlsbb(__a);
+  return __builtin_altivec_vctzlsbb((vector unsigned char)__a);
 #endif
 }
 
 static __inline__ signed int __ATTRS_o_ai
 vec_cnttz_lsbb(vector unsigned char __a) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclzlsbb(__a);
 #else
   return __builtin_altivec_vctzlsbb(__a);
 #endif
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_parity_lsbb(vector unsigned int __a) {
   return __builtin_altivec_vprtybw(__a);
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_parity_lsbb(vector signed int __a) {
-  return __builtin_altivec_vprtybw(__a);
+  return __builtin_altivec_vprtybw((vector unsigned int)__a);
 }
 
 #ifdef __SIZEOF_INT128__
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_parity_lsbb(vector unsigned __int128 __a) {
   return __builtin_altivec_vprtybq(__a);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_parity_lsbb(vector signed __int128 __a) {
-  return __builtin_altivec_vprtybq(__a);
+  return __builtin_altivec_vprtybq((vector unsigned __int128)__a);
 }
 #endif
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_parity_lsbb(vector unsigned long long __a) {
   return __builtin_altivec_vprtybd(__a);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_parity_lsbb(vector signed long long __a) {
-  return __builtin_altivec_vprtybd(__a);
+  return __builtin_altivec_vprtybd((vector unsigned long long)__a);
 }
 
 #else
 /* vec_cmpne */
 
 static __inline__ vector bool char __ATTRS_o_ai
 vec_cmpne(vector bool char __a, vector bool char __b) {
   return ~(vec_cmpeq(__a, __b));

 vec_cmpgt(vector double __a, vector double __b) {
   return (vector bool long long)__builtin_vsx_xvcmpgtdp(__a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpgt(vector signed __int128 __a, vector signed __int128 __b) {
-  return (vector bool __int128)__builtin_altivec_vcmpgtsq(
-      (vector bool __int128)__a, (vector bool __int128)__b);
+  return (vector bool __int128)__builtin_altivec_vcmpgtsq(__a, __b);
 }
 
 static __inline__ vector bool __int128 __ATTRS_o_ai
 vec_cmpgt(vector unsigned __int128 __a, vector unsigned __int128 __b) {
-  return (vector bool __int128)__builtin_altivec_vcmpgtuq(
-      (vector bool __int128)__a, (vector bool __int128)__b);
+  return (vector bool __int128)__builtin_altivec_vcmpgtuq(__a, __b);
 }
 #endif
 
 /* vec_cmpge */
 
 static __inline__ vector bool char __ATTRS_o_ai
 vec_cmpge(vector signed char __a, vector signed char __b) {
   return ~(vec_cmpgt(__b, __a));

 }
 #endif
 
 #ifdef __POWER8_VECTOR__
 /* vec_popcnt */
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_popcnt(vector signed char __a) {
-  return __builtin_altivec_vpopcntb(__a);
+  return (vector unsigned char)__builtin_altivec_vpopcntb(
+      (vector unsigned char)__a);
 }
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_popcnt(vector unsigned char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_popcnt(vector signed short __a) {
-  return __builtin_altivec_vpopcnth(__a);
+  return (vector unsigned short)__builtin_altivec_vpopcnth(
+      (vector unsigned short)__a);
 }
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_popcnt(vector unsigned short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_popcnt(vector signed int __a) {
-  return __builtin_altivec_vpopcntw(__a);
+  return __builtin_altivec_vpopcntw((vector unsigned int)__a);
 }
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_popcnt(vector unsigned int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_popcnt(vector signed long long __a) {
-  return __builtin_altivec_vpopcntd(__a);
+  return __builtin_altivec_vpopcntd((vector unsigned long long)__a);
 }
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_popcnt(vector unsigned long long __a) {
   return __builtin_altivec_vpopcntd(__a);
 }
 
 #define vec_vclz vec_cntlz
 /* vec_cntlz */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_cntlz(vector signed char __a) {
-  return __builtin_altivec_vclzb(__a);
+  return (vector signed char)__builtin_altivec_vclzb((vector unsigned char)__a);
 }
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_cntlz(vector unsigned char __a) {
   return __builtin_altivec_vclzb(__a);
 }
 static __inline__ vector signed short __ATTRS_o_ai
 vec_cntlz(vector signed short __a) {
-  return __builtin_altivec_vclzh(__a);
+  return (vector signed short)__builtin_altivec_vclzh(
+      (vector unsigned short)__a);
 }
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_cntlz(vector unsigned short __a) {
   return __builtin_altivec_vclzh(__a);
 }
 static __inline__ vector signed int __ATTRS_o_ai
 vec_cntlz(vector signed int __a) {
-  return __builtin_altivec_vclzw(__a);
+  return (vector signed int)__builtin_altivec_vclzw((vector unsigned int)__a);
 }
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_cntlz(vector unsigned int __a) {
   return __builtin_altivec_vclzw(__a);
 }
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_cntlz(vector signed long long __a) {
-  return __builtin_altivec_vclzd(__a);
+  return (vector signed long long)__builtin_altivec_vclzd(
+      (vector unsigned long long)__a);
 }
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_cntlz(vector unsigned long long __a) {
   return __builtin_altivec_vclzd(__a);
 }
 #endif
 
 #ifdef __POWER9_VECTOR__
 
 /* vec_cnttz */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_cnttz(vector signed char __a) {
-  return __builtin_altivec_vctzb(__a);
+  return (vector signed char)__builtin_altivec_vctzb((vector unsigned char)__a);
 }
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_cnttz(vector unsigned char __a) {
   return __builtin_altivec_vctzb(__a);
 }
 static __inline__ vector signed short __ATTRS_o_ai
 vec_cnttz(vector signed short __a) {
-  return __builtin_altivec_vctzh(__a);
+  return (vector signed short)__builtin_altivec_vctzh(
+      (vector unsigned short)__a);
 }
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_cnttz(vector unsigned short __a) {
   return __builtin_altivec_vctzh(__a);
 }
 static __inline__ vector signed int __ATTRS_o_ai
 vec_cnttz(vector signed int __a) {
-  return __builtin_altivec_vctzw(__a);
+  return (vector signed int)__builtin_altivec_vctzw((vector unsigned int)__a);
 }
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_cnttz(vector unsigned int __a) {
   return __builtin_altivec_vctzw(__a);
 }
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_cnttz(vector signed long long __a) {
-  return __builtin_altivec_vctzd(__a);
+  return (vector signed long long)__builtin_altivec_vctzd(
+      (vector unsigned long long)__a);
 }
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_cnttz(vector unsigned long long __a) {
   return __builtin_altivec_vctzd(__a);
 }
 
 /* vec_first_match_index */
 

 }
 
 static __inline__ void __ATTRS_o_ai vec_xst_len_r(vector unsigned char __a,
                                                   unsigned char *__b,
                                                   size_t __c) {
   vector unsigned char __mask =
       (vector unsigned char)__builtin_altivec_lvsl(16 - __c, (int *)NULL);
   vector unsigned char __res =
-      __builtin_altivec_vperm_4si((vector int)__a, (vector int)__a, __mask);
+      (vector unsigned char)__builtin_altivec_vperm_4si(
+          (vector int)__a, (vector int)__a, __mask);
   return __builtin_vsx_stxvll((vector int)__res, __b, (__c << 56));
 }
 #endif
 #endif
 
 #if defined(__POWER9_VECTOR__) && defined(__powerpc64__)
 #define __vec_ldrmb(PTR, CNT) vec_xl_len_r((const unsigned char *)(PTR), (CNT))
 #define __vec_strmb(PTR, CNT, VAL)                                             \

 #ifdef __XL_COMPAT_ALTIVEC__
 #define vec_ctf(__a, __b)                                                      \
   _Generic((__a), vector int                                                   \
            : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),  \
              vector unsigned int                                               \
            : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \
                                                    (__b)),                     \
              vector unsigned long long                                         \
-           : (__builtin_vsx_xvcvuxdsp((vector unsigned long long)(__a)) *      \
-              (vector float)(vector unsigned)((0x7f - (__b)) << 23)),          \
+           : (vector double)(__builtin_vsx_xvcvuxdsp(                          \
+                                 (vector unsigned long long)(__a)) *           \
+                             (vector float)(vector unsigned)((0x7f - (__b))    \
+                                                             << 23)),          \
              vector signed long long                                           \
-           : (__builtin_vsx_xvcvsxdsp((vector signed long long)(__a)) *        \
-              (vector float)(vector unsigned)((0x7f - (__b)) << 23)))
+           : (vector double)(__builtin_vsx_xvcvsxdsp(                          \
+                                 (vector signed long long)(__a)) *             \
+                             (vector float)(vector unsigned)((0x7f - (__b))    \
+                                                             << 23)))
 #else // __XL_COMPAT_ALTIVEC__
 #define vec_ctf(__a, __b)                                                      \
-  _Generic((__a), vector int                                                   \
-           : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),  \
-             vector unsigned int                                               \
-           : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \
-                                                   (__b)),                     \
-             vector unsigned long long                                         \
-           : (__builtin_convertvector((vector unsigned long long)(__a),        \
-                                      vector double) *                         \
-              (vector double)(vector unsigned long long)((0x3ffULL - (__b))    \
-                                                         << 52)),              \
-             vector signed long long                                           \
-           : (__builtin_convertvector((vector signed long long)(__a),          \
-                                      vector double) *                         \
-              (vector double)(vector unsigned long long)((0x3ffULL - (__b))    \
+  _Generic(                                                                    \
+      (__a), vector int                                                        \
+      : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),       \
+        vector unsigned int                                                    \
+      : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a),      \
+                                              (__b)),                          \
+        vector unsigned long long                                              \
+      : (vector double)(__builtin_convertvector(                               \
+                            (vector unsigned long long)(__a), vector double) * \
+                        (vector double)(vector unsigned long long)((0x3ffULL - \
+                                                                    (__b))     \
+                                                                   << 52)),    \
+        vector signed long long                                                \
+      : (vector double)(__builtin_convertvector(                               \
+                            (vector signed long long)(__a), vector double) *   \
+                        (vector double)(vector unsigned long long)((0x3ffULL - \
+                                                                    (__b))     \
                                                                    << 52)))
 #endif // __XL_COMPAT_ALTIVEC__
 #else
 #define vec_ctf(__a, __b)                                                      \
   _Generic((__a), vector int                                                   \
            : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),  \
              vector unsigned int                                               \
            : (vector float)__builtin_altivec_vcfux((vector unsigned int)(__a), \
                                                    (__b)))

 #define vec_vcfsx(__a, __b) __builtin_altivec_vcfsx((vector int)(__a), (__b))
 
 /* vec_cts */
 
 #ifdef __VSX__
 #ifdef __XL_COMPAT_ALTIVEC__
 #define vec_cts(__a, __b)                                                      \
   _Generic((__a), vector float                                                 \
-           : __builtin_altivec_vctsxs((vector float)(__a), (__b)),             \
+           : (vector signed int)__builtin_altivec_vctsxs((vector float)(__a),  \
+                                                         (__b)),               \
              vector double                                                     \
            : __extension__({                                                   \
              vector double __ret =                                             \
                  (vector double)(__a) *                                        \
                  (vector double)(vector unsigned long long)((0x3ffULL + (__b)) \
                                                             << 52);            \
-             __builtin_vsx_xvcvdpsxws(__ret);                                  \
+             (vector signed long long)__builtin_vsx_xvcvdpsxws(__ret);         \
            }))
 #else // __XL_COMPAT_ALTIVEC__
 #define vec_cts(__a, __b)                                                      \
   _Generic((__a), vector float                                                 \
-           : __builtin_altivec_vctsxs((vector float)(__a), (__b)),             \
+           : (vector signed int)__builtin_altivec_vctsxs((vector float)(__a),  \
+                                                         (__b)),               \
              vector double                                                     \
            : __extension__({                                                   \
              vector double __ret =                                             \
                  (vector double)(__a) *                                        \
                  (vector double)(vector unsigned long long)((0x3ffULL + (__b)) \
                                                             << 52);            \
-             __builtin_convertvector(__ret, vector signed long long);          \
+             (vector signed long long)__builtin_convertvector(                 \
+                 __ret, vector signed long long);                              \
            }))
 #endif // __XL_COMPAT_ALTIVEC__
 #else
 #define vec_cts __builtin_altivec_vctsxs
 #endif
 
 /* vec_vctsxs */
 
 #define vec_vctsxs __builtin_altivec_vctsxs
 
 /* vec_ctu */
 
 #ifdef __VSX__
 #ifdef __XL_COMPAT_ALTIVEC__
 #define vec_ctu(__a, __b)                                                      \
   _Generic((__a), vector float                                                 \
-           : __builtin_altivec_vctuxs((vector float)(__a), (__b)),             \
+           : (vector unsigned int)__builtin_altivec_vctuxs(                    \
+                 (vector float)(__a), (__b)),                                  \
              vector double                                                     \
            : __extension__({                                                   \
              vector double __ret =                                             \
                  (vector double)(__a) *                                        \
                  (vector double)(vector unsigned long long)((0x3ffULL + __b)   \
                                                             << 52);            \
-             __builtin_vsx_xvcvdpuxws(__ret);                                  \
+             (vector unsigned long long)__builtin_vsx_xvcvdpuxws(__ret);       \
            }))
 #else // __XL_COMPAT_ALTIVEC__
 #define vec_ctu(__a, __b)                                                      \
   _Generic((__a), vector float                                                 \
-           : __builtin_altivec_vctuxs((vector float)(__a), (__b)),             \
+           : (vector unsigned int)__builtin_altivec_vctuxs(                    \
+                 (vector float)(__a), (__b)),                                  \
              vector double                                                     \
            : __extension__({                                                   \
              vector double __ret =                                             \
                  (vector double)(__a) *                                        \
                  (vector double)(vector unsigned long long)((0x3ffULL + __b)   \
                                                             << 52);            \
-             __builtin_convertvector(__ret, vector unsigned long long);        \
+             (vector unsigned long long)__builtin_convertvector(               \
+                 __ret, vector unsigned long long);                            \
            }))
 #endif // __XL_COMPAT_ALTIVEC__
 #else
 #define vec_ctu __builtin_altivec_vctuxs
 #endif
 
 #ifdef __LITTLE_ENDIAN__
 /* vec_ctsl */

 #ifdef __POWER8_VECTOR__
 static __inline__ vector signed char __ATTRS_o_ai
 vec_nand(vector signed char __a, vector signed char __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_nand(vector signed char __a, vector bool char __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector signed char)__b);
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_nand(vector bool char __a, vector signed char __b) {
-  return ~(__a & __b);
+  return (vector signed char)~(__a & (vector bool char)__b);
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_nand(vector unsigned char __a, vector unsigned char __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_nand(vector unsigned char __a, vector bool char __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector unsigned char)__b);
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_nand(vector bool char __a, vector unsigned char __b) {
-  return ~(__a & __b);
+  return (vector unsigned char)~(__a & (vector bool char)__b);
 }
 
 static __inline__ vector bool char __ATTRS_o_ai vec_nand(vector bool char __a,
                                                          vector bool char __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_nand(vector signed short __a, vector signed short __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_nand(vector signed short __a, vector bool short __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector signed short)__b);
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_nand(vector bool short __a, vector signed short __b) {
-  return ~(__a & __b);
+  return (vector signed short)~(__a & (vector bool short)__b);
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_nand(vector unsigned short __a, vector unsigned short __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_nand(vector unsigned short __a, vector bool short __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector unsigned short)__b);
 }
 
 static __inline__ vector bool short __ATTRS_o_ai
 vec_nand(vector bool short __a, vector bool short __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_nand(vector signed int __a, vector signed int __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector signed int __ATTRS_o_ai vec_nand(vector signed int __a,
                                                           vector bool int __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector signed int)__b);
 }
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_nand(vector bool int __a, vector signed int __b) {
-  return ~(__a & __b);
+  return (vector signed int)~(__a & (vector bool int)__b);
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_nand(vector unsigned int __a, vector unsigned int __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_nand(vector unsigned int __a, vector bool int __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector unsigned int)__b);
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_nand(vector bool int __a, vector unsigned int __b) {
-  return ~(__a & __b);
+  return (vector unsigned int)~(__a & (vector bool int)__b);
 }
 
 static __inline__ vector bool int __ATTRS_o_ai vec_nand(vector bool int __a,
                                                         vector bool int __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector float __ATTRS_o_ai
 vec_nand(vector float __a, vector float __b) {
   return (vector float)(~((vector unsigned int)__a &
                           (vector unsigned int)__b));
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_nand(vector signed long long __a, vector signed long long __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_nand(vector signed long long __a, vector bool long long __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector signed long long)__b);
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_nand(vector bool long long __a, vector signed long long __b) {
-  return ~(__a & __b);
+  return (vector signed long long)~(__a & (vector bool long long)__b);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_nand(vector unsigned long long __a, vector unsigned long long __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_nand(vector unsigned long long __a, vector bool long long __b) {
-  return ~(__a & __b);
+  return ~(__a & (vector unsigned long long)__b);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_nand(vector bool long long __a, vector unsigned long long __b) {
-  return ~(__a & __b);
+  return (vector unsigned long long)~(__a & (vector bool long long)__b);
 }
 
 static __inline__ vector bool long long __ATTRS_o_ai
 vec_nand(vector bool long long __a, vector bool long long __b) {
   return ~(__a & __b);
 }
 
 static __inline__ vector double __ATTRS_o_ai

 #ifdef __POWER8_VECTOR__
 static __inline__ vector signed char __ATTRS_o_ai
 vec_orc(vector signed char __a, vector signed char __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_orc(vector signed char __a, vector bool char __b) {
-  return __a | ~__b;
+  return __a | (vector signed char)~__b;
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_orc(vector bool char __a, vector signed char __b) {
-  return __a | ~__b;
+  return (vector signed char)(__a | (vector bool char)~__b);
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_orc(vector unsigned char __a, vector unsigned char __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_orc(vector unsigned char __a, vector bool char __b) {
-  return __a | ~__b;
+  return __a | (vector unsigned char)~__b;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_orc(vector bool char __a, vector unsigned char __b) {
-  return __a | ~__b;
+  return (vector unsigned char)(__a | (vector bool char)~__b);
 }
 
 static __inline__ vector bool char __ATTRS_o_ai vec_orc(vector bool char __a,
                                                         vector bool char __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_orc(vector signed short __a, vector signed short __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_orc(vector signed short __a, vector bool short __b) {
-  return __a | ~__b;
+  return __a | (vector signed short)~__b;
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_orc(vector bool short __a, vector signed short __b) {
-  return __a | ~__b;
+  return (vector signed short)(__a | (vector bool short)~__b);
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_orc(vector unsigned short __a, vector unsigned short __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_orc(vector unsigned short __a, vector bool short __b) {
-  return __a | ~__b;
+  return __a | (vector unsigned short)~__b;
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_orc(vector bool short __a, vector unsigned short __b) {
-  return __a | ~__b;
+  return (vector unsigned short)(__a | (vector bool short)~__b);
 }
 
 static __inline__ vector bool short __ATTRS_o_ai
 vec_orc(vector bool short __a, vector bool short __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_orc(vector signed int __a, vector signed int __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector signed int __ATTRS_o_ai vec_orc(vector signed int __a,
                                                          vector bool int __b) {
-  return __a | ~__b;
+  return __a | (vector signed int)~__b;
 }
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_orc(vector bool int __a, vector signed int __b) {
-  return __a | ~__b;
+  return (vector signed int)(__a | (vector bool int)~__b);
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_orc(vector unsigned int __a, vector unsigned int __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_orc(vector unsigned int __a, vector bool int __b) {
-  return __a | ~__b;
+  return __a | (vector unsigned int)~__b;
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_orc(vector bool int __a, vector unsigned int __b) {
-  return __a | ~__b;
+  return (vector unsigned int)(__a | (vector bool int)~__b);
 }
 
 static __inline__ vector bool int __ATTRS_o_ai vec_orc(vector bool int __a,
                                                        vector bool int __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector float __ATTRS_o_ai
 vec_orc(vector bool int __a, vector float __b) {
- return (vector float)(__a | ~(vector unsigned int)__b);
+  return (vector float)(__a | ~(vector bool int)__b);
 }
 
 static __inline__ vector float __ATTRS_o_ai
 vec_orc(vector float __a, vector bool int __b) {
-  return (vector float)((vector unsigned int)__a | ~__b);
+  return (vector float)((vector bool int)__a | ~__b);
 }
 
 static __inline__ vector float __ATTRS_o_ai vec_orc(vector float __a,
                                                     vector float __b) {
   return (vector float)((vector unsigned int)__a | ~(vector unsigned int)__b);
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector signed long long __a, vector signed long long __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector signed long long __a, vector bool long long __b) {
-  return __a | ~__b;
+  return __a | (vector signed long long)~__b;
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector bool long long __a, vector signed long long __b) {
-  return __a | ~__b;
+  return (vector signed long long)(__a | (vector bool long long)~__b);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_orc(vector unsigned long long __a, vector unsigned long long __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_orc(vector unsigned long long __a, vector bool long long __b) {
-  return __a | ~__b;
+  return __a | (vector unsigned long long)~__b;
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_orc(vector bool long long __a, vector unsigned long long __b) {
-  return __a | ~__b;
+  return (vector unsigned long long)(__a | (vector bool long long)~__b);
 }
 
 static __inline__ vector bool long long __ATTRS_o_ai
 vec_orc(vector bool long long __a, vector bool long long __b) {
   return __a | ~__b;
 }
 
 static __inline__ vector double __ATTRS_o_ai
 vec_orc(vector double __a, vector bool long long __b) {
-  return (vector double)((vector unsigned long long)__a | ~__b);
+  return (vector double)((vector bool long long)__a | ~__b);
 }
 
 static __inline__ vector double __ATTRS_o_ai
 vec_orc(vector bool long long __a, vector double __b) {
-  return (vector double)(__a | ~(vector unsigned long long)__b);
+  return (vector double)(__a | ~(vector bool long long)__b);
 }
 
 static __inline__ vector double __ATTRS_o_ai vec_orc(vector double __a,
                                                      vector double __b) {
-  return (vector double)((vector bool long long)__a |
+  return (vector double)((vector unsigned long long)__a |
                          ~(vector unsigned long long)__b);
 }
 #endif
 
 /* vec_vor */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_vor(vector signed char __a, vector signed char __b) {

 #ifdef __POWER8_VECTOR__
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_rl(vector signed long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vrld(__a, __b);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_rl(vector unsigned long long __a, vector unsigned long long __b) {
-  return __builtin_altivec_vrld(__a, __b);
+  return (vector unsigned long long)__builtin_altivec_vrld(
+      (vector long long)__a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_rl(vector signed __int128 __a, vector unsigned __int128 __b) {
-  return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector signed __int128)) - __a));
+  return (vector signed __int128)(((vector unsigned __int128)__b
+                                   << (vector unsigned __int128)__a) |
+                                  ((vector unsigned __int128)__b >>
+                                   ((__CHAR_BIT__ *
+                                     sizeof(vector unsigned __int128)) -
+                                    (vector unsigned __int128)__a)));
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_rl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector unsigned __int128)) - __a));
 }
 #endif
 

 vec_rlmi(vector unsigned __int128 __a, vector unsigned __int128 __b,
          vector unsigned __int128 __c) {
   return __builtin_altivec_vrlqmi(__a, __c, __b);
 }
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_rlmi(vector signed __int128 __a, vector signed __int128 __b,
          vector signed __int128 __c) {
-  return __builtin_altivec_vrlqmi(__a, __c, __b);
+  return (vector signed __int128)__builtin_altivec_vrlqmi(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__c,
+      (vector unsigned __int128)__b);
 }
 #endif
 
 /* vec_rlnm */
 #ifdef __POWER9_VECTOR__
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_rlnm(vector unsigned int __a, vector unsigned int __b,
          vector unsigned int __c) {
vec_rlnm(vector signed __int128 __a, vector signed __int128 __b,
   vector unsigned char MaskAndShift =
 #ifdef __LITTLE_ENDIAN__
       __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, -1, -1, -1, 16, 0,
                               1, -1, -1, -1, -1, -1);
 #else
       __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, 31, 30, 15, -1,
                               -1, -1, -1, -1, -1, -1, -1);
 #endif
-  return __builtin_altivec_vrlqnm(__a, (vector unsigned __int128) MaskAndShift);
+  return (vector signed __int128)__builtin_altivec_vrlqnm(
+      (vector unsigned __int128)__a, (vector unsigned __int128)MaskAndShift);
 }
 #endif
 
 /* vec_vrlb */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_vrlb(vector signed char __a, vector unsigned char __b) {
   return (vector signed char)__builtin_altivec_vrlb((vector char)__a, __b);

 #ifdef __SIZEOF_INT128__
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_subc(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __builtin_altivec_vsubcuq(__a, __b);
 }
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_subc(vector signed __int128 __a, vector signed __int128 __b) {
-  return __builtin_altivec_vsubcuq(__a, __b);
+  return (vector signed __int128)__builtin_altivec_vsubcuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b);
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_subc_u128(vector unsigned char __a, vector unsigned char __b) {
-  return (vector unsigned char)__builtin_altivec_vsubcuq(__a, __b);
+  return (vector unsigned char)__builtin_altivec_vsubcuq_c(
+      (vector unsigned char)__a, (vector unsigned char)__b);
 }
 #endif // __POWER8_VECTOR__
 
 /* vec_vsubcuw */
 
 static __inline__ vector unsigned int __attribute__((__always_inline__))
 vec_vsubcuw(vector unsigned int __a, vector unsigned int __b) {
   return __builtin_altivec_vsubcuw(__a, __b);

 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vsubuqm(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __a - __b;
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_sub_u128(vector unsigned char __a, vector unsigned char __b) {
-  return __builtin_altivec_vsubuqm(__a, __b);
+  return (vector unsigned char)__builtin_altivec_vsubuqm(__a, __b);
 }
 
 /* vec_vsubeuqm */
 
 #ifdef __SIZEOF_INT128__
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_vsubeuqm(vector signed __int128 __a, vector signed __int128 __b,
              vector signed __int128 __c) {
-  return __builtin_altivec_vsubeuqm(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vsubeuqm(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vsubeuqm(vector unsigned __int128 __a, vector unsigned __int128 __b,
              vector unsigned __int128 __c) {
   return __builtin_altivec_vsubeuqm(__a, __b, __c);
 }
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_sube(vector signed __int128 __a, vector signed __int128 __b,
              vector signed __int128 __c) {
-  return __builtin_altivec_vsubeuqm(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vsubeuqm(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_sube(vector unsigned __int128 __a, vector unsigned __int128 __b,
              vector unsigned __int128 __c) {
   return __builtin_altivec_vsubeuqm(__a, __b, __c);
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_sube_u128(vector unsigned char __a, vector unsigned char __b,
               vector unsigned char __c) {
-  return (vector unsigned char)__builtin_altivec_vsubeuqm(__a, __b, __c);
+  return (vector unsigned char)__builtin_altivec_vsubeuqm_c(
+      (vector unsigned char)__a, (vector unsigned char)__b,
+      (vector unsigned char)__c);
 }
 
 /* vec_vsubcuq */
 
 #ifdef __SIZEOF_INT128__
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_vsubcuq(vector signed __int128 __a, vector signed __int128 __b) {
-  return __builtin_altivec_vsubcuq(__a, __b);
+  return (vector signed __int128)__builtin_altivec_vsubcuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vsubcuq(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __builtin_altivec_vsubcuq(__a, __b);
 }
 
 /* vec_vsubecuq */
 
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_vsubecuq(vector signed __int128 __a, vector signed __int128 __b,
              vector signed __int128 __c) {
-  return __builtin_altivec_vsubecuq(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vsubecuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_vsubecuq(vector unsigned __int128 __a, vector unsigned __int128 __b,
              vector unsigned __int128 __c) {
   return __builtin_altivec_vsubecuq(__a, __b, __c);
 }
 #endif
vec_subec(vector unsigned int __a, vector unsigned int __b,
   return vec_addec(__a, ~__b, __c);
 }
 #endif
 
 #ifdef __SIZEOF_INT128__
 static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_subec(vector signed __int128 __a, vector signed __int128 __b,
              vector signed __int128 __c) {
-  return __builtin_altivec_vsubecuq(__a, __b, __c);
+  return (vector signed __int128)__builtin_altivec_vsubecuq(
+      (vector unsigned __int128)__a, (vector unsigned __int128)__b,
+      (vector unsigned __int128)__c);
 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_subec(vector unsigned __int128 __a, vector unsigned __int128 __b,
              vector unsigned __int128 __c) {
   return __builtin_altivec_vsubecuq(__a, __b, __c);
 }
 #endif
 
 static __inline__ vector unsigned char __attribute__((__always_inline__))
 vec_subec_u128(vector unsigned char __a, vector unsigned char __b,
                vector unsigned char __c) {
-  return (vector unsigned char)__builtin_altivec_vsubecuq(__a, __b, __c);
+  return (vector unsigned char)__builtin_altivec_vsubecuq_c(
+      (vector unsigned char)__a, (vector unsigned char)__b,
+      (vector unsigned char)__c);
 }
 #endif // __POWER8_VECTOR__
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_sube(vector signed int __a, vector signed int __b,
          vector signed int __c) {
   vector signed int __mask = {1, 1, 1, 1};
   vector signed int __carry = __c & __mask;
static __inline__ int __ATTRS_o_ai vec_all_eq(vector double __a,
                                               vector double __b) {
   return __builtin_vsx_xvcmpeqdp_p(__CR6_LT, __a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed __int128 __a,
                                               vector signed __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_LT, (vector unsigned __int128)__a,
+                                      (vector signed __int128)__b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_all_eq(vector unsigned __int128 __a,
                                               vector unsigned __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_LT, __a,
+                                      (vector signed __int128)__b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_all_eq(vector bool __int128 __a,
                                               vector bool __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_LT, (vector unsigned __int128)__a,
+                                      (vector signed __int128)__b);
 }
 #endif
 
 /* vec_all_ge */
 
 static __inline__ int __ATTRS_o_ai vec_all_ge(vector signed char __a,
                                               vector signed char __b) {
   return __builtin_altivec_vcmpgtsb_p(__CR6_EQ, __b, __a);
static __inline__ int __ATTRS_o_ai vec_all_ne(vector double __a,
                                               vector double __b) {
   return __builtin_vsx_xvcmpeqdp_p(__CR6_EQ, __a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ int __ATTRS_o_ai vec_all_ne(vector signed __int128 __a,
                                               vector signed __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_EQ, (vector unsigned __int128)__a,
+                                      __b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_all_ne(vector unsigned __int128 __a,
                                               vector unsigned __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a,
+                                      (vector signed __int128)__b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_all_ne(vector bool __int128 __a,
                                               vector bool __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_EQ, (vector unsigned __int128)__a,
+                                      (vector signed __int128)__b);
 }
 #endif
 
 /* vec_all_nge */
 
 static __inline__ int __ATTRS_o_ai vec_all_nge(vector float __a,
                                                vector float __b) {
 #ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_any_eq(vector double __a,
                                               vector double __b) {
   return __builtin_vsx_xvcmpeqdp_p(__CR6_EQ_REV, __a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ int __ATTRS_o_ai vec_any_eq(vector signed __int128 __a,
                                               vector signed __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV,
+                                      (vector unsigned __int128)__a, __b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_any_eq(vector unsigned __int128 __a,
                                               vector unsigned __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a,
+                                      (vector signed __int128)__b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_any_eq(vector bool __int128 __a,
                                               vector bool __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b);
+  return __builtin_altivec_vcmpequq_p(
+      __CR6_EQ_REV, (vector unsigned __int128)__a, (vector signed __int128)__b);
 }
 #endif
 
 /* vec_any_ge */
 
 static __inline__ int __ATTRS_o_ai vec_any_ge(vector signed char __a,
                                               vector signed char __b) {
   return __builtin_altivec_vcmpgtsb_p(__CR6_LT_REV, __b, __a);
static __inline__ int __ATTRS_o_ai vec_any_ne(vector double __a,
                                               vector double __b) {
   return __builtin_vsx_xvcmpeqdp_p(__CR6_LT_REV, __a, __b);
 }
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
 static __inline__ int __ATTRS_o_ai vec_any_ne(vector signed __int128 __a,
                                               vector signed __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_LT_REV,
+                                      (vector unsigned __int128)__a, __b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_any_ne(vector unsigned __int128 __a,
                                               vector unsigned __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b);
+  return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a,
+                                      (vector signed __int128)__b);
 }
 
 static __inline__ int __ATTRS_o_ai vec_any_ne(vector bool __int128 __a,
                                               vector bool __int128 __b) {
-  return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b);
+  return __builtin_altivec_vcmpequq_p(
+      __CR6_LT_REV, (vector unsigned __int128)__a, (vector signed __int128)__b);
 }
 #endif
 
 /* vec_any_nge */
 
 static __inline__ int __ATTRS_o_ai vec_any_nge(vector float __a,
                                                vector float __b) {
 #ifdef __VSX__
_Generic((X), vector unsigned int                                            \
            : __builtin_crypto_vshasigmaw, vector unsigned long long            \
            : __builtin_crypto_vshasigmad)((X), (Y), (Z))
 #endif
 
 #ifdef __POWER8_VECTOR__
 static __inline__ vector bool char __ATTRS_o_ai
 vec_permxor(vector bool char __a, vector bool char __b,
             vector bool char __c) {
-  return __builtin_altivec_crypto_vpermxor(__a, __b, __c);
+  return (vector bool char)__builtin_altivec_crypto_vpermxor(
+      (vector unsigned char)__a, (vector unsigned char)__b,
+      (vector unsigned char)__c);
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_permxor(vector signed char __a, vector signed char __b,
             vector signed char __c) {
-  return __builtin_altivec_crypto_vpermxor(__a, __b, __c);
+  return (vector signed char)__builtin_altivec_crypto_vpermxor(
+      (vector unsigned char)__a, (vector unsigned char)__b,
+      (vector unsigned char)__c);
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_permxor(vector unsigned char __a, vector unsigned char __b,
             vector unsigned char __c) {
   return __builtin_altivec_crypto_vpermxor(__a, __b, __c);
 }
 

 static __inline__ vector unsigned long long __ATTRS_o_ai
 __builtin_crypto_vpmsumb(vector unsigned long long __a,
                          vector unsigned long long __b) {
   return __builtin_altivec_crypto_vpmsumd(__a, __b);
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_vgbbd(vector signed char __a) {
-  return __builtin_altivec_vgbbd((vector unsigned char)__a);
+  return (vector signed char)__builtin_altivec_vgbbd((vector unsigned char)__a);
 }
 
 #define vec_pmsum_be __builtin_crypto_vpmsumb
 #define vec_gb __builtin_altivec_vgbbd
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_vgbbd(vector unsigned char __a) {
   return __builtin_altivec_vgbbd(__a);
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_gbb(vector signed long long __a) {
-  return __builtin_altivec_vgbbd((vector unsigned char)__a);
+  return (vector signed long long)__builtin_altivec_vgbbd(
+      (vector unsigned char)__a);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_gbb(vector unsigned long long __a) {
-  return __builtin_altivec_vgbbd((vector unsigned char)__a);
+  return (vector unsigned long long)__builtin_altivec_vgbbd(
+      (vector unsigned char)__a);
 }
 
 static __inline__ vector long long __ATTRS_o_ai
 vec_vbpermq(vector signed char __a, vector signed char __b) {
-  return __builtin_altivec_vbpermq((vector unsigned char)__a,
+  return (vector long long)__builtin_altivec_vbpermq((vector unsigned char)__a,
                                                      (vector unsigned char)__b);
 }
 
 static __inline__ vector long long __ATTRS_o_ai
 vec_vbpermq(vector unsigned char __a, vector unsigned char __b) {
-  return __builtin_altivec_vbpermq(__a, __b);
+  return (vector long long)__builtin_altivec_vbpermq(__a, __b);
 }
 
 #if defined(__powerpc64__) && defined(__SIZEOF_INT128__)
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_bperm(vector unsigned __int128 __a, vector unsigned char __b) {
   return __builtin_altivec_vbpermq((vector unsigned char)__a,
                                    (vector unsigned char)__b);
 }
 #endif
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_bperm(vector unsigned char __a, vector unsigned char __b) {
-  return __builtin_altivec_vbpermq(__a, __b);
+  return (vector unsigned char)__builtin_altivec_vbpermq(__a, __b);
 }
 #endif // __POWER8_VECTOR__
 #ifdef __POWER9_VECTOR__
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_bperm(vector unsigned long long __a, vector unsigned char __b) {
   return __builtin_altivec_vbpermd(__a, __b);
 }
 #endif

 #endif
 #else
   #define vec_xl_be vec_xl
 #endif
 
 #if defined(__POWER10_VECTOR__) && defined(__VSX__) &&                         \
     defined(__SIZEOF_INT128__)
 
-/* vect_xl_sext */
+/* vec_xl_sext */
 
-static __inline__ vector unsigned __int128 __ATTRS_o_ai
+static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_xl_sext(ptrdiff_t __offset, const signed char *__pointer) {
-  return (vector unsigned __int128)*(__pointer + __offset);
+  return (vector signed __int128)*(__pointer + __offset);
 }
 
-static __inline__ vector unsigned __int128 __ATTRS_o_ai
+static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_xl_sext(ptrdiff_t __offset, const signed short *__pointer) {
-  return (vector unsigned __int128)*(__pointer + __offset);
+  return (vector signed __int128)*(__pointer + __offset);
 }
 
-static __inline__ vector unsigned __int128 __ATTRS_o_ai
+static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_xl_sext(ptrdiff_t __offset, const signed int *__pointer) {
-  return (vector unsigned __int128)*(__pointer + __offset);
+  return (vector signed __int128)*(__pointer + __offset);
 }
 
-static __inline__ vector unsigned __int128 __ATTRS_o_ai
+static __inline__ vector signed __int128 __ATTRS_o_ai
 vec_xl_sext(ptrdiff_t __offset, const signed long long *__pointer) {
-  return (vector unsigned __int128)*(__pointer + __offset);
+  return (vector signed __int128)*(__pointer + __offset);
 }
 
 /* vec_xl_zext */
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_xl_zext(ptrdiff_t __offset, const unsigned char *__pointer) {
   return (vector unsigned __int128)*(__pointer + __offset);
 }
vec_expandm(vector unsigned __int128 __a) {
   return __builtin_altivec_vexpandqm(__a);
 }
 #endif
 
 /* vec_cntm */
 
 #define vec_cntm(__a, __mp)                                                    \
   _Generic((__a), vector unsigned char                                         \
-           : __builtin_altivec_vcntmbb((__a), (unsigned char)(__mp)),          \
+           : __builtin_altivec_vcntmbb((vector unsigned char)(__a),            \
+                                       (unsigned char)(__mp)),                 \
              vector unsigned short                                             \
-           : __builtin_altivec_vcntmbh((__a), (unsigned char)(__mp)),          \
+           : __builtin_altivec_vcntmbh((vector unsigned short)(__a),           \
+                                       (unsigned char)(__mp)),                 \
              vector unsigned int                                               \
-           : __builtin_altivec_vcntmbw((__a), (unsigned char)(__mp)),          \
+           : __builtin_altivec_vcntmbw((vector unsigned int)(__a),             \
+                                       (unsigned char)(__mp)),                 \
              vector unsigned long long                                         \
-           : __builtin_altivec_vcntmbd((__a), (unsigned char)(__mp)))
+           : __builtin_altivec_vcntmbd((vector unsigned long long)(__a),       \
+                                       (unsigned char)(__mp)))
 
 /* vec_gen[b|h|w|d|q]m */
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_genbm(unsigned long long __bm) {
   return __builtin_altivec_mtvsrbm(__bm);
 }
 

 
 #define vec_gnb(__a, __b) __builtin_altivec_vgnb(__a, __b)
 
 /* vec_ternarylogic */
 #ifdef __VSX__
 #ifdef __SIZEOF_INT128__
 #define vec_ternarylogic(__a, __b, __c, __imm)                                 \
   _Generic((__a), vector unsigned char                                         \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned char)__builtin_vsx_xxeval(                       \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned short                                             \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned short)__builtin_vsx_xxeval(                      \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned int                                               \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned int)__builtin_vsx_xxeval(                        \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned long long                                         \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned long long)__builtin_vsx_xxeval(                  \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned __int128                                          \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)))
+           : (vector unsigned __int128)__builtin_vsx_xxeval(                   \
+               (vector unsigned long long)(__a),                               \
+               (vector unsigned long long)(__b),                               \
 #else
 #define vec_ternarylogic(__a, __b, __c, __imm)                                 \
   _Generic((__a), vector unsigned char                                         \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned char)__builtin_vsx_xxeval(                       \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned short                                             \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned short)__builtin_vsx_xxeval(                      \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned int                                               \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)),  \
+           : (vector unsigned int)__builtin_vsx_xxeval(                        \
+                 (vector unsigned long long)(__a),                             \
+                 (vector unsigned long long)(__b),                             \
+                 (vector unsigned long long)(__c), (__imm)),                   \
              vector unsigned long long                                         \
-           : __builtin_vsx_xxeval((vector unsigned long long)(__a),            \
-                                  (vector unsigned long long)(__b),            \
-                                  (vector unsigned long long)(__c), (__imm)))
+           : (vector unsigned long long)__builtin_vsx_xxeval(                  \
+               (vector unsigned long long)(__a),                               \
+               (vector unsigned long long)(__b),                               \
 #endif /* __SIZEOF_INT128__ */
 #endif /* __VSX__ */
 
 /* vec_genpcvm */
 
 #ifdef __VSX__
 #define vec_genpcvm(__a, __imm)                                                \
-  _Generic((__a), vector unsigned char                                         \
-           : __builtin_vsx_xxgenpcvbm((__a), (int)(__imm)),                    \
-             vector unsigned short                                             \
-           : __builtin_vsx_xxgenpcvhm((__a), (int)(__imm)),                    \
-             vector unsigned int                                               \
-           : __builtin_vsx_xxgenpcvwm((__a), (int)(__imm)),                    \
-             vector unsigned long long                                         \
-           : __builtin_vsx_xxgenpcvdm((__a), (int)(__imm)))
+  _Generic(                                                                    \
+      (__a), vector unsigned char                                              \
+      : __builtin_vsx_xxgenpcvbm((vector unsigned char)(__a), (int)(__imm)),   \
+        vector unsigned short                                                  \
+      : __builtin_vsx_xxgenpcvhm((vector unsigned short)(__a), (int)(__imm)),  \
+        vector unsigned int                                                    \
+      : __builtin_vsx_xxgenpcvwm((vector unsigned int)(__a), (int)(__imm)),    \
+        vector unsigned long long                                              \
+      : __builtin_vsx_xxgenpcvdm((vector unsigned long long)(__a),             \
+                                 (int)(__imm)))
 #endif /* __VSX__ */
 
 /* vec_clr_first */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_clr_first(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vclrrb(__a, __n);
+  return (vector signed char)__builtin_altivec_vclrrb((vector unsigned char)__a,
+                                                      __n);
 #else
-  return __builtin_altivec_vclrlb( __a, __n);
+  return (vector signed char)__builtin_altivec_vclrlb((vector unsigned char)__a,
+                                                      __n);
 #endif
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_clr_first(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vclrrb((vector signed char)__a, __n);
+  return (vector unsigned char)__builtin_altivec_vclrrb(
+      (vector unsigned char)__a, __n);
 #else
-  return __builtin_altivec_vclrlb((vector signed char)__a, __n);
+  return (vector unsigned char)__builtin_altivec_vclrlb(
+      (vector unsigned char)__a, __n);
 #endif
 }
 
 /* vec_clr_last */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_clr_last(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vclrlb(__a, __n);
+  return (vector signed char)__builtin_altivec_vclrlb((vector unsigned char)__a,
+                                                      __n);
 #else
-  return __builtin_altivec_vclrrb( __a, __n);
+  return (vector signed char)__builtin_altivec_vclrrb((vector unsigned char)__a,
+                                                      __n);
 #endif
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_clr_last(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vclrlb((vector signed char)__a, __n);
+  return (vector unsigned char)__builtin_altivec_vclrlb(
+      (vector unsigned char)__a, __n);
 #else
-  return __builtin_altivec_vclrrb((vector signed char)__a, __n);
+  return (vector unsigned char)__builtin_altivec_vclrrb(
+      (vector unsigned char)__a, __n);
 #endif
 }
 
 /* vec_cntlzm */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_cntlzm(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vclzdm(__a, __b);

 }
 
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_mod(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return  __a % __b;
 }
 #endif
 
-/* vec_sldbi */
-
-#define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))
-
-/* vec_srdbi */
+/* vec_sldb */
+#define vec_sldb(__a, __b, __c)                                                \
+  _Generic(                                                                    \
+      (__a), vector unsigned char                                              \
+      : (vector unsigned char)__builtin_altivec_vsldbi(                        \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed char                                                     \
+      : (vector signed char)__builtin_altivec_vsldbi(                          \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector unsigned short                                                  \
+      : (vector unsigned short)__builtin_altivec_vsldbi(                       \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed short                                                    \
+      : (vector signed short)__builtin_altivec_vsldbi(                         \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector unsigned int                                                    \
+      : (vector unsigned int)__builtin_altivec_vsldbi(                         \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed int                                                      \
+      : (vector signed int)__builtin_altivec_vsldbi((vector unsigned char)__a, \
+                                                    (vector unsigned char)__b, \
+                                                    (__c & 0x7)),              \
+        vector unsigned long long                                              \
+      : (vector unsigned long long)__builtin_altivec_vsldbi(                   \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed long long                                                \
+      : (vector signed long long)__builtin_altivec_vsldbi(                     \
+          (vector unsigned char)__a, (vector unsigned char)__b, (__c & 0x7)))
 
-#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
+/* vec_srdb */
+#define vec_srdb(__a, __b, __c)                                                \
+  _Generic(                                                                    \
+      (__a), vector unsigned char                                              \
+      : (vector unsigned char)__builtin_altivec_vsrdbi(                        \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed char                                                     \
+      : (vector signed char)__builtin_altivec_vsrdbi(                          \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector unsigned short                                                  \
+      : (vector unsigned short)__builtin_altivec_vsrdbi(                       \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed short                                                    \
+      : (vector signed short)__builtin_altivec_vsrdbi(                         \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector unsigned int                                                    \
+      : (vector unsigned int)__builtin_altivec_vsrdbi(                         \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed int                                                      \
+      : (vector signed int)__builtin_altivec_vsrdbi((vector unsigned char)__a, \
+                                                    (vector unsigned char)__b, \
+                                                    (__c & 0x7)),              \
+        vector unsigned long long                                              \
+      : (vector unsigned long long)__builtin_altivec_vsrdbi(                   \
+            (vector unsigned char)__a, (vector unsigned char)__b,              \
+            (__c & 0x7)),                                                      \
+        vector signed long long                                                \
+      : (vector signed long long)__builtin_altivec_vsrdbi(                     \
+          (vector unsigned char)__a, (vector unsigned char)__b, (__c & 0x7)))
 
 /* vec_insertl */
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_insertl(unsigned char __a, vector unsigned char __b, unsigned int __c) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vinsbrx(__b, __c, __a);
 #else
#else
   vector unsigned long long __ret = __builtin_altivec_vextddvrx(__a, __b, __c);
   return vec_sld(__ret, __ret, 8);
 #endif
 }
 
 #ifdef __VSX__
 
 /* vec_permx */
-
 #define vec_permx(__a, __b, __c, __d)                                          \
-  __builtin_vsx_xxpermx((__a), (__b), (__c), (__d))
+  _Generic(                                                                    \
+      (__a), vector unsigned char                                              \
+      : (vector unsigned char)__builtin_vsx_xxpermx(                           \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector signed char                                                     \
+      : (vector signed char)__builtin_vsx_xxpermx(                             \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector unsigned short                                                  \
+      : (vector unsigned short)__builtin_vsx_xxpermx(                          \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector signed short                                                    \
+      : (vector signed short)__builtin_vsx_xxpermx(                            \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector unsigned int                                                    \
+      : (vector unsigned int)__builtin_vsx_xxpermx(                            \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector signed int                                                      \
+      : (vector signed int)__builtin_vsx_xxpermx(                              \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector unsigned long long                                              \
+      : (vector unsigned long long)__builtin_vsx_xxpermx(                      \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector signed long long                                                \
+      : (vector signed long long)__builtin_vsx_xxpermx(                        \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector float                                                           \
+      : (vector float)__builtin_vsx_xxpermx(                                   \
+            (vector unsigned char)__a, (vector unsigned char)__b, __c, __d),   \
+        vector double                                                          \
+      : (vector double)__builtin_vsx_xxpermx(                                  \
+          (vector unsigned char)__a, (vector unsigned char)__b, __c, __d))
 
 /* vec_blendv */
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_blendv(vector signed char __a, vector signed char __b,
            vector unsigned char __c) {
-  return __builtin_vsx_xxblendvb(__a, __b, __c);
+  return (vector signed char)__builtin_vsx_xxblendvb(
+      (vector unsigned char)__a, (vector unsigned char)__b, __c);
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_blendv(vector unsigned char __a, vector unsigned char __b,
            vector unsigned char __c) {
   return __builtin_vsx_xxblendvb(__a, __b, __c);
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_blendv(vector signed short __a, vector signed short __b,
            vector unsigned short __c) {
-  return __builtin_vsx_xxblendvh(__a, __b, __c);
+  return (vector signed short)__builtin_vsx_xxblendvh(
+      (vector unsigned short)__a, (vector unsigned short)__b, __c);
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_blendv(vector unsigned short __a, vector unsigned short __b,
            vector unsigned short __c) {
   return __builtin_vsx_xxblendvh(__a, __b, __c);
 }
 
 static __inline__ vector signed int __ATTRS_o_ai
 vec_blendv(vector signed int __a, vector signed int __b,
            vector unsigned int __c) {
-  return __builtin_vsx_xxblendvw(__a, __b, __c);
+  return (vector signed int)__builtin_vsx_xxblendvw(
+      (vector unsigned int)__a, (vector unsigned int)__b, __c);
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_blendv(vector unsigned int __a, vector unsigned int __b,
            vector unsigned int __c) {
   return __builtin_vsx_xxblendvw(__a, __b, __c);
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_blendv(vector signed long long __a, vector signed long long __b,
            vector unsigned long long __c) {
-  return __builtin_vsx_xxblendvd(__a, __b, __c);
+  return (vector signed long long)__builtin_vsx_xxblendvd(
+      (vector unsigned long long)__a, (vector unsigned long long)__b, __c);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_blendv(vector unsigned long long __a, vector unsigned long long __b,
            vector unsigned long long __c) {
-  return __builtin_vsx_xxblendvd(__a, __b, __c);
+  return (vector unsigned long long)__builtin_vsx_xxblendvd(__a, __b, __c);
 }
 
 static __inline__ vector float __ATTRS_o_ai
 vec_blendv(vector float __a, vector float __b, vector unsigned int __c) {
-  return __builtin_vsx_xxblendvw(__a, __b, __c);
+  return (vector float)__builtin_vsx_xxblendvw((vector unsigned int)__a,
+                                               (vector unsigned int)__b, __c);
 }
 
 static __inline__ vector double __ATTRS_o_ai
 vec_blendv(vector double __a, vector double __b,
            vector unsigned long long __c) {
-  return __builtin_vsx_xxblendvd(__a, __b, __c);
+  return (vector double)__builtin_vsx_xxblendvd(
+      (vector unsigned long long)__a, (vector unsigned long long)__b, __c);
 }
 
-/* vec_replace_elt */
-
-#define vec_replace_elt __builtin_altivec_vec_replace_elt
-
-/* vec_replace_unaligned */
+#define vec_replace_unaligned(__a, __b, __c)                                   \
+  _Generic((__a), vector signed int                                            \
+           : (vector signed int)__builtin_altivec_vinsw(                       \
+                 (vector unsigned char)__a, (unsigned int)__b, __c),           \
+             vector unsigned int                                               \
+           : (vector unsigned int)__builtin_altivec_vinsw(                     \
+                 (vector unsigned char)__a, (unsigned int)__b, __c),           \
+             vector unsigned long long                                         \
+           : (vector unsigned long long)__builtin_altivec_vinsd(               \
+                 (vector unsigned char)__a, (unsigned long long)__b, __c),     \
+             vector signed long long                                           \
+           : (vector signed long long)__builtin_altivec_vinsd(                 \
+                 (vector unsigned char)__a, (unsigned long long)__b, __c),     \
+             vector float                                                      \
+           : (vector float)__builtin_altivec_vinsw((vector unsigned char)__a,  \
+                                                   (unsigned int)__b, __c),    \
+             vector double                                                     \
+           : (vector double)__builtin_altivec_vinsd(                           \
+               (vector unsigned char)__a, (unsigned long long)__b, __c))
 
-#define vec_replace_unaligned __builtin_altivec_vec_replace_unaligned
+#define vec_replace_elt(__a, __b, __c)                                         \
+  _Generic((__a), vector signed int                                            \
+           : (vector signed int)__builtin_altivec_vinsw_elt(                   \
+                 (vector unsigned char)__a, (unsigned int)__b, __c),           \
+             vector unsigned int                                               \
+           : (vector unsigned int)__builtin_altivec_vinsw_elt(                 \
+                 (vector unsigned char)__a, (unsigned int)__b, __c),           \
+             vector unsigned long long                                         \
+           : (vector unsigned long long)__builtin_altivec_vinsd_elt(           \
+                 (vector unsigned char)__a, (unsigned long long)__b, __c),     \
+             vector signed long long                                           \
+           : (vector signed long long)__builtin_altivec_vinsd_elt(             \
+                 (vector unsigned char)__a, (unsigned long long)__b, __c),     \
+             vector float                                                      \
+           : (vector float)__builtin_altivec_vinsw_elt(                        \
+                 (vector unsigned char)__a, (unsigned int)__b, __c),           \
+             vector double                                                     \
+           : (vector double)__builtin_altivec_vinsd_elt(                       \
+               (vector unsigned char)__a, (unsigned long long)__b, __c))
 
 /* vec_splati */
 
 #define vec_splati(__a)                                                        \
   _Generic((__a), signed int                                                   \
            : ((vector signed int)__a), unsigned int                            \
            : ((vector unsigned int)__a), float                                 \
            : ((vector float)__a))

 }
 #endif /* __VSX__ */
 
 /* vec_stril */
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_stril(vector unsigned char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribr((vector signed char)__a);
+  return (vector unsigned char)__builtin_altivec_vstribr(
+      (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribl((vector signed char)__a);
+  return (vector unsigned char)__builtin_altivec_vstribl(
+      (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_stril(vector signed char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribr(__a);
+  return (vector signed char)__builtin_altivec_vstribr(
+      (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribl(__a);
+  return (vector signed char)__builtin_altivec_vstribl(
+      (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_stril(vector unsigned short __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstrihr((vector signed short)__a);
+  return (vector unsigned short)__builtin_altivec_vstrihr(
+      (vector signed short)__a);
 #else
-  return __builtin_altivec_vstrihl((vector signed short)__a);
+  return (vector unsigned short)__builtin_altivec_vstrihl(
+      (vector signed short)__a);
 #endif
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_stril(vector signed short __a) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vstrihr(__a);
 #else
   return __builtin_altivec_vstrihl(__a);
 #endif
 }
 
 /* vec_stril_p */
 
 static __inline__ int __ATTRS_o_ai vec_stril_p(vector unsigned char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribr_p(__CR6_EQ, (vector signed char)__a);
+  return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribl_p(__CR6_EQ, (vector signed char)__a);
+  return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ int __ATTRS_o_ai vec_stril_p(vector signed char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribr_p(__CR6_EQ, __a);
+  return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribl_p(__CR6_EQ, __a);
+  return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ int __ATTRS_o_ai vec_stril_p(vector unsigned short __a) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vstrihr_p(__CR6_EQ, (vector signed short)__a);
 #else
   return __builtin_altivec_vstrihl_p(__CR6_EQ, (vector signed short)__a);
 #endif
 }
 
 static __inline__ int __ATTRS_o_ai vec_stril_p(vector signed short __a) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vstrihr_p(__CR6_EQ, __a);
 #else
   return __builtin_altivec_vstrihl_p(__CR6_EQ, __a);
 #endif
 }
 
 /* vec_strir */
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_strir(vector unsigned char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribl((vector signed char)__a);
+  return (vector unsigned char)__builtin_altivec_vstribl(
+      (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribr((vector signed char)__a);
+  return (vector unsigned char)__builtin_altivec_vstribr(
+      (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_strir(vector signed char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribl(__a);
+  return (vector signed char)__builtin_altivec_vstribl(
+      (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribr(__a);
+  return (vector signed char)__builtin_altivec_vstribr(
+      (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_strir(vector unsigned short __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstrihl((vector signed short)__a);
+  return (vector unsigned short)__builtin_altivec_vstrihl(
+      (vector signed short)__a);
 #else
-  return __builtin_altivec_vstrihr((vector signed short)__a);
+  return (vector unsigned short)__builtin_altivec_vstrihr(
+      (vector signed short)__a);
 #endif
 }
 
 static __inline__ vector signed short __ATTRS_o_ai
 vec_strir(vector signed short __a) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vstrihl(__a);
 #else
   return __builtin_altivec_vstrihr(__a);
 #endif
 }
 
 /* vec_strir_p */
 
 static __inline__ int __ATTRS_o_ai vec_strir_p(vector unsigned char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribl_p(__CR6_EQ, (vector signed char)__a);
+  return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribr_p(__CR6_EQ, (vector signed char)__a);
+  return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ int __ATTRS_o_ai vec_strir_p(vector signed char __a) {
 #ifdef __LITTLE_ENDIAN__
-  return __builtin_altivec_vstribl_p(__CR6_EQ, __a);
+  return __builtin_altivec_vstribl_p(__CR6_EQ, (vector unsigned char)__a);
 #else
-  return __builtin_altivec_vstribr_p(__CR6_EQ, __a);
+  return __builtin_altivec_vstribr_p(__CR6_EQ, (vector unsigned char)__a);
 #endif
 }
 
 static __inline__ int __ATTRS_o_ai vec_strir_p(vector unsigned short __a) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vstrihl_p(__CR6_EQ, (vector signed short)__a);
 #else
   return __builtin_altivec_vstrihr_p(__CR6_EQ, (vector signed short)__a);

clang/lib/Sema/SemaChecking.cpp

static bool isValidBPFPreserveFieldInfoArg(Expr *Arg) {
   // If it is an array element access, we delay decision
   // to BPF backend to check whether the access is a
   // field access or not.
   return (Arg->IgnoreParens()->getObjectKind() == OK_BitField ||
           isa<MemberExpr>(Arg->IgnoreParens()) ||
           isa<ArraySubscriptExpr>(Arg->IgnoreParens()));
 }
 
-static bool isEltOfVectorTy(ASTContext &Context, CallExpr *Call, Sema &S,
-                            QualType VectorTy, QualType EltTy) {
-  QualType VectorEltTy = VectorTy->castAs<VectorType>()->getElementType();
-  if (!Context.hasSameType(VectorEltTy, EltTy)) {
-    S.Diag(Call->getBeginLoc(), diag::err_typecheck_call_different_arg_types)
-        << Call->getSourceRange() << VectorEltTy << EltTy;
-    return false;
-  }
-  return true;
-}
-
 static bool isValidBPFPreserveTypeInfoArg(Expr *Arg) {
   QualType ArgType = Arg->getType();
   if (ArgType->getAsPlaceholderType())
     return false;
 
   // for TYPE_EXISTENCE/TYPE_SIZEOF reloc type
   // format:
   //   1. __builtin_preserve_type_info(*(<type> *)0, flag);
case PPC::BI__builtin_pack_vector_int128:
     return SemaFeatureCheck(*this, TheCall, "vsx",
                             diag::err_ppc_builtin_only_on_arch, "7");
   case PPC::BI__builtin_pdepd:
   case PPC::BI__builtin_pextd:
     return SemaFeatureCheck(*this, TheCall, "isa-v31-instructions",
                             diag::err_ppc_builtin_only_on_arch, "10");
   case PPC::BI__builtin_altivec_vgnb:
      return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
-  case PPC::BI__builtin_altivec_vec_replace_elt:
-  case PPC::BI__builtin_altivec_vec_replace_unaligned: {
-    QualType VecTy = TheCall->getArg(0)->getType();
-    QualType EltTy = TheCall->getArg(1)->getType();
-    unsigned Width = Context.getIntWidth(EltTy);
-    return SemaBuiltinConstantArgRange(TheCall, 2, 0, Width == 32 ? 12 : 8) ||
-           !isEltOfVectorTy(Context, TheCall, *this, VecTy, EltTy);
-  }
+  case PPC::BI__builtin_altivec_vinsw:
+  case PPC::BI__builtin_altivec_vinsd:
+    return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15);
   case PPC::BI__builtin_vsx_xxeval:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255);
   case PPC::BI__builtin_altivec_vsldbi:
      return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_altivec_vsrdbi:
      return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   case PPC::BI__builtin_vsx_xxpermx:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);

clang/test/CodeGen/PowerPC/altivec-dss.c

-// RUN: %clang_cc1 -triple powerpc-linux-gnu -S -O0 -o - %s -target-feature +altivec | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-linux-gnu -S -O0 -o - %s -target-feature +altivec | FileCheck %s
 
 // REQUIRES: powerpc-registered-target
 
 #include <altivec.h>
 
 // CHECK-LABEL: test1
 // CHECK: dss 
 void test1() {
   vec_dss(1);
 }

clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
-// RUN:   -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec \
+// RUN: -target-feature +power8-vector -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
 
 #include <altivec.h>
 vector signed long long vsll1, vsll2, vsll3;
+vector unsigned long long vull1, vull2, vull3;
 vector signed char vsc;
+vector unsigned char vuc;
 vector bool long long vbll;
 
 void dummy();
 void test() {
   vec_abs(vsll1);
 // CHECK: call <2 x i64> @llvm.ppc.altivec.vmaxsd
   dummy();
 // CHECK-NEXT: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_vpkudum(vsll1, vsll2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_packs(vsll1, vsll2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vpksdss
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_vpkudus(vsll1, vsll2);
+  vec_vpkudus(vull1, vull2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vpkudus
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_packsu(vsll1, vsll2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vpksdus
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_rl(vsll1, vsll2);
+  vec_rl(vull1, vull2);
 // CHECK: call <2 x i64> @llvm.ppc.altivec.vrld
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_sel(vsll1, vsll2, vbll);
 // CHECK: xor <2 x i64>
 // CHECK: and <2 x i64>
 // CHECK: and <2 x i64>
 // CHECK: or <2 x i64>
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_sl(vsll1, vsll2);
+  vec_sl(vull1, vull2);
 // CHECK: shl <2 x i64>
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_sld(vsll1, vsll2, 2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_sldw(vsll1, vsll2, 2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_sll(vsll1, vsll2);
+  vec_sll(vsll1, vuc);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_slo(vsll1, vsc);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_splat(vsll1, 2);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_sr(vsll1, vsll2);
+  vec_sr(vull1, vull2);
 // CHECK: lshr <2 x i64>
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_sra(vsll1, vsll2);
+  vec_sra(vsll1, vull2);
 // CHECK: ashr <2 x i64>
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
-  vec_srl(vsll1, vsc);
+  vec_srl(vsll1, vuc);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_sro(vsll1, vsc);
 // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro
   dummy();
 // CHECK: call void bitcast (void (...)* @dummy to void ()*)()
   vec_sub(vsll1, vsll2);

clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown \
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -triple powerpc64le-unknown-unknown \
 // RUN: -target-feature +crypto -target-feature +power8-vector \
 // RUN: -emit-llvm %s -o - | FileCheck %s
 
-// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown \
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -triple powerpc64-unknown-unknown \
 // RUN: -target-feature +crypto -target-feature +power8-vector \
 // RUN: -emit-llvm %s -o - | FileCheck %s
 #include <altivec.h>
 #define B_INIT1 { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, \
                   0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10 };
 #define B_INIT2 { 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, \
                   0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x70 };
 #define H_INIT1 { 0x0102, 0x0304, 0x0506, 0x0708, \

 {
   vector unsigned char a = B_INIT1
   vector unsigned char b = B_INIT2
   vector unsigned char c = B_INIT2
   return __builtin_altivec_crypto_vpermxor(a, b, c);
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
-// CHECK-LABEL: define{{.*}} <8 x i16> @test_vpermxorh
-vector unsigned short test_vpermxorh(void)
-{
-  vector unsigned short a = H_INIT1
-  vector unsigned short b = H_INIT2
-  vector unsigned short c = H_INIT2
-  return __builtin_altivec_crypto_vpermxor(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor
-}
-
-// CHECK-LABEL: define{{.*}} <4 x i32> @test_vpermxorw
-vector unsigned int test_vpermxorw(void)
-{
-  vector unsigned int a = W_INIT1
-  vector unsigned int b = W_INIT2
-  vector unsigned int c = W_INIT2
-  return __builtin_altivec_crypto_vpermxor(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor
-}
-
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vpermxord
-vector unsigned long long test_vpermxord(void)
-{
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
-  vector unsigned long long c = D_INIT2
-  return __builtin_altivec_crypto_vpermxor(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor
-}
-
 // CHECK-LABEL: test_vpermxorbc
 vector bool char test_vpermxorbc(vector bool char a,
                                 vector bool char b,
                                 vector bool char c) {
   return vec_permxor(a, b, c);
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
 // CHECK-LABEL: test_vpermxorsc
 vector signed char test_vpermxorsc(vector signed char a,
                                    vector signed char b,
                                    vector signed char c) {
   return vec_permxor(a, b, c);
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
 // CHECK-LABEL: test_vpermxoruc
 vector unsigned char test_vpermxoruc(vector unsigned char a,
                                      vector unsigned char b,
                                      vector unsigned char c) {
   return vec_permxor(a, b, c);
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
-// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorb_be
-vector unsigned char test_vpermxorb_be(vector unsigned char a,
-                                       vector unsigned char b,
-                                       vector unsigned char c) {
-  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
-}
-
-// CHECK-LABEL: define{{.*}} <8 x i16> @test_vpermxorh_be
-vector unsigned short test_vpermxorh_be(vector unsigned short a,
-                                        vector unsigned short b,
-                                        vector unsigned short c) {
-  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
-}
-
-// CHECK-LABEL: define{{.*}} <4 x i32> @test_vpermxorw_be
-vector unsigned int test_vpermxorw_be(vector unsigned int a,
-                                      vector unsigned int b,
-                                      vector unsigned int c) {
-  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
-}
-
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vpermxord_be
-vector unsigned long long test_vpermxord_be(vector unsigned long long a,
-                                            vector unsigned long long b,
-                                            vector unsigned long long c) {
-  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
-}
-
-// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorbc_be
-vector bool char test_vpermxorbc_be(vector bool char a,
-                                    vector bool char b,
-                                    vector bool char c) {
-  return  __builtin_altivec_crypto_vpermxor_be(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
-}
-
-// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorsc_be
-vector signed char test_vpermxorsc_be(vector signed char a,
-                                      vector signed char b,
-                                      vector signed char c) {
-  return  __builtin_altivec_crypto_vpermxor_be(a, b, c);
-// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
-}
-
 // CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxoruc_be
 vector unsigned char test_vpermxoruc_be(vector unsigned char a,
                                         vector unsigned char b,
                                         vector unsigned char c) {
   return  __builtin_altivec_crypto_vpermxor_be(a, b, c);
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
 }
 

 vector unsigned long long test_vcipherlast_e(void)
 {
   vector unsigned long long a = D_INIT1
   vector unsigned long long b = D_INIT2
   return __builtin_crypto_vcipherlast(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
 
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vncipher_e
-vector unsigned long long test_vncipher_e(void)
-{
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
-  return __builtin_crypto_vncipher(a, b);
-// CHECK: @llvm.ppc.altivec.crypto.vncipher
-}
-
-// CHECK-LABEL: define{{.*}} <2 x i64> @test_vncipherlast_e
-vector unsigned long long test_vncipherlast_e(void)
-{
-  vector unsigned long long a = D_INIT1
-  vector unsigned long long b = D_INIT2
-  return __builtin_crypto_vncipherlast(a, b);
-// CHECK: @llvm.ppc.altivec.crypto.vncipherlast
-}
-
 // CHECK-LABEL: define{{.*}} <4 x i32> @test_vshasigmaw_e
 vector unsigned int test_vshasigmaw_e(void)
 {
   vector unsigned int a = W_INIT1
   return __builtin_crypto_vshasigmaw(a, 1, 15);
 // CHECK: @llvm.ppc.altivec.crypto.vshasigmaw
 }
 
 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vshasigmad_e
 vector unsigned long long test_vshasigmad_e(void)
 {
   vector unsigned long long a = D_INIT2
   return __builtin_crypto_vshasigmad(a, 0, 15);
 // CHECK: @llvm.ppc.altivec.crypto.vshasigmad
 }
 
 // CHECK-LABEL: @test_vec_sbox_be
-vector unsigned char test_vec_sbox_be(void)
+vector unsigned long long test_vec_sbox_be(void)
 {
-  vector unsigned char a = B_INIT1
+  vector unsigned long long a = D_INIT1
   return vec_sbox_be(a);
 // CHECK: @llvm.ppc.altivec.crypto.vsbox
 }
 
 // CHECK-LABEL: @test_vec_cipher_be
-vector unsigned char test_vec_cipher_be(void)
+vector unsigned long long test_vec_cipher_be(void)
 {
-  vector unsigned char a = B_INIT1
-  vector unsigned char b = B_INIT2
+  vector unsigned long long a = D_INIT1
+  vector unsigned long long b = D_INIT2
   return vec_cipher_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }
 
 // CHECK-LABEL: @test_vec_cipherlast_be
-vector unsigned char test_vec_cipherlast_be(void)
+vector unsigned long long test_vec_cipherlast_be(void)
 {
-  vector unsigned char a = B_INIT1
-  vector unsigned char b = B_INIT2
+  vector unsigned long long a = D_INIT1
+  vector unsigned long long b = D_INIT2
   return vec_cipherlast_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipherlast
 }
 
 // CHECK-LABEL: @test_vec_ncipher_be
-vector unsigned char test_vec_ncipher_be(void)
+vector unsigned long long test_vec_ncipher_be(void)
 {
-  vector unsigned char a = B_INIT1
-  vector unsigned char b = B_INIT2
+  vector unsigned long long a = D_INIT1
+  vector unsigned long long b = D_INIT2
   return vec_ncipher_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipher
 }
 
 // CHECK-LABEL: @test_vec_ncipherlast_be
-vector unsigned char test_vec_ncipherlast_be(void)
+vector unsigned long long test_vec_ncipherlast_be(void)
 {
-  vector unsigned char a = B_INIT1
-  vector unsigned char b = B_INIT2
+  vector unsigned long long a = D_INIT1
+  vector unsigned long long b = D_INIT2
   return vec_ncipherlast_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vncipherlast
 }
 
 // CHECK-LABEL: @test_vec_shasigma_bew
 vector unsigned int test_vec_shasigma_bew(void)
 {
   vector unsigned int a = W_INIT1
   return vec_shasigma_be(a, 1, 15);
 // CHECK: @llvm.ppc.altivec.crypto.vshasigmaw
 }
 
 // CHECK-LABEL: @test_vec_shasigma_bed
 vector unsigned long long test_vec_shasigma_bed(void)
 {
   vector unsigned long long a = D_INIT2
   return vec_shasigma_be(a, 1, 15);
 // CHECK: @llvm.ppc.altivec.crypto.vshasigmad
 }
 
 // CHECK-LABEL: @test_vec_pmsum_beb
-vector unsigned short test_vec_pmsum_beb(void)
+vector unsigned char test_vec_pmsum_beb(void)
 {
   vector unsigned char a = B_INIT1
   vector unsigned char b = B_INIT2
   return vec_pmsum_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumb
 }
 
 // CHECK-LABEL: @test_vec_pmsum_beh
-vector unsigned int test_vec_pmsum_beh(void)
+vector unsigned short test_vec_pmsum_beh(void)
 {
   vector unsigned short a = H_INIT1
   vector unsigned short b = H_INIT2
   return vec_pmsum_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumh
 }
 
 // CHECK-LABEL: @test_vec_pmsum_bew
-vector unsigned long long test_vec_pmsum_bew(void)
+vector unsigned int test_vec_pmsum_bew(void)
 {
   vector unsigned int a = W_INIT1
   vector unsigned int b = W_INIT2
   return vec_pmsum_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumw
 }
 
 // CHECK-LABEL: @test_vec_pmsum_bed
-vector unsigned __int128 test_vec_pmsum_bed(void)
+vector unsigned long long test_vec_pmsum_bed(void)
 {
   vector unsigned long long a = D_INIT1
   vector unsigned long long b = D_INIT2
   return vec_pmsum_be(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vpmsumd
 }
 

clang/test/CodeGen/PowerPC/builtins-ppc-error.c

 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \
 // RUN:   -triple powerpc64-unknown-unknown -fsyntax-only   \
 // RUN: -flax-vector-conversions=integer \
 // RUN: -Wall -Werror -verify %s
 
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector  \
 // RUN: -triple powerpc64le-unknown-unknown -fsyntax-only    \
 // RUN: -flax-vector-conversions=integer \
 // RUN: -Wall -Werror -verify %s
 
-// FIXME: Fix <altivec.h> so this test also passes under
-// -flax-vector-conversions=none (this last test exists to produce an error if
-// we change the default to that without fixing <altivec.h>).
-// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \
-// RUN:   -triple powerpc64-unknown-unknown -fsyntax-only   \
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power9-vector \
+// RUN: -triple powerpc64-unknown-unknown -fsyntax-only   \
 // RUN: -Wall -Werror -verify %s
 
 #include <altivec.h>
 
 extern vector signed int vsi;
-extern vector signed int vui;
+extern vector unsigned int vui;
 extern vector float vf;
 extern vector unsigned char vuc;
 extern vector signed __int128 vsllli;
 
 void testInsertWord(void) {
   int index = 5;
-  vector unsigned char v1 = vec_insert4b(vsi, vuc, index); // expected-error {{argument to '__builtin_vsx_insertword' must be a constant integer}}
+  vector unsigned char v1 = vec_insert4b(vui, vuc, index); // expected-error {{argument to '__builtin_vsx_insertword' must be a constant integer}}
   vector unsigned long long v2 = vec_extract4b(vuc, index);   // expected-error {{argument to '__builtin_vsx_extractuword' must be a constant integer}}
 }
 
 void testXXPERMDI(int index) {
   vec_xxpermdi(vsi); //expected-error {{too few arguments to function call, expected 3, have 1}}
   vec_xxpermdi(vsi, vsi, 2, 4); //expected-error {{too many arguments to function call, expected 3, have 4}}
   vec_xxpermdi(vsi, vsi, index); //expected-error {{argument 3 to '__builtin_vsx_xxpermdi' must be a 2-bit unsigned literal (i.e. 0, 1, 2 or 3)}}
   vec_xxpermdi(1, 2, 3); //expected-error {{first two arguments to '__builtin_vsx_xxpermdi' must be vectors}}

clang/test/CodeGen/PowerPC/builtins-ppc-int128.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64-unknown-unknown -target-cpu pwr8 \
 // RUN:   -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | FileCheck %s
-// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64le-unknown-unknown -target-cpu pwr8 \
 // RUN:   -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | \
 // RUN:   FileCheck %s -check-prefix=CHECK-LE
 #include <altivec.h>
 
 vector signed __int128 res_vslll;
 unsigned long long aull[2] = { 1L, 2L };
 

clang/test/CodeGen/PowerPC/builtins-ppc-ld-st-rmb.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=BE-PWR8
-// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=LE-PWR8
 
-// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr9 -o - | FileCheck %s -check-prefix=BE-PWR9
-// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr9 -o - | FileCheck %s -check-prefix=LE-PWR9
-// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -triple powerpc-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr9 -o - | FileCheck %s -check-prefix=BE32-PWR9
 
 #include <altivec.h>
 // BE-PWR8-LABEL: @test_ldrmb1(
 // BE-PWR8-NEXT:  entry:
 // BE-PWR8-NEXT:    [[PTR_ADDR:%.*]] = alloca i8*, align 8
 // BE-PWR8-NEXT:    store i8* [[PTR:%.*]], i8** [[PTR_ADDR]], align 8
 // BE-PWR8-NEXT:    [[TMP0:%.*]] = load i8*, i8** [[PTR_ADDR]], align 8

clang/test/CodeGen/PowerPC/builtins-ppc-p10vector-error.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-unknown -target-cpu pwr10 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-aix -target-cpu pwr10 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-aix -target-cpu pwr10 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 #include <altivec.h>
 
 vector unsigned char vuca;
 vector unsigned short vusa;
 vector unsigned int vuia;
 vector unsigned long long vulla;

clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \
 // RUN:   -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK
 
 #include <altivec.h>
 
 vector signed __int128 vi128a;
 vector signed char vsca, vscb;
 vector unsigned char vuca, vucb, vucc;

 
 vector double test_vec_blend_d(void) {
   // CHECK: @llvm.ppc.vsx.xxblendvd(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64>
   // CHECK-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double>
   // CHECK-NEXT: ret <2 x double>
   return vec_blendv(vda, vdb, vullc);
 }
 
+// CHECK-BE-LABEL: @test_vec_replace_elt_si(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = load i32, i32* @sia, align 4
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 0)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-BE-NEXT:    ret <4 x i32> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_elt_si(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = load i32, i32* @sia, align 4
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 12)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-LE-NEXT:    ret <4 x i32> [[TMP6]]
+//
 vector signed int test_vec_replace_elt_si(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 0
-  // CHECK-BE-NEXT: ret <4 x i32>
-  // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 12
-  // CHECK-LE-NEXT: ret <4 x i32>
   return vec_replace_elt(vsia, sia, 0);
 }
 
+// CHECK-BE-LABEL: @test_vec_replace_elt_ui(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = load i32, i32* @uia, align 4
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 4)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-BE-NEXT:    ret <4 x i32> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_elt_ui(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = load i32, i32* @uia, align 4
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-LE-NEXT:    ret <4 x i32> [[TMP6]]
+//
 vector unsigned int test_vec_replace_elt_ui(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 4
-  // CHECK-BE-NEXT: ret <4 x i32>
-  // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 8
-  // CHECK-LE-NEXT: ret <4 x i32>
   return vec_replace_elt(vuia, uia, 1);
 }
 
+// CHECK-BE-LABEL: @test_vec_replace_elt_f(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = load float, float* @fa, align 4
+// CHECK-BE-NEXT:    [[CONV:%.*]] = fptoui float [[TMP2]] to i32
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 8)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
+// CHECK-BE-NEXT:    ret <4 x float> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_elt_f(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = load float, float* @fa, align 4
+// CHECK-LE-NEXT:    [[CONV:%.*]] = fptoui float [[TMP2]] to i32
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 4)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
+// CHECK-LE-NEXT:    ret <4 x float> [[TMP6]]
+//
 vector float test_vec_replace_elt_f(void) {
-  // CHECK-BE: bitcast float %{{.+}} to i32
-  // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 8
-  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
-  // CHECK-BE-NEXT: ret <4 x float>
-  // CHECK-LE: bitcast float %{{.+}} to i32
-  // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 4
-  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <4 x float>
-  // CHECK-LE-NEXT: ret <4 x float>
   return vec_replace_elt(vfa, fa, 2);
 }
 
+// CHECK-BE-LABEL: @test_vec_replace_elt_sll(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = load i64, i64* @llb, align 8
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-BE-NEXT:    ret <2 x i64> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_elt_sll(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = load i64, i64* @llb, align 8
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-LE-NEXT:    ret <2 x i64> [[TMP6]]
+//
 vector signed long long test_vec_replace_elt_sll(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
-  // CHECK-BE-NEXT: ret <2 x i64>
-  // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
-  // CHECK-LE-NEXT: ret <2 x i64>
   return vec_replace_elt(vslla, llb, 0);
 }
 
+// CHECK-BE-LABEL: @test_vec_replace_elt_ull(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = load i64, i64* @ulla, align 8
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-BE-NEXT:    ret <2 x i64> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_elt_ull(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = load i64, i64* @ulla, align 8
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-LE-NEXT:    ret <2 x i64> [[TMP6]]
+//
 vector unsigned long long test_vec_replace_elt_ull(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
-  // CHECK-BE-NEXT: ret <2 x i64>
-  // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
-  // CHECK-LE-NEXT: ret <2 x i64>
   return vec_replace_elt(vulla, ulla, 0);
 }
 
+// CHECK-BE-LABEL: @test_vec_replace_elt_d(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = load double, double* @da, align 8
+// CHECK-BE-NEXT:    [[CONV:%.*]] = fptoui double [[TMP2]] to i64
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
+// CHECK-BE-NEXT:    ret <2 x double> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_elt_d(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = load double, double* @da, align 8
+// CHECK-LE-NEXT:    [[CONV:%.*]] = fptoui double [[TMP2]] to i64
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 0)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
+// CHECK-LE-NEXT:    ret <2 x double> [[TMP6]]
+//
 vector double test_vec_replace_elt_d(void) {
-  // CHECK-BE: bitcast double %{{.+}} to i64
-  // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
-  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double>
-  // CHECK-BE-NEXT: ret <2 x double>
-  // CHECK-LE: bitcast double %{{.+}} to i64
-  // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
-  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <2 x double>
-  // CHECK-LE-NEXT: ret <2 x double>
   return vec_replace_elt(vda, da, 1);
 }
 
-vector unsigned char test_vec_replace_unaligned_si(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 6
-  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
-  // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 6
-  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
-  // CHECK-LE-NEXT: ret <16 x i8>
+// CHECK-BE-LABEL: @test_vec_replace_unaligned_si(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = load i32, i32* @sia, align 4
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP2]], i32 [[TMP3]], i32 6)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-BE-NEXT:    ret <4 x i32> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_unaligned_si(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = load i32, i32* @sia, align 4
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP2]], i32 [[TMP3]], i32 6)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-LE-NEXT:    ret <4 x i32> [[TMP6]]
+//
+vector signed int test_vec_replace_unaligned_si(void) {
   return vec_replace_unaligned(vsia, sia, 6);
 }
 
-vector unsigned char test_vec_replace_unaligned_ui(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 8
-  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
-  // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 4
-  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
-  // CHECK-LE-NEXT: ret <16 x i8>
+// CHECK-BE-LABEL: @test_vec_replace_unaligned_ui(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = load i32, i32* @uia, align 4
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP2]], i32 [[TMP3]], i32 8)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-BE-NEXT:    ret <4 x i32> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_unaligned_ui(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = load i32, i32* @uia, align 4
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP2]], i32 [[TMP3]], i32 8)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
+// CHECK-LE-NEXT:    ret <4 x i32> [[TMP6]]
+//
+vector unsigned int test_vec_replace_unaligned_ui(void) {
   return vec_replace_unaligned(vuia, uia, 8);
 }
 
-vector unsigned char test_vec_replace_unaligned_f(void) {
-  // CHECK-BE: bitcast float %{{.+}} to i32
-  // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 12
-  // CHECK-BE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
-  // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: bitcast float %{{.+}} to i32
-  // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsw(<4 x i32> %{{.+}}, i32 %{{.+}}, i32 0
-  // CHECK-LE-NEXT: bitcast <4 x i32> %{{.*}} to <16 x i8>
-  // CHECK-LE-NEXT: ret <16 x i8>
+// CHECK-BE-LABEL: @test_vec_replace_unaligned_f(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = load float, float* @fa, align 4
+// CHECK-BE-NEXT:    [[CONV:%.*]] = fptoui float [[TMP3]] to i32
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP2]], i32 [[CONV]], i32 12)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
+// CHECK-BE-NEXT:    ret <4 x float> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_unaligned_f(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = load float, float* @fa, align 4
+// CHECK-LE-NEXT:    [[CONV:%.*]] = fptoui float [[TMP3]] to i32
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP2]], i32 [[CONV]], i32 12)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
+// CHECK-LE-NEXT:    ret <4 x float> [[TMP6]]
+//
+vector float test_vec_replace_unaligned_f(void) {
   return vec_replace_unaligned(vfa, fa, 12);
 }
 
-vector unsigned char test_vec_replace_unaligned_sll(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 6
-  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
-  // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 2
-  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
-  // CHECK-LE-NEXT: ret <16 x i8>
+// CHECK-BE-LABEL: @test_vec_replace_unaligned_sll(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = load i64, i64* @llb, align 8
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP2]], i64 [[TMP3]], i32 6)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-BE-NEXT:    ret <2 x i64> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_unaligned_sll(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = load i64, i64* @llb, align 8
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP2]], i64 [[TMP3]], i32 6)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-LE-NEXT:    ret <2 x i64> [[TMP6]]
+//
+vector signed long long test_vec_replace_unaligned_sll(void) {
   return vec_replace_unaligned(vslla, llb, 6);
 }
 
-vector unsigned char test_vec_replace_unaligned_ull(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 7
-  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
-  // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 1
-  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
-  // CHECK-LE-NEXT: ret <16 x i8>
+// CHECK-BE-LABEL: @test_vec_replace_unaligned_ull(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = load i64, i64* @ulla, align 8
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP2]], i64 [[TMP3]], i32 7)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-BE-NEXT:    ret <2 x i64> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_unaligned_ull(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = load i64, i64* @ulla, align 8
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP2]], i64 [[TMP3]], i32 7)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64>
+// CHECK-LE-NEXT:    ret <2 x i64> [[TMP6]]
+//
+vector unsigned long long test_vec_replace_unaligned_ull(void) {
   return vec_replace_unaligned(vulla, ulla, 7);
 }
 
-vector unsigned char test_vec_replace_unaligned_d(void) {
-  // CHECK-BE: bitcast double %{{.+}} to i64
-  // CHECK-BE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 8
-  // CHECK-BE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
-  // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: bitcast double %{{.+}} to i64
-  // CHECK-LE-NEXT: @llvm.ppc.altivec.vinsd(<2 x i64> %{{.+}}, i64 %{{.+}}, i32 0
-  // CHECK-LE-NEXT: bitcast <2 x i64> %{{.*}} to <16 x i8>
-  // CHECK-LE-NEXT: ret <16 x i8>
+// CHECK-BE-LABEL: @test_vec_replace_unaligned_d(
+// CHECK-BE-NEXT:  entry:
+// CHECK-BE-NEXT:    [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16
+// CHECK-BE-NEXT:    [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-BE-NEXT:    [[TMP3:%.*]] = load double, double* @da, align 8
+// CHECK-BE-NEXT:    [[CONV:%.*]] = fptoui double [[TMP3]] to i64
+// CHECK-BE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP2]], i64 [[CONV]], i32 8)
+// CHECK-BE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-BE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
+// CHECK-BE-NEXT:    ret <2 x double> [[TMP6]]
+//
+// CHECK-LE-LABEL: @test_vec_replace_unaligned_d(
+// CHECK-LE-NEXT:  entry:
+// CHECK-LE-NEXT:    [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16
+// CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// CHECK-LE-NEXT:    [[TMP3:%.*]] = load double, double* @da, align 8
+// CHECK-LE-NEXT:    [[CONV:%.*]] = fptoui double [[TMP3]] to i64
+// CHECK-LE-NEXT:    [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP2]], i64 [[CONV]], i32 8)
+// CHECK-LE-NEXT:    [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
+// CHECK-LE-NEXT:    [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
+// CHECK-LE-NEXT:    ret <2 x double> [[TMP6]]
+//
+vector double test_vec_replace_unaligned_d(void) {
   return vec_replace_unaligned(vda, da, 8);
 }
 
+
 vector unsigned char test_vec_insertl_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_insertl(uca, vuca, uia);
 }
 
int test_vec_all_ge_u128(void) {
   // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3)
   // CHECK-NEXT: ret i32
   return vec_all_ge(vui128a, vui128b);
 }
 
 vector signed __int128 test_vec_rl_s128(void) {
   // CHECK-LABEL: @test_vec_rl_s128(
   // CHECK: sub <1 x i128>
   // CHECK-NEXT: lshr <1 x i128>
   // CHECK-NEXT: or <1 x i128>
   // CHECK-NEXT: ret <1 x i128>
-  return vec_rl(vsi128a, vsi128b);
+  return vec_rl(vsi128a, vui128b);
 }
 
 vector unsigned __int128 test_vec_rl_u128(void) {
   // CHECK-LABEL: @test_vec_rl_u128(
   // CHECK: sub <1 x i128>
   // CHECK: lshr <1 x i128>
   // CHECK: or <1 x i128>
   // CHECK-NEXT: ret <1 x i128>

clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -target-feature +altivec -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -target-feature +altivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC
 // Added -target-feature +vsx above to avoid errors about "vector double" and to
 // generate the correct errors for functions that are only overloaded with VSX
 // (vec_cmpge, vec_cmple). Without this option, there is only one overload so
 // it is selected.
 #include <altivec.h>
 
 void dummy() { }

 // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK: bitcast <4 x i32> [[T3]] to <16 x i8>
 // CHECK-LE: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
 // CHECK-LE: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
 // CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK-LE: bitcast <4 x i32> [[T3]] to <16 x i8>
 // CHECK-PPC: error: assigning to
 
-  res_vsc =  vec_eqv(vbc, vbc);
+  res_vbc =  vec_eqv(vbc, vbc);
 // CHECK: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
 // CHECK: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
 // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK: bitcast <4 x i32> [[T3]] to <16 x i8>
 // CHECK-LE: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
 // CHECK-LE: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
 // CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK-LE: bitcast <4 x i32> [[T3]] to <16 x i8>

 // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK: bitcast <4 x i32> [[T3]] to <8 x i16>
 // CHECK-LE: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
 // CHECK-LE: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
 // CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK-LE: bitcast <4 x i32> [[T3]] to <8 x i16>
 // CHECK-PPC: error: assigning to
 
-  res_vss =  vec_eqv(vbs, vbs);
+  res_vbs =  vec_eqv(vbs, vbs);
 // CHECK: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
 // CHECK: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
 // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK: bitcast <4 x i32> [[T3]] to <8 x i16>
 // CHECK-LE: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
 // CHECK-LE: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
 // CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK-LE: bitcast <4 x i32> [[T3]] to <8 x i16>

 // CHECK-LE: bitcast <4 x i32> [[T3]] to <8 x i16>
 // CHECK-PPC: error: assigning to
 
   res_vsi =  vec_eqv(vsi, vsi);
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}})
 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}})
 // CHECK-PPC: error: assigning to
 
-  res_vsi =  vec_eqv(vbi, vbi);
+  res_vbi =  vec_eqv(vbi, vbi);
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}})
 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}})
 // CHECK-PPC: error: assigning to
 
   res_vui =  vec_eqv(vui, vui);
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}})
 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> {{.*}}, <4 x i32> {{.+}})
 // CHECK-PPC: error: assigning to
 
   res_vsll =  vec_eqv(vsll, vsll);
 // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK: bitcast <4 x i32> [[T3]] to <2 x i64>
 // CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK-LE: bitcast <4 x i32> [[T3]] to <2 x i64>
 // CHECK-PPC: error: assigning to
 
-  res_vsll =  vec_eqv(vbll, vbll);
+  res_vbll =  vec_eqv(vbll, vbll);
 // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK: bitcast <4 x i32> [[T3]] to <2 x i64>
 // CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
 // CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
 // CHECK-LE: bitcast <4 x i32> [[T3]] to <2 x i64>
// CHECK-LE: @llvm.ppc.altivec.vminud
   /* vec_nand */
   res_vsc = vec_nand(vsc, vsc);
 // CHECK: [[T1:%.+]] = and <16 x i8>
 // CHECK: xor <16 x i8> [[T1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 // CHECK-LE: [[T1:%.+]] = and <16 x i8>
 // CHECK-LE: xor <16 x i8> [[T1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 // CHECK-PPC: warning: implicit declaration of function 'vec_nand' is invalid in C99
 
-  res_vsc = vec_nand(vbc, vbc);
+  res_vbc = vec_nand(vbc, vbc);
 // CHECK: [[T1:%.+]] = and <16 x i8>
 // CHECK: xor <16 x i8> [[T1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 // CHECK-LE: [[T1:%.+]] = and <16 x i8>
 // CHECK-LE: xor <16 x i8> [[T1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   
   res_vuc = vec_nand(vuc, vuc);
 // CHECK: [[T1:%.+]] = and <16 x i8>
 // CHECK: xor <16 x i8> [[T1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 // CHECK-LE: [[T1:%.+]] = and <16 x i8>
 // CHECK-LE: xor <16 x i8> [[T1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   
   res_vss = vec_nand(vss, vss);
 // CHECK: [[T1:%.+]] = and <8 x i16>
 // CHECK: xor <8 x i16> [[T1]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 // CHECK-LE: [[T1:%.+]] = and <8 x i16>
 // CHECK-LE: xor <8 x i16> [[T1]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 
-  res_vss = vec_nand(vbs, vbs);
+  res_vbs = vec_nand(vbs, vbs);
 // CHECK: [[T1:%.+]] = and <8 x i16>
 // CHECK: xor <8 x i16> [[T1]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 // CHECK-LE: [[T1:%.+]] = and <8 x i16>
 // CHECK-LE: xor <8 x i16> [[T1]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 
   res_vus = vec_nand(vus, vus);
 // CHECK: [[T1:%.+]] = and <8 x i16>
 // CHECK: xor <8 x i16> [[T1]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 // CHECK-LE: [[T1:%.+]] = and <8 x i16>
 // CHECK-LE: xor <8 x i16> [[T1]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 
   res_vsi = vec_nand(vsi, vsi);
 // CHECK: [[T1:%.+]] = and <4 x i32>
 // CHECK: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 // CHECK-LE: [[T1:%.+]] = and <4 x i32>
 // CHECK-LE: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 
-  res_vsi = vec_nand(vbi, vbi);
+  res_vbi = vec_nand(vbi, vbi);
 // CHECK: [[T1:%.+]] = and <4 x i32>
 // CHECK: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 // CHECK-LE: [[T1:%.+]] = and <4 x i32>
 // CHECK-LE: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 
   res_vui = vec_nand(vui, vui);
 // CHECK: [[T1:%.+]] = and <4 x i32>
 // CHECK: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 // CHECK-LE: [[T1:%.+]] = and <4 x i32>
 // CHECK-LE: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 
   res_vf = vec_nand(vfa, vfa);
 // CHECK: [[T1:%.+]] = and <4 x i32>
 // CHECK: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 // CHECK-LE: [[T1:%.+]] = and <4 x i32>
 // CHECK-LE: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
 
   res_vsll = vec_nand(vsll, vsll);
 // CHECK: [[T1:%.+]] = and <2 x i64>
 // CHECK: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
 // CHECK-LE: [[T1:%.+]] = and <2 x i64>
 // CHECK-LE: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
 
-  res_vsll = vec_nand(vbll, vbll);
+  res_vbll = vec_nand(vbll, vbll);
 // CHECK: [[T1:%.+]] = and <2 x i64>
 // CHECK: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
 // CHECK-LE: [[T1:%.+]] = and <2 x i64>
 // CHECK-LE: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
 
   res_vull = vec_nand(vull, vull);
 // CHECK: [[T1:%.+]] = and <2 x i64>
 // CHECK: xor <2 x i64> [[T1]], <i64 -1, i64 -1>

 // CHECK: sub <1 x i128>
 // CHECK-LE: sub <1 x i128>
 
   /* vec_vbpermq */
   res_vsll = vec_vbpermq(vsc, vsc);
 // CHECK: llvm.ppc.altivec.vbpermq
 // CHECK-LE: llvm.ppc.altivec.vbpermq
 
-  res_vull = vec_vbpermq(vuc, vuc);
+  res_vsll = vec_vbpermq(vuc, vuc);
 // CHECK: llvm.ppc.altivec.vbpermq
 // CHECK-LE: llvm.ppc.altivec.vbpermq
 // CHECK-PPC: warning: implicit declaration of function 'vec_vbpermq'
 
   /* vec_vgbbd */
   res_vsc = vec_vgbbd(vsc);
 // CHECK: llvm.ppc.altivec.vgbbd
 // CHECK-LE: llvm.ppc.altivec.vgbbd
// CHECK-LE: llvm.ppc.altivec.vgbbd
   res_vull = vec_gbb(vull);
 // CHECK: llvm.ppc.altivec.vgbbd
 // CHECK-LE: llvm.ppc.altivec.vgbbd
 
   res_vull = vec_bperm(vux, vuc);
   // CHECK: llvm.ppc.altivec.vbpermq
   // CHECK-LE: llvm.ppc.altivec.vbpermq
 
-  res_vull = vec_bperm(vuc, vuc);
+  res_vuc = vec_bperm(vuc, vuc);
   // CHECK: llvm.ppc.altivec.vbpermq
   // CHECK-LE: llvm.ppc.altivec.vbpermq
 
   res_vsll = vec_neg(vsll);
 // CHECK: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
 // CHECK-LE: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
 // CHECK_PPC: call to 'vec_neg' is ambiguous
 

clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
 // RUN:   -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -flax-vector-conversions=integer \
 // RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
 
 // RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
 // RUN:   -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -flax-vector-conversions=integer \
 // RUN:   -o - | FileCheck %s
 
-// FIXME: This last test is intended to fail if the default is changed to
-// -flax-vector-conversions=none and <altivec.h> isn't fixed first.
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
 // RUN:   -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
 
 #include <altivec.h>
 
 vector signed char vsca, vscb;
 vector unsigned char vuca, vucb;
 vector bool char vbca, vbcb;

clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
+// RUN: -triple powerpc64-unknown-linux -emit-llvm %s -o - | FileCheck %s
+//
+// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
+// RUN: -triple powerpc64le-unknown-linux -emit-llvm %s -o - | FileCheck %s 
+
+// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
+// RUN: -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s
+#include <altivec.h>
+
+// CHECK-LABEL: @test_vaddeuqm_c(
+// CHECK:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[TMP4]]
+vector unsigned char test_vaddeuqm_c(vector unsigned char a, vector unsigned char b,
+                                vector unsigned char c) {
+  return __builtin_altivec_vaddeuqm_c(a, b, c);
+}
+
+// CHECK-LABEL: @test_vaddcuq_c(
+// CHECK:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+vector unsigned char test_vaddcuq_c(vector unsigned char a, vector unsigned char b) {
+  return __builtin_altivec_vaddcuq_c(a, b);
+}
+
+// CHECK-LABEL: @test_vaddecuq_c(
+// CHECK:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[TMP4]]
+vector unsigned char test_vaddecuq_c(vector unsigned char a, vector unsigned char b,
+                                vector unsigned char c) {
+  return __builtin_altivec_vaddecuq_c(a, b, c);
+}
+
+// CHECK-LABEL: @test_vsubeuqm_c(
+// CHECK:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[TMP4]]
+vector unsigned char test_vsubeuqm_c(vector unsigned char a, vector unsigned char b,
+                                vector unsigned char c) {
+  return __builtin_altivec_vsubeuqm_c(a, b, c);
+}
+
+// CHECK-LABEL: @test_vsubcuq_c(
+// CHECK:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+vector unsigned char test_vsubcuq_c(vector unsigned char a, vector unsigned char b) {
+  return __builtin_altivec_vsubcuq_c(a, b);
+}
+
+// CHECK-LABEL: @test_vsubecuq_c(
+// CHECK:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]])
+// CHECK-NEXT:    [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
+// CHECK-NEXT:    ret <16 x i8> [[TMP4]]
+vector unsigned char test_vsubecuq_c(vector unsigned char a, vector unsigned char b,
+                                vector unsigned char c) {
+  return __builtin_altivec_vsubecuq_c(a, b, c);
+}

clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \
+// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \
 // RUN:   -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck \
 // RUN:   %s -check-prefix=CHECK-LE
-// RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \
+// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \
 // RUN:   -triple powerpc64-aix-unknown -emit-llvm %s -o - | FileCheck \
 // RUN:   %s -check-prefix=CHECK-AIX
-// RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \
+// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \
 // RUN:   -triple powerpc-aix-unknown -emit-llvm %s -o - | FileCheck \
 // RUN:   %s -check-prefix=CHECK-AIX
 #include <altivec.h>
 // CHECK-LE-LABEL: @test_subc(
 // CHECK-LE-NEXT:  entry:
 // CHECK-LE-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
 // CHECK-LE-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
 // CHECK-LE-NEXT:    [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) #[[ATTR3:[0-9]+]]
 // CHECK-LE-NEXT:    [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>

clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
 // RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
 
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
 // RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - \
 // RUN: | FileCheck %s -check-prefix=CHECK-LE
 
 // RUN: not %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpc-unknown-unknown \
 // RUN: -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC
 #include <altivec.h>
 
 // CHECK-PPC: error: __int128 is not supported on this target

clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c

 // REQUIRES: powerpc-registered-target
 
-// RUN: %clang_cc1 -target-feature +vsx -target-cpu pwr10 \
-// RUN:   -triple powerpc64le-unknown-unknown -fsyntax-only %s -verify
-// RUN: %clang_cc1 -target-feature +vsx -target-cpu pwr10 \
-// RUN:   -triple powerpc64-unknown-unknown -fsyntax-only %s -verify
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \
+// RUN:   -triple powerpc64le-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_SI
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \
+// RUN:   -triple powerpc64-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_F
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \
+// RUN:   -triple powerpc64le-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_SLL
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \
+// RUN:   -triple powerpc64-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_ELT_D
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \
+// RUN:   -triple powerpc64le-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify -D __TEST_UNALIGNED_UI
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -target-cpu pwr10 \
+// RUN:   -triple powerpc64-unknown-unknown -emit-llvm -ferror-limit 10 %s -verify
 
 #include <altivec.h>
 
 vector signed int vsia;
 vector unsigned int vuia;
 vector signed long long vslla;
 vector unsigned long long vulla;
 vector float vfa;
 vector double vda;
 signed int sia;
 unsigned int uia;
 signed long long slla;
 unsigned long long ulla;
 float fa;
 double da;
 
+#ifdef __TEST_ELT_SI
 vector signed int test_vec_replace_elt_si(void) {
-  return vec_replace_elt(vsia, sia, 13); // expected-error {{argument value 13 is outside the valid range [0, 12]}}
-}
-
-vector unsigned int test_vec_replace_elt_ui(void) {
-  return vec_replace_elt(vuia, sia, 1); // expected-error {{arguments are of different types ('unsigned int' vs 'int')}}
+  return vec_replace_elt(vsia, sia, 13); // expected-error {{element number out of range [0..3]}}
 }
 
+#elif defined(__TEST_ELT_F)
 vector float test_vec_replace_elt_f(void) {
-  return vec_replace_elt(vfa, fa, 20); // expected-error {{argument value 20 is outside the valid range [0, 12]}}
-}
-
-vector float test_vec_replace_elt_f_2(void) {
-  return vec_replace_elt(vfa, da, 0); // expected-error {{arguments are of different types ('float' vs 'double')}}
+  return vec_replace_elt(vfa, fa, 20); // expected-error {{element number out of range [0..3]}}
 }
 
+#elif defined(__TEST_ELT_SLL)
 vector signed long long test_vec_replace_elt_sll(void) {
-  return vec_replace_elt(vslla, slla, 9); // expected-error {{argument value 9 is outside the valid range [0, 8]}}
-}
-
-vector unsigned long long test_vec_replace_elt_ull(void) {
-  return vec_replace_elt(vulla, vda, 0); // expected-error {{arguments are of different types ('unsigned long long' vs '__vector double' (vector of 2 'double' values))}}
-}
-
-vector unsigned long long test_vec_replace_elt_ull_2(void) {
-  return vec_replace_elt(vulla, vulla, vsia); // expected-error {{argument to '__builtin_altivec_vec_replace_elt' must be a constant integer}}
+  return vec_replace_elt(vslla, slla, 9); // expected-error {{element number out of range [0..1]}}
 }
 
+#elif defined(__TEST_ELT_D)
 vector double test_vec_replace_elt_d(void) {
-  return vec_replace_elt(vda, da, 33); // expected-error {{argument value 33 is outside the valid range [0, 8]}}
-}
-
-vector unsigned char test_vec_replace_unaligned_si(void) {
-  return vec_replace_unaligned(vsia, da, 6); // expected-error {{arguments are of different types ('int' vs 'double')}}
-}
-
-vector unsigned char test_vec_replace_unaligned_ui(void) {
-  return vec_replace_unaligned(vuia, uia, 14); // expected-error {{argument value 14 is outside the valid range [0, 12]}}
-}
-
-vector unsigned char test_vec_replace_unaligned_f(void) {
-  return vec_replace_unaligned(vfa, fa, 19); // expected-error {{argument value 19 is outside the valid range [0, 12]}}
-}
-
-vector unsigned char test_vec_replace_unaligned_sll(void) {
-  return vec_replace_unaligned(vslla, fa, 0); // expected-error {{arguments are of different types ('long long' vs 'float')}}
-}
-
-vector unsigned char test_vec_replace_unaligned_ull(void) {
-  return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{argument value 12 is outside the valid range [0, 8]}}
-}
-
-vector unsigned char test_vec_replace_unaligned_d(void) {
-  return vec_replace_unaligned(vda, fa, 8); // expected-error {{arguments are of different types ('double' vs 'float')}}
+  return vec_replace_elt(vda, da, 33); // expected-error {{element number out of range [0..1]}}
 }
 
-vector unsigned char test_vec_replace_unaligned_d_2(void) {
-  return vec_replace_unaligned(vda, vda, da); // expected-error {{argument to '__builtin_altivec_vec_replace_unaligned' must be a constant integer}}
+#elif defined(__TEST_UNALIGNED_UI)
+vector unsigned int test_vec_replace_unaligned_ui(void) {
+  return vec_replace_unaligned(vuia, uia, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} \
+                                               // expected-error {{argument value 16 is outside the valid range [0, 15]}} \
+                                               // expected-error {{argument value 16 is outside the valid range [0, 15]}} \
+                                               // expected-error {{argument value 16 is outside the valid range [0, 15]}} \
+                                               // expected-error {{argument value 16 is outside the valid range [0, 15]}} \
+                                               // expected-error {{argument value 16 is outside the valid range [0, 15]}}
+}
+
+#else
+vector unsigned long long test_vec_replace_unaligned_ull(void) {
+  return vec_replace_unaligned(vulla, ulla, 19); // expected-error {{argument value 19 is outside the valid range [0, 15]}} \
+                                                 // expected-error {{argument value 19 is outside the valid range [0, 15]}} \
+                                                 // expected-error {{argument value 19 is outside the valid range [0, 15]}} \
+                                                 // expected-error {{argument value 19 is outside the valid range [0, 15]}} \
+                                                 // expected-error {{argument value 19 is outside the valid range [0, 15]}} \
+                                                 // expected-error {{argument value 19 is outside the valid range [0, 15]}}
 }
+#endif

clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE
 #include <altivec.h>
 
 vector bool char vbc = { 0, 1, 0, 1, 0, 1, 0, 1,
                          0, 1, 0, 1, 0, 1, 0, 1 };
 vector signed char vsc = { -8,  9, -10, 11, -12, 13, -14, 15,
                            -0,  1,  -2,  3,  -4,  5,  -6,  7};
 vector unsigned char vuc = { 8,  9, 10, 11, 12, 13, 14, 15,
                              0,  1,  2,  3,  4,  5,  6,  7};

 // CHECK-LE: xor <2 x i64>
 
   res_vull = vec_nor(vull, vull);
 // CHECK: or <2 x i64>
 // CHECK: xor <2 x i64>
 // CHECK-LE: or <2 x i64>
 // CHECK-LE: xor <2 x i64>
 
-  res_vull = vec_nor(vbll, vbll);
+  res_vbll = vec_nor(vbll, vbll);
 // CHECK: or <2 x i64>
 // CHECK: xor <2 x i64>
 // CHECK-LE: or <2 x i64>
 // CHECK-LE: xor <2 x i64>
 
   res_vd = vec_nor(vd, vd);
 // CHECK: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
 // CHECK: [[OR:%.+]] = or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: fptosi <2 x double> %{{.*}} to <2 x i64>
   // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float>
 
   res_vsll = vec_ctsl(vd, 3);
   // CHECK: fmul <2 x double> {{%.*}}, <double 8.000000e+00, double 8.000000e+00>
   // CHECK: fptosi <2 x double> {{%.*}} to <2 x i64>
   // CHECK-LE: fmul <2 x double> {{%.*}}, <double 8.000000e+00, double 8.000000e+00>
   // CHECK-LE: fptosi <2 x double> {{%.*}} to <2 x i64>
 
-  res_vsll = vec_ctu(vd, 0);
+  res_vull = vec_ctu(vd, 0);
 // CHECK: fmul <2 x double>
 // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>
 // CHECK-LE: fmul <2 x double>
 // CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64>
 
-  res_vsll = vec_ctu(vd, 31);
+  res_vull = vec_ctu(vd, 31);
 // CHECK: fmul <2 x double>
 // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>
 // CHECK-LE: fmul <2 x double>
 // CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64>
 
   res_vull = vec_ctul(vf, 3);
   // CHECK: fmul <4 x float> {{%.*}}, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
   // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcvspuxds(<4 x float>

 res_vd = vec_xlds(sll, ad);
 // CHECK: load double
 // CHECK: insertelement <2 x double>
 // CHECK: shufflevector <2 x double>
 // CHECK-LE: load double
 // CHECK-LE: insertelement <2 x double>
 // CHECK-LE: shufflevector <2 x double>
 
-res_vsll = vec_load_splats(sll, asi);
+res_vsi = vec_load_splats(sll, asi);
 // CHECK: load i32
 // CHECK: insertelement <4 x i32>
 // CHECK: shufflevector <4 x i32>
 // CHECK-LE: load i32
 // CHECK-LE: insertelement <4 x i32>
 // CHECK-LE: shufflevector <4 x i32>
 
-res_vsll = vec_load_splats(ull, asi);
+res_vsi = vec_load_splats(ull, asi);
 // CHECK: load i32
 // CHECK: insertelement <4 x i32>
 // CHECK: shufflevector <4 x i32>
 // CHECK-LE: load i32
 // CHECK-LE: insertelement <4 x i32>
 // CHECK-LE: shufflevector <4 x i32>
 
-res_vsll = vec_load_splats(sll, aui);
+res_vui = vec_load_splats(sll, aui);
 // CHECK: load i32
 // CHECK: insertelement <4 x i32>
 // CHECK: shufflevector <4 x i32>
 // CHECK-LE: load i32
 // CHECK-LE: insertelement <4 x i32>
 // CHECK-LE: shufflevector <4 x i32>
 
-res_vsll = vec_load_splats(ull, aui);
+res_vui = vec_load_splats(ull, aui);
 // CHECK: load i32
 // CHECK: insertelement <4 x i32>
 // CHECK: shufflevector <4 x i32>
 // CHECK-LE: load i32
 // CHECK-LE: insertelement <4 x i32>
 // CHECK-LE: shufflevector <4 x i32>
 
-res_vsll = vec_load_splats(sll, af);
+res_vf = vec_load_splats(sll, af);
 // CHECK: load float
 // CHECK: insertelement <4 x float>
 // CHECK: shufflevector <4 x float>
 // CHECK-LE: load float
 // CHECK-LE: insertelement <4 x float>
 // CHECK-LE: shufflevector <4 x float>
 
-res_vsll = vec_load_splats(ull, af);
+res_vf = vec_load_splats(ull, af);
 // CHECK: load float
 // CHECK: insertelement <4 x float>
 // CHECK: shufflevector <4 x float>
 // CHECK-LE: load float
 // CHECK-LE: insertelement <4 x float>
 // CHECK-LE: shufflevector <4 x float>
 
 vec_xst_be(vsll, sll, asll);

 res_vsll = vec_permi(vsll, vsll, 2);
 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>
 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>
 
 res_vull = vec_permi(vull, vull, 3);
 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
 
-res_vull = vec_permi(vbll, vbll, 3);
+res_vbll = vec_permi(vbll, vbll, 3);
 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
 
 res_vd = vec_xxsldwi(vd, vd, 0);
 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 
 res_vf = vec_xxsldwi(vf, vf, 1);

clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1  -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
 // RUN:   -target-feature +power8-vector -triple powerpc64le-unknown-unknown \
 // RUN:   -emit-llvm %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-P8
 #include <altivec.h>
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__VEC_ADDR_I:%.*]] = alloca <8 x i16>, align 16
 // CHECK-NEXT:    [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8

clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-vec-error.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -fsyntax-only \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-linux-gnu -fsyntax-only \
 // RUN:   -target-cpu pwr8 -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-linux-gnu -fsyntax-only \
 // RUN:   -target-cpu pwr8 -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-aix -fsyntax-only \
 // RUN:   -target-cpu pwr8 -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-aix -fsyntax-only \
 // RUN:   -target-cpu pwr8 -Wall -Werror -verify %s
 
 #include <altivec.h>
 vector unsigned char test_ldrmb(char *ptr) {
   return __vec_ldrmb(ptr, 17); // expected-error {{argument value 17 is outside the valid range [1, 16]}}
 }
 
 void test_strmb(char *ptr, vector unsigned char data) {

clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c

 // REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64-unknown-linux-gnu -emit-llvm %s -o - \
 // RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr7 | FileCheck %s
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
 // RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
 // RUN:   -U__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck \
 // RUN:   --check-prefix=NOCOMPAT %s
 #include <altivec.h>
 vector double vd = { 3.4e22, 1.8e-3 };
-vector signed long long vsll = { -12345678999ll, 12345678999 };
-vector unsigned long long vull = { 11547229456923630743llu, 18014402265226391llu };
+vector signed long long res_vsll, vsll = { -12345678999ll, 12345678999 };
+vector unsigned long long res_vull, vull = { 11547229456923630743llu, 18014402265226391llu };
 vector float res_vf;
 vector double res_vd;
 vector signed int res_vsi;
 vector unsigned int res_vui;
 
 void test() {
 // CHECK-LABEL: @test(
 // CHECK-NEXT:  entry:
 // CHECK-LE-LABEL: @test(
 // CHECK-LE-NEXT:  entry:
 
-  res_vf = vec_ctf(vsll, 4);
+  res_vd = vec_ctf(vsll, 4);
 // CHECK:         [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]])
 // CHECK-NEXT:    fmul <4 x float> [[TMP1]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
 
-  res_vf = vec_ctf(vull, 4);
+  res_vd = vec_ctf(vull, 4);
 // CHECK:         [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
 // CHECK-NEXT:    [[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]])
 // CHECK-NEXT:    fmul <4 x float> [[TMP3]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
 
-  res_vsi = vec_cts(vd, 4);
+  res_vsll = vec_cts(vd, 4);
 // CHECK:         [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:    fmul <2 x double> [[TMP4]], <double 1.600000e+01, double 1.600000e+01>
 // CHECK:         call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
 
-  res_vui = vec_ctu(vd, 4);
+  res_vull = vec_ctu(vd, 4);
 // CHECK:         [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:    fmul <2 x double> [[TMP8]], <double 1.600000e+01, double 1.600000e+01>
 // CHECK:         call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
 
   res_vd = vec_round(vd);
 // CHECK:         call double @llvm.ppc.readflm()
 // CHECK:         call double @llvm.ppc.setrnd(i32 0)
 // CHECK:         call <2 x double> @llvm.rint.v2f64(<2 x double>
 // CHECK:         call double @llvm.ppc.setflm(double
 // NOCOMPAT:      call <2 x double> @llvm.round.v2f64(<2 x double>
 }

clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp

-// RUN: %clang_cc1 -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:            -o - | FileCheck %s
 
 #include <altivec.h>
 
 // CHECK-LABEL: @_Z5test1Dv8_tS_
 // CHECK: @llvm.ppc.altivec.vcmpequh.p
 bool test1(vector unsigned short v1, vector unsigned short v2) {
   return v1 == v2;

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
   // P10 Vector Insert with immediate.
-  def int_ppc_altivec_vinsw :
+  def int_ppc_altivec_vinsw : GCCBuiltin<"__builtin_altivec_vinsw">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<2>>]>;
-  def int_ppc_altivec_vinsd :
+  def int_ppc_altivec_vinsd : GCCBuiltin<"__builtin_altivec_vinsd">,
               Intrinsic<[llvm_v2i64_ty],
                         [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+
   // P10 Vector Extract.
   def int_ppc_altivec_vextdubvlx : GCCBuiltin<"__builtin_altivec_vextdubvlx">,
               Intrinsic<[llvm_v2i64_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vextdubvrx : GCCBuiltin<"__builtin_altivec_vextdubvrx">,
               Intrinsic<[llvm_v2i64_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],