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Differential D131622

[NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c
ClosedPublic

Authored by lei on Aug 10 2022, 2:48 PM.

Details

Reviewers
nemanjai
amyk
power-llvm-team
Commits
rG7d8ae9f755d7: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c
Summary

Followup patch to address request from https://reviews.llvm.org/D124093

Diff Detail

Event Timeline

lei created this revision.Aug 10 2022, 2:48 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2022, 2:48 PM
Herald added a subscriber: shchenz. · View Herald Transcript
lei requested review of this revision.Aug 10 2022, 2:48 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2022, 2:48 PM
Harbormaster completed remote builds in B180528: Diff 451640.Aug 10 2022, 4:38 PM
amyk accepted this revision.Aug 15 2022, 1:55 PM

I think this LGTM.

This revision is now accepted and ready to land.Aug 15 2022, 1:55 PM
Closed by commit rG7d8ae9f755d7: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c (authored by lei). · Explain WhyAug 16 2022, 11:56 AM
This revision was automatically updated to reflect the committed changes.
lei added a commit: rG7d8ae9f755d7: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c.

Revision Contents

PathSize
clang/
test/
CodeGen/
PowerPC/
15 lines

Diff 453086

clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c

Show All 15 Lines
vector float res_vf; vector float res_vf;
vector double res_vd; vector double res_vd;
vector signed int res_vsi; vector signed int res_vsi;
vector unsigned int res_vui; vector unsigned int res_vui;
void test() { void test() {
// CHECK-LABEL: @test( // CHECK-LABEL: @test(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-LE-LABEL: @test( // NOCOMPAT-LABEL: @test(
// CHECK-LE-NEXT: entry: // NOCOMPAT-NEXT: entry:
res_vf = vec_ctf(vsll, 4); res_vf = vec_ctf(vsll, 4);
// CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16 // CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]])
// CHECK-NEXT: fmul <4 x float> [[TMP1]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02> // CHECK-NEXT: fmul <4 x float> [[TMP1]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
// NOCOMPAT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], <double 6.250000e-02, double 6.250000e-02>
res_vf = vec_ctf(vull, 4); res_vf = vec_ctf(vull, 4);
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16 // CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]])
// CHECK-NEXT: fmul <4 x float> [[TMP3]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02> // CHECK-NEXT: fmul <4 x float> [[TMP3]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
// NOCOMPAT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], <double 6.250000e-02, double 6.250000e-02>
res_vsll = vec_cts(vd, 4); res_vsll = vec_cts(vd, 4);
// CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16 // CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double 1.600000e+01> // CHECK-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double 1.600000e+01>
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
// NOCOMPAT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double 1.600000e+01>
res_vull = vec_ctu(vd, 4); res_vull = vec_ctu(vd, 4);
// CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16 // CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT: fmul <2 x double> [[TMP8]], <double 1.600000e+01, double 1.600000e+01> // CHECK-NEXT: fmul <2 x double> [[TMP8]], <double 1.600000e+01, double 1.600000e+01>
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> // NOCOMPAT: [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], <double 1.600000e+01, double 1.600000e+01>
res_vd = vec_round(vd); res_vd = vec_round(vd);
// CHECK: call double @llvm.ppc.readflm() // CHECK: call double @llvm.ppc.readflm()
// CHECK: call double @llvm.ppc.setrnd(i32 0) // CHECK: call double @llvm.ppc.setrnd(i32 0)
// CHECK: call <2 x double> @llvm.rint.v2f64(<2 x double> // CHECK: call <2 x double> @llvm.rint.v2f64(<2 x double>
// CHECK: call double @llvm.ppc.setflm(double // CHECK: call double @llvm.ppc.setflm(double
// NOCOMPAT: call <2 x double> @llvm.round.v2f64(<2 x double> // NOCOMPAT: call <2 x double> @llvm.round.v2f64(<2 x double>
} }