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Differential D123362

[RISCV][test] Precommit test for D122791.
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Authored by jacquesguan on Apr 7 2022, 11:50 PM.

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RKSimon
craig.topper
frasercrmck
benshi001
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rG3fcaea176cbf: [RISCV][test] Precommit test for D122791.

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jacquesguan created this revision.Apr 7 2022, 11:50 PM
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jacquesguan requested review of this revision.Apr 7 2022, 11:50 PM
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jacquesguan added a child revision: D122791: [DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat..Apr 7 2022, 11:51 PM
Harbormaster completed remote builds in B158629: Diff 421424.Apr 8 2022, 12:38 AM
RKSimon added inline comments.May 1 2022, 8:32 AM
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
1355

you can probably remove the cfi noise by changing these to:

define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
4

Extra attributes or better to have extra RUN lines with/without +m?

jacquesguan updated this revision to Diff 442822.Jul 7 2022, 2:11 AM

Address comment.

Herald added a subscriber: shiva0217. · View Herald TranscriptJul 7 2022, 2:11 AM
jacquesguan marked 2 inline comments as done.Jul 7 2022, 2:12 AM
jacquesguan added inline comments.
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
1355

Done, thanks.

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
4

Done, thanks.

Harbormaster completed remote builds in B174087: Diff 442822.Jul 7 2022, 2:56 AM
RKSimon accepted this revision.Jul 9 2022, 5:00 AM

LGTM

This revision is now accepted and ready to land.Jul 9 2022, 5:00 AM
This revision was landed with ongoing or failed builds.Jul 18 2022, 8:09 PM
Closed by commit rG3fcaea176cbf: [RISCV][test] Precommit test for D122791. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan marked 2 inline comments as done.
jacquesguan added a commit: rG3fcaea176cbf: [RISCV][test] Precommit test for D122791..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
30 lines
29 lines
33 lines
30 lines
29 lines
29 lines

Diff 445682

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll

Show First 20 Lines • Show All 854 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: vadd.vi v8, v8, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 2, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 2, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = add <vscale x 8 x i64> %va, %splat %vc = add <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
; RV32-LABEL: vadd_xx_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vadd_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vadd.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = add <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}

llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

Show First 20 Lines • Show All 1,346 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = and <vscale x 8 x i64> %va, %splat %vc = and <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
RKSimonUnsubmitted
Done
ReplyInline Actions

you can probably remove the cfi noise by changing these to:

define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
RKSimon: you can probably remove the cfi noise by changing these to: ``` define <vscale x 8 x i64>…
jacquesguanAuthorUnsubmitted
Done
ReplyInline Actions

Done, thanks.

jacquesguan: Done, thanks.
; RV32-LABEL: vand_xx_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vand_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = and <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
RKSimonUnsubmitted
Done
ReplyInline Actions

Extra attributes or better to have extra RUN lines with/without +m?

RKSimon: Extra attributes or better to have extra RUN lines with/without +m?
jacquesguanAuthorUnsubmitted
Done
ReplyInline Actions

Done, thanks.

jacquesguan: Done, thanks.
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmul_vv_nxv1i8: ; CHECK-LABEL: vmul_vv_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = mul <vscale x 1 x i8> %va, %vb %vc = mul <vscale x 1 x i8> %va, %vb
ret <vscale x 1 x i8> %vc ret <vscale x 1 x i8> %vc
▲ Show 20 Lines • Show All 901 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vsll.vi v8, v8, 4 ; CHECK-NEXT: vsll.vi v8, v8, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = mul <vscale x 8 x i64> %va, %splat %vc = mul <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
; RV32-LABEL: vmul_xx_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vmul_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = mul <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}

llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

Show First 20 Lines • Show All 1,138 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vmv.v.i v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 -1, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 -1, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i64> %va, %splat %vc = or <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
; RV32-LABEL: vor_xx_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vor_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vor.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = or <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

Show First 20 Lines • Show All 833 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: vsub.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = sub <vscale x 8 x i64> %va, %splat %vc = sub <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
; RV32-LABEL: vsub_xx_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vsub_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vsub.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = sub <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

Show First 20 Lines • Show All 1,346 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: vxor.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = xor <vscale x 8 x i64> %va, %splat %vc = xor <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vxor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
; RV32-LABEL: vxor_xx_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vxor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vxor_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vxor.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = xor <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}