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Differential D123217

[RISCV] Select unmasked integer setcc insts via ISel post-process
ClosedPublic

Authored by frasercrmck on Apr 6 2022, 6:40 AM.

Details

Reviewers
craig.topper
rogfer01
arcbbb
Commits
rG8ebc9b156065: [RISCV] Select unmasked integer setcc insts via ISel post-process
Summary

This patch has no effect on the generated code, whilst mitigating the
increase in ISel table size caused by the recent addition of masked
patterns.

I aim to do the same for floating-point patterns once D123051 lands,
giving us a reason to use masked floating-point patterns.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
3 lines
43 lines

Diff 421126

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 1,763 Lines • ▼ Show 20 Linesmulticlass VPseudoBinaryM<VReg RetClass,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
let ForceTailAgnostic = true in let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>; Op2Class, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
} }
} }
multiclass VPseudoBinaryEmul<VReg RetClass, multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo lmul, LMULInfo lmul,
LMULInfo emul, LMULInfo emul,
▲ Show 20 Lines • Show All 3,733 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 447 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
(fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
CondCode cc> { CondCode cc> {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
vti.RegClass:$rs2, cc, vti.RegClass:$rs2, cc,
(vti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
vti.RegClass:$rs2, cc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
(vti.Mask (IMPLICIT_DEF)), (vti.Mask (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs1,
vti.RegClass:$rs2, vti.RegClass:$rs2,
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. // Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> : CondCode cc, CondCode invcc> :
VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
vti.RegClass:$rs1, invcc, vti.RegClass:$rs1, invcc,
(vti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
vti.RegClass:$rs1, invcc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
(vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> { CondCode cc, CondCode invcc> {
defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX);
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat (XLenVT GPR:$rs2)), cc, (SplatPat (XLenVT GPR:$rs2)), cc,
(vti.Mask true_mask),
VLOpFrag)),
(instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat (XLenVT GPR:$rs2)), cc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),
(vti.Vector vti.RegClass:$rs1), invcc, (vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask true_mask),
VLOpFrag)),
(instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),
(vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> { CondCode cc, CondCode invcc> {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5 simm5:$rs2), cc, (SplatPat_simm5 simm5:$rs2), cc,
(vti.Mask true_mask),
VLOpFrag)),
(instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5 simm5:$rs2), cc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
XLenVT:$rs2, (vti.Mask V0), GPR:$vl, XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc, (vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask true_mask),
VLOpFrag)),
(instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
simm5:$rs2, (vti.Mask V0), GPR:$vl, simm5:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
} }
multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name,
CondCode cc, ComplexPattern splatpat_kind> { CondCode cc, ComplexPattern splatpat_kind> {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc, (splatpat_kind simm5:$rs2), cc,
(vti.Mask true_mask),
VLOpFrag)),
(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
} }
multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc,
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