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Differential D123207

[WIP][X86][AVX2] More broadcasts from constant pool
AbandonedPublic

Authored by lebedev.ri on Apr 6 2022, 4:59 AM.

Details

Reviewers
RKSimon
Summary

We weren't creating i8/i16 broadcasts from constant pool, even though we can.
This shows a number of new load folding failures, and i'm not really sure what to do about them.
Do we want this in the first place?

Diff Detail

Unit TestsFailed

TimeTest
60,100 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics::vloxseg_mask.c
60,070 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics::vlsegff_mask.c
60,080 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics::vluxseg_mask_mf.c
60,070 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-overloaded::vloxseg_mask_mf.c
60,180 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-overloaded::vluxseg_mask_mf.c
View Full Test Results (10 Failed)

Event Timeline

lebedev.ri created this revision.Apr 6 2022, 4:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2022, 4:59 AM
Herald added subscribers: pengfei, hiraditya. · View Herald Transcript
lebedev.ri requested review of this revision.Apr 6 2022, 4:59 AM
Harbormaster completed remote builds in B158179: Diff 420795.Apr 6 2022, 5:47 AM
RKSimon added inline comments.Apr 6 2022, 6:32 AM
llvm/test/CodeGen/X86/avx512-arith.ll
327

Pull out the AVX512 support for i64 broadcasts first? That should be well defined, is a more likely win, and should help reduce this massive patch.....

lebedev.ri abandoned this revision.Apr 12 2022, 12:38 PM

Large Diff

This large diff affects 181 files. Files without inline comments have been collapsed. Expand All Files

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Diff 420795

llvm/lib/Target/X86/X86ISelLowering.cpp

llvm/test/CodeGen/X86/avg.ll

llvm/test/CodeGen/X86/avx2-arith.ll

llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll

llvm/test/CodeGen/X86/avx2-shift.ll

llvm/test/CodeGen/X86/avx2-vbroadcast.ll

llvm/test/CodeGen/X86/avx2-vector-shifts.ll

llvm/test/CodeGen/X86/avx512-any_extend_load.ll

llvm/test/CodeGen/X86/avx512-arith.ll

Context not available.
define <2 x i64> @imulq128_bcast(<2 x i64> %x) { define <2 x i64> @imulq128_bcast(<2 x i64> %x) {
; AVX512F-LABEL: imulq128_bcast: ; AVX512F-LABEL: imulq128_bcast:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [8086,8086] ; AVX512F-NEXT: vpbroadcastq {{.*#+}} xmm1 = [8086,8086]
; AVX512F-NEXT: vpmuludq %xmm1, %xmm0, %xmm2 ; AVX512F-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0 ; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512F-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ; AVX512F-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpsllq $32, %xmm0, %xmm0 ; AVX512F-NEXT: vpsllq $32, %xmm0, %xmm0
Context not available.
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: imulq128_bcast: ; AVX512VL-LABEL: imulq128_bcast:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [8086,8086] ; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [8086,8086]
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2 ; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0
Context not available.
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: imulq128_bcast: ; AVX512BW-LABEL: imulq128_bcast:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [8086,8086] ; AVX512BW-NEXT: vpbroadcastq {{.*#+}} xmm1 = [8086,8086]
; AVX512BW-NEXT: vpmuludq %xmm1, %xmm0, %xmm2 ; AVX512BW-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; AVX512BW-NEXT: vpsrlq $32, %xmm0, %xmm0 ; AVX512BW-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512BW-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ; AVX512BW-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpsllq $32, %xmm0, %xmm0 ; AVX512BW-NEXT: vpsllq $32, %xmm0, %xmm0
Context not available.
; ;
; AVX512DQ-LABEL: imulq128_bcast: ; AVX512DQ-LABEL: imulq128_bcast:
; AVX512DQ: # %bb.0: ; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512DQ-NEXT: vmovdqa {{.*#+}} xmm1 = [8086,8086] ; AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Pull out the AVX512 support for i64 broadcasts first? That should be well defined, is a more likely win, and should help reduce this massive patch.....

RKSimon: Pull out the AVX512 support for i64 broadcasts first? That should be well defined, is a more…
; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; SKX-LABEL: imulq128_bcast: ; SKX-LABEL: imulq128_bcast:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
%z = mul <2 x i64> %x, <i64 8086, i64 8086> %z = mul <2 x i64> %x, <i64 8086, i64 8086>
ret <2 x i64>%z ret <2 x i64>%z
} }
Context not available.

llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll

llvm/test/CodeGen/X86/avx512-ext.ll

llvm/test/CodeGen/X86/avx512-trunc.ll

llvm/test/CodeGen/X86/avx512-vec-cmp.ll

llvm/test/CodeGen/X86/avx512fp16-arith.ll

llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll

llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll

llvm/test/CodeGen/X86/avx512vl-logic.ll

llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll

llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll

llvm/test/CodeGen/X86/bitcast-setcc-128.ll

llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll

llvm/test/CodeGen/X86/combine-abs.ll

llvm/test/CodeGen/X86/combine-add-ssat.ll

llvm/test/CodeGen/X86/combine-add-usat.ll

llvm/test/CodeGen/X86/combine-movmsk.ll

llvm/test/CodeGen/X86/combine-mul.ll

llvm/test/CodeGen/X86/combine-pavg.ll

llvm/test/CodeGen/X86/combine-shl.ll

llvm/test/CodeGen/X86/combine-smax.ll

llvm/test/CodeGen/X86/combine-smin.ll

llvm/test/CodeGen/X86/combine-udiv.ll

llvm/test/CodeGen/X86/concat-cast.ll

llvm/test/CodeGen/X86/dpbusd_const.ll

llvm/test/CodeGen/X86/dpbusd_i4.ll

llvm/test/CodeGen/X86/exedepsfix-broadcast.ll

llvm/test/CodeGen/X86/extractelement-fp.ll

llvm/test/CodeGen/X86/fma-fneg-combine.ll

llvm/test/CodeGen/X86/fma_patterns.ll

llvm/test/CodeGen/X86/fp-intrinsics-fma.ll

llvm/test/CodeGen/X86/fp-round.ll

llvm/test/CodeGen/X86/fp128-cast.ll

llvm/test/CodeGen/X86/gfni-funnel-shifts.ll

llvm/test/CodeGen/X86/gfni-rotates.ll

llvm/test/CodeGen/X86/gfni-shifts.ll

llvm/test/CodeGen/X86/horizontal-reduce-smax.ll

llvm/test/CodeGen/X86/horizontal-reduce-smin.ll

llvm/test/CodeGen/X86/horizontal-reduce-umax.ll

llvm/test/CodeGen/X86/horizontal-reduce-umin.ll

llvm/test/CodeGen/X86/i64-to-float.ll

llvm/test/CodeGen/X86/known-signbits-vector.ll

llvm/test/CodeGen/X86/machine-combiner-int-vec.ll

llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll

llvm/test/CodeGen/X86/masked_store_trunc_usat.ll

llvm/test/CodeGen/X86/memset-nonzero.ll

llvm/test/CodeGen/X86/midpoint-int-vec-128.ll

llvm/test/CodeGen/X86/midpoint-int-vec-256.ll

llvm/test/CodeGen/X86/midpoint-int-vec-512.ll

llvm/test/CodeGen/X86/min-legal-vector-width.ll

llvm/test/CodeGen/X86/movmsk-cmp.ll

llvm/test/CodeGen/X86/paddus.ll

llvm/test/CodeGen/X86/pmul.ll

llvm/test/CodeGen/X86/pmulh.ll

llvm/test/CodeGen/X86/pr34605.ll

llvm/test/CodeGen/X86/pr37499.ll

llvm/test/CodeGen/X86/pr43509.ll

llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll

llvm/test/CodeGen/X86/prefer-avx256-mulo.ll

llvm/test/CodeGen/X86/prefer-avx256-popcnt.ll

llvm/test/CodeGen/X86/prefer-avx256-shift.ll

llvm/test/CodeGen/X86/prefer-avx256-trunc.ll

llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll

llvm/test/CodeGen/X86/psubus.ll

llvm/test/CodeGen/X86/rotate-extract-vector.ll

llvm/test/CodeGen/X86/sadd_sat_vec.ll

llvm/test/CodeGen/X86/sat-add.ll

llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll

llvm/test/CodeGen/X86/slow-pmulld.ll

llvm/test/CodeGen/X86/sqrt-fastmath.ll

llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/X86/srem-vector-lkk.ll

llvm/test/CodeGen/X86/ssub_sat_vec.ll

llvm/test/CodeGen/X86/uadd_sat_vec.ll

llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll

llvm/test/CodeGen/X86/urem-vector-lkk.ll

llvm/test/CodeGen/X86/usub_sat_vec.ll

llvm/test/CodeGen/X86/var-permute-128.ll

llvm/test/CodeGen/X86/var-permute-256.ll

llvm/test/CodeGen/X86/vec-copysign-avx512.ll

llvm/test/CodeGen/X86/vec-strict-inttofp-128-fp16.ll

llvm/test/CodeGen/X86/vec-strict-inttofp-256-fp16.ll

llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

llvm/test/CodeGen/X86/vec-strict-inttofp-512-fp16.ll

llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll

llvm/test/CodeGen/X86/vec_cmp_uint-128.ll

llvm/test/CodeGen/X86/vec_fabs.ll

llvm/test/CodeGen/X86/vec_fp_to_int.ll

llvm/test/CodeGen/X86/vec_int_to_fp.ll

llvm/test/CodeGen/X86/vec_minmax_uint.ll

llvm/test/CodeGen/X86/vec_smulo.ll

llvm/test/CodeGen/X86/vec_uaddo.ll

llvm/test/CodeGen/X86/vec_umulo.ll

llvm/test/CodeGen/X86/vec_usubo.ll

llvm/test/CodeGen/X86/vector-bitreverse.ll

llvm/test/CodeGen/X86/vector-compare-all_of.ll

llvm/test/CodeGen/X86/vector-compare-any_of.ll

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

llvm/test/CodeGen/X86/vector-ext-logic.ll

llvm/test/CodeGen/X86/vector-fshl-128.ll

llvm/test/CodeGen/X86/vector-fshl-256.ll

llvm/test/CodeGen/X86/vector-fshl-512.ll

llvm/test/CodeGen/X86/vector-fshl-rot-128.ll

llvm/test/CodeGen/X86/vector-fshl-rot-256.ll

llvm/test/CodeGen/X86/vector-fshl-rot-512.ll

llvm/test/CodeGen/X86/vector-fshr-128.ll

llvm/test/CodeGen/X86/vector-fshr-256.ll

llvm/test/CodeGen/X86/vector-fshr-512.ll

llvm/test/CodeGen/X86/vector-fshr-rot-128.ll

llvm/test/CodeGen/X86/vector-fshr-rot-256.ll

llvm/test/CodeGen/X86/vector-fshr-rot-512.ll

llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll

llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll

llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll

llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll

llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll

llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll

llvm/test/CodeGen/X86/vector-lzcnt-128.ll

llvm/test/CodeGen/X86/vector-lzcnt-256.ll

llvm/test/CodeGen/X86/vector-lzcnt-512.ll

llvm/test/CodeGen/X86/vector-mul.ll

llvm/test/CodeGen/X86/vector-pack-128.ll

llvm/test/CodeGen/X86/vector-pack-256.ll

llvm/test/CodeGen/X86/vector-pack-512.ll

llvm/test/CodeGen/X86/vector-pcmp.ll

llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll

llvm/test/CodeGen/X86/vector-popcnt-128.ll

llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll

llvm/test/CodeGen/X86/vector-popcnt-256.ll

llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll

llvm/test/CodeGen/X86/vector-popcnt-512.ll

llvm/test/CodeGen/X86/vector-reduce-add-mask.ll

llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll

llvm/test/CodeGen/X86/vector-reduce-smax.ll

llvm/test/CodeGen/X86/vector-reduce-smin.ll

llvm/test/CodeGen/X86/vector-reduce-umax.ll

llvm/test/CodeGen/X86/vector-reduce-umin.ll

llvm/test/CodeGen/X86/vector-rotate-128.ll

llvm/test/CodeGen/X86/vector-rotate-256.ll

llvm/test/CodeGen/X86/vector-rotate-512.ll

llvm/test/CodeGen/X86/vector-shift-ashr-128.ll

llvm/test/CodeGen/X86/vector-shift-ashr-256.ll

llvm/test/CodeGen/X86/vector-shift-ashr-512.ll

llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll

llvm/test/CodeGen/X86/vector-shift-lshr-128.ll

llvm/test/CodeGen/X86/vector-shift-lshr-256.ll

llvm/test/CodeGen/X86/vector-shift-lshr-512.ll

llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll

llvm/test/CodeGen/X86/vector-shift-shl-128.ll

llvm/test/CodeGen/X86/vector-shift-shl-256.ll

llvm/test/CodeGen/X86/vector-shift-shl-512.ll

llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll

llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll

llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll

llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll

llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll

llvm/test/CodeGen/X86/vector-trunc-packus.ll

llvm/test/CodeGen/X86/vector-trunc-ssat.ll

llvm/test/CodeGen/X86/vector-trunc-usat.ll

llvm/test/CodeGen/X86/vector-trunc.ll

llvm/test/CodeGen/X86/vector-tzcnt-128.ll

llvm/test/CodeGen/X86/vector-tzcnt-256.ll

llvm/test/CodeGen/X86/vector-tzcnt-512.ll

llvm/test/CodeGen/X86/vector-unsigned-cmp.ll

llvm/test/CodeGen/X86/vector-zext.ll

llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll

llvm/test/CodeGen/X86/vselect-avx.ll

llvm/test/CodeGen/X86/vselect-minmax.ll

llvm/test/CodeGen/X86/vselect-pcmp.ll

llvm/test/CodeGen/X86/vselect.ll

llvm/test/CodeGen/X86/x86-interleaved-access.ll