[X86] Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y))

[RKSimon]

Summary

As noticed on PR39174, if we're extracting a single non-constant bit, then try to use BT+SETCC instead to avoid messing around moving the shift amount to the ECX register, using slow x86 shift ops etc.

[pengfei]

As noticed on PR39174, if we're extracting a single non-constant bit, then try to use BT+SETCC instead to avoid messing around moving the shift amount to the ECX register, using slow x86 shift ops etc.

Why using ECX register is a slow shift?

[RKSimon]

In D122891#3422324, @pengfei wrote:

As noticed on PR39174, if we're extracting a single non-constant bit, then try to use BT+SETCC instead to avoid messing around moving the shift amount to the ECX register, using slow x86 shift ops etc.

Why using ECX register is a slow shift?

Just that we have to move the shift amount to ECX for the shift ops, which can have side effects on register pressure/allocation.

[pengfei]

In D122891#3422384, @RKSimon wrote:

In D122891#3422324, @pengfei wrote:

As noticed on PR39174, if we're extracting a single non-constant bit, then try to use BT+SETCC instead to avoid messing around moving the shift amount to the ECX register, using slow x86 shift ops etc.

Why using ECX register is a slow shift?

Just that we have to move the shift amount to ECX for the shift ops, which can have side effects on register pressure/allocation.

LGTM. I thought that, but the word slow made me think if there's any other issue I don't know :)

[RKSimon]

Thanks @pengfei

[lebedev.ri]

What about the case where we want to have the inverse of the bit, https://godbolt.org/z/sEjq9n9Kn
I would presume we can consume any such not by inverting the predicate (b<->nb).

[RKSimon]

In D122891#3424712, @lebedev.ri wrote:

What about the case where we want to have the inverse of the bit, https://godbolt.org/z/sEjq9n9Kn
I would presume we can consume any such not by inverting the predicate (b<->nb).

np - we already do something like that in some of the other X86ISD::BT lowering cases - I'll take a look next week

llvm/lib/Target/X86/X86ISelLowering.cpp

if (SDValue R = combineAndNotIntoANDNP(N, DAG))
     return R;
 
   if (SDValue ShiftRight = combineAndMaskToShift(N, DAG, Subtarget))
     return ShiftRight;
 
   if (SDValue R = combineAndLoadToBZHI(N, DAG, Subtarget))
     return R;
 
+  // Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y), COND_B) iff Y is not a constant
+  // avoids slow variable shift (moving shift amount to ECX etc.)
+  if (isOneConstant(N1) && N0->hasOneUse()) {
+    SDValue Src = N0;
+    while ((Src.getOpcode() == ISD::ZERO_EXTEND ||
+            Src.getOpcode() == ISD::TRUNCATE) &&
+           Src.getOperand(0)->hasOneUse())
+      Src = Src.getOperand(0);
+    if (Src.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(Src.getOperand(1)))
+      if (SDValue BT = getBT(Src.getOperand(0), Src.getOperand(1), dl, DAG))
+        return getSETCC(X86::COND_B, BT, dl, DAG);
+  }
+
   if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
     // Attempt to recursively combine a bitmask AND with shuffles.
     SDValue Op(N, 0);
     if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
       return Res;
 
     // If either operand is a constant mask, then only the elements that aren't
     // zero are actually demanded by the other operand.

llvm/test/CodeGen/X86/setcc.ll

; X64-NEXT:    retq
   %.not = xor i1 %trunc, 1
   ret i1 %.not
 }
 
 ; PR39174
 define zeroext i1 @t7(i32 %0) {
 ; X86-LABEL: t7:
 ; X86:       ## %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movb $19, %al
-; X86-NEXT:    shrb %cl, %al
-; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl $19, %ecx
+; X86-NEXT:    btl %eax, %ecx
+; X86-NEXT:    setb %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t7:
 ; X64:       ## %bb.0:
-; X64-NEXT:    movl %edi, %ecx
-; X64-NEXT:    movb $19, %al
-; X64-NEXT:    ## kill: def $cl killed $cl killed $ecx
-; X64-NEXT:    shrb %cl, %al
-; X64-NEXT:    andb $1, %al
+; X64-NEXT:    movl $19, %eax
+; X64-NEXT:    btl %edi, %eax
+; X64-NEXT:    setb %al
 ; X64-NEXT:    retq
   %2 = trunc i32 %0 to i5
   %3 = lshr i5 -13, %2
   %4 = and i5 %3, 1
   %5 = icmp ne i5 %4, 0
   ret i1 %5
 }
 
 define zeroext i1 @t8(i8 %0, i8 %1) {
 ; X86-LABEL: t8:
 ; X86:       ## %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    shrb %cl, %al
-; X86-NEXT:    andb $1, %al
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    btl %eax, %ecx
+; X86-NEXT:    setb %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t8:
 ; X64:       ## %bb.0:
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    ## kill: def $cl killed $cl killed $ecx
-; X64-NEXT:    shrb %cl, %al
-; X64-NEXT:    andb $1, %al
-; X64-NEXT:    ## kill: def $al killed $al killed $eax
+; X64-NEXT:    btl %esi, %edi
+; X64-NEXT:    setb %al
 ; X64-NEXT:    retq
   %3 = lshr i8 %0, %1
   %4 = and i8 %3, 1
   %5 = icmp ne i8 %4, 0
   ret i1 %5
 }
 
 define i16 @shift_and(i16 %a) {