This is an archive of the discontinued LLVM Phabricator instance.

Differential D122868

[PowerPC] Adjust `MaxAtomicSizeInBitsSupported` on PPC64
ClosedPublic

Authored by lkail on Mar 31 2022, 11:01 PM.

Details

Reviewers
jsji
brad
nemanjai
efriedma
hubert.reinterpretcast
Group Reviewers
Restricted Project
Commits
rG18679ac0d7ec: [PowerPC] Adjust `MaxAtomicSizeInBitsSupported` on PPC64
Summary

AtomicExpandPass uses this variable to determine emitting libcalls or not. The default value is 1024 and if we don't specify it for PPC64 explicitly, AtomicExpandPass won't emit __atomic_* libcalls for those target unable to inline atomic ops and finally the backend emits __sync_* libcalls. Thanks @efriedma for pointing it out.

Diff Detail

Unit TestsFailed

TimeTest
60,130 msx64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp
60,030 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,060 msx64 debian > libFuzzer.libFuzzer::large.test
60,030 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test
60,030 msx64 debian > libFuzzer.libFuzzer::out-of-process-fuzz.test
View Full Test Results (6 Failed)

Event Timeline

lkail created this revision.Mar 31 2022, 11:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 31 2022, 11:01 PM
Herald added subscribers: shchenz, kbarton, hiraditya. · View Herald Transcript
lkail requested review of this revision.Mar 31 2022, 11:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 31 2022, 11:01 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
lkail added a parent revision: D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up.Mar 31 2022, 11:01 PM
lkail added a reviewer: efriedma.Mar 31 2022, 11:09 PM
Harbormaster completed remote builds in B157315: Diff 419624.Mar 31 2022, 11:50 PM
efriedma accepted this revision.Apr 1 2022, 12:10 PM

LGTM

This revision is now accepted and ready to land.Apr 1 2022, 12:10 PM
lkail mentioned this in D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up.Apr 6 2022, 9:12 PM
lkail added a reviewer: hubert.reinterpretcast.Apr 6 2022, 9:17 PM
lkail updated this revision to Diff 421413.Apr 7 2022, 9:39 PM

Rebased.

Harbormaster completed remote builds in B158622: Diff 421413.Apr 7 2022, 10:40 PM
lkail removed a parent revision: D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up.Apr 8 2022, 4:41 PM
This revision was landed with ongoing or failed builds.Apr 8 2022, 5:03 PM
Closed by commit rG18679ac0d7ec: [PowerPC] Adjust `MaxAtomicSizeInBitsSupported` on PPC64 (authored by lkail). · Explain Why
This revision was automatically updated to reflect the committed changes.
lkail added a commit: rG18679ac0d7ec: [PowerPC] Adjust `MaxAtomicSizeInBitsSupported` on PPC64.
lkail mentioned this in D122472: [PowerPC][Atomics] Fix lowering of llvm.ppc.cfence on i128 when `-ppc-quadword-atomics` is off.Apr 9 2022, 1:37 AM

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
5 lines
test/
CodeGen/
PowerPC/
262 lines
Transforms/
AtomicExpand/
PowerPC/
20 lines

Diff 419624

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,316 Lines • ▼ Show 20 Lines
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
if (!isPPC64) { if (!isPPC64) {
setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
} }
if (shouldInlineQuadwordAtomics()) { if (shouldInlineQuadwordAtomics()) {
setMaxAtomicSizeInBitsSupported(128);
setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom); setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom); setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom);
} }
setBooleanContents(ZeroOrOneBooleanContent); setBooleanContents(ZeroOrOneBooleanContent);
if (Subtarget.hasAltivec()) { if (Subtarget.hasAltivec()) {
// Altivec instructions set fields to all zeros or all ones. // Altivec instructions set fields to all zeros or all ones.
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
} }
setLibcallName(RTLIB::MULO_I128, nullptr); setLibcallName(RTLIB::MULO_I128, nullptr);
if (!isPPC64) { if (!isPPC64) {
// These libcalls are not available in 32-bit. // These libcalls are not available in 32-bit.
setLibcallName(RTLIB::SHL_I128, nullptr); setLibcallName(RTLIB::SHL_I128, nullptr);
setLibcallName(RTLIB::SRL_I128, nullptr); setLibcallName(RTLIB::SRL_I128, nullptr);
setLibcallName(RTLIB::SRA_I128, nullptr); setLibcallName(RTLIB::SRA_I128, nullptr);
setLibcallName(RTLIB::MUL_I128, nullptr); setLibcallName(RTLIB::MUL_I128, nullptr);
setLibcallName(RTLIB::MULO_I64, nullptr); setLibcallName(RTLIB::MULO_I64, nullptr);
} }
if (!isPPC64) if (!isPPC64)
setMaxAtomicSizeInBitsSupported(32); setMaxAtomicSizeInBitsSupported(32);
else if (shouldInlineQuadwordAtomics())
setMaxAtomicSizeInBitsSupported(128);
else
setMaxAtomicSizeInBitsSupported(64);
setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
// We have target-specific dag combine patterns for the following nodes: // We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, ISD::MUL, setTargetDAGCombine({ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, ISD::MUL,
ISD::FMA, ISD::SINT_TO_FP, ISD::BUILD_VECTOR}); ISD::FMA, ISD::SINT_TO_FP, ISD::BUILD_VECTOR});
if (Subtarget.hasFPCVT()) if (Subtarget.hasFPCVT())
setTargetDAGCombine(ISD::UINT_TO_FP); setTargetDAGCombine(ISD::UINT_TO_FP);
▲ Show 20 Lines • Show All 16,770 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/atomics-i128.ll

Show All 37 Lines
; ;
; PWR7-LABEL: swap: ; PWR7-LABEL: swap:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_lock_test_and_set_16 ; PWR7-NEXT: bl __atomic_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: swap: ; LE-PWR8-LABEL: swap:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: swap: ; AIX64-PWR8-LABEL: swap:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_lock_test_and_set_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: swap: ; AIX32-PWR8-LABEL: swap:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; ;
; PWR7-LABEL: add: ; PWR7-LABEL: add:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_fetch_and_add_16 ; PWR7-NEXT: bl __atomic_fetch_add_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: add: ; LE-PWR8-LABEL: add:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: add: ; AIX64-PWR8-LABEL: add:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_fetch_and_add_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_add_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: add: ; AIX32-PWR8-LABEL: add:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; ;
; PWR7-LABEL: sub: ; PWR7-LABEL: sub:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_fetch_and_sub_16 ; PWR7-NEXT: bl __atomic_fetch_sub_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: sub: ; LE-PWR8-LABEL: sub:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: sub: ; AIX64-PWR8-LABEL: sub:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_fetch_and_sub_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_sub_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: sub: ; AIX32-PWR8-LABEL: sub:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; ;
; PWR7-LABEL: and: ; PWR7-LABEL: and:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_fetch_and_and_16 ; PWR7-NEXT: bl __atomic_fetch_and_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: and: ; LE-PWR8-LABEL: and:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: and: ; AIX64-PWR8-LABEL: and:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_fetch_and_and_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_and_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: and: ; AIX32-PWR8-LABEL: and:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; ;
; PWR7-LABEL: or: ; PWR7-LABEL: or:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_fetch_and_or_16 ; PWR7-NEXT: bl __atomic_fetch_or_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: or: ; LE-PWR8-LABEL: or:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: or: ; AIX64-PWR8-LABEL: or:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_fetch_and_or_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_or_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: or: ; AIX32-PWR8-LABEL: or:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; ;
; PWR7-LABEL: xor: ; PWR7-LABEL: xor:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_fetch_and_xor_16 ; PWR7-NEXT: bl __atomic_fetch_xor_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: xor: ; LE-PWR8-LABEL: xor:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: xor: ; AIX64-PWR8-LABEL: xor:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_fetch_and_xor_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_xor_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: xor: ; AIX32-PWR8-LABEL: xor:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; ;
; PWR7-LABEL: nand: ; PWR7-LABEL: nand:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __sync_fetch_and_nand_16 ; PWR7-NEXT: bl __atomic_fetch_nand_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: nand: ; LE-PWR8-LABEL: nand:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
Show All 10 Lines
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: nand: ; AIX64-PWR8-LABEL: nand:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__sync_fetch_and_nand_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_nand_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: nand: ; AIX32-PWR8-LABEL: nand:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_weak_acquire_acquire: ; PWR7-LABEL: cas_weak_acquire_acquire:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: bl __sync_val_compare_and_swap_16 ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 2
; PWR7-NEXT: li r8, 2
; PWR7-NEXT: bl __atomic_compare_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync ; PWR7-NEXT: ld r4, 120(r1)
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: ld r3, 112(r1)
; PWR7-NEXT: addi r1, r1, 128
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: cas_weak_acquire_acquire: ; LE-PWR8-LABEL: cas_weak_acquire_acquire:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: .LBB7_1: # %entry ; LE-PWR8-NEXT: .LBB7_1: # %entry
; LE-PWR8-NEXT: # ; LE-PWR8-NEXT: #
Show All 16 Lines
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_weak_acquire_acquire: ; AIX64-PWR8-LABEL: cas_weak_acquire_acquire:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: bl .__sync_val_compare_and_swap_16[PR] ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 2
; AIX64-PWR8-NEXT: li r8, 2
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: cas_weak_acquire_acquire: ; AIX32-PWR8-LABEL: cas_weak_acquire_acquire:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
; AIX32-PWR8-NEXT: stw r0, 4(r1) ; AIX32-PWR8-NEXT: stw r0, 4(r1)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_weak_release_monotonic: ; PWR7-LABEL: cas_weak_release_monotonic:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: lwsync ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: bl __sync_val_compare_and_swap_16 ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 3
; PWR7-NEXT: li r8, 0
; PWR7-NEXT: bl __atomic_compare_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: ld r4, 120(r1)
; PWR7-NEXT: ld r3, 112(r1)
; PWR7-NEXT: addi r1, r1, 128
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: cas_weak_release_monotonic: ; LE-PWR8-LABEL: cas_weak_release_monotonic:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: .LBB8_1: # %entry ; LE-PWR8-NEXT: .LBB8_1: # %entry
Show All 16 Lines
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_weak_release_monotonic: ; AIX64-PWR8-LABEL: cas_weak_release_monotonic:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: lwsync ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: bl .__sync_val_compare_and_swap_16[PR] ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 3
; AIX64-PWR8-NEXT: li r8, 0
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: cas_weak_release_monotonic: ; AIX32-PWR8-LABEL: cas_weak_release_monotonic:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
; AIX32-PWR8-NEXT: stw r0, 4(r1) ; AIX32-PWR8-NEXT: stw r0, 4(r1)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_sc_sc: ; PWR7-LABEL: cas_sc_sc:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sync ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: bl __sync_val_compare_and_swap_16 ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 5
; PWR7-NEXT: li r8, 5
; PWR7-NEXT: bl __atomic_compare_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync ; PWR7-NEXT: ld r4, 120(r1)
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: ld r3, 112(r1)
; PWR7-NEXT: addi r1, r1, 128
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: cas_sc_sc: ; LE-PWR8-LABEL: cas_sc_sc:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
; LE-PWR8-NEXT: .LBB9_1: # %entry ; LE-PWR8-NEXT: .LBB9_1: # %entry
Show All 17 Lines
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_sc_sc: ; AIX64-PWR8-LABEL: cas_sc_sc:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: sync ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: bl .__sync_val_compare_and_swap_16[PR] ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 5
; AIX64-PWR8-NEXT: li r8, 5
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: cas_sc_sc: ; AIX32-PWR8-LABEL: cas_sc_sc:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
; AIX32-PWR8-NEXT: stw r0, 4(r1) ; AIX32-PWR8-NEXT: stw r0, 4(r1)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_acqrel_acquire: ; PWR7-LABEL: cas_acqrel_acquire:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: lwsync ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: bl __sync_val_compare_and_swap_16 ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 4
; PWR7-NEXT: li r8, 2
; PWR7-NEXT: bl __atomic_compare_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: lwsync ; PWR7-NEXT: ld r4, 120(r1)
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: ld r3, 112(r1)
; PWR7-NEXT: addi r1, r1, 128
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: cas_acqrel_acquire: ; LE-PWR8-LABEL: cas_acqrel_acquire:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: .LBB10_1: # %entry ; LE-PWR8-NEXT: .LBB10_1: # %entry
Show All 17 Lines
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_acqrel_acquire: ; AIX64-PWR8-LABEL: cas_acqrel_acquire:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: lwsync ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: bl .__sync_val_compare_and_swap_16[PR] ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 4
; AIX64-PWR8-NEXT: li r8, 2
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: lwsync ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: cas_acqrel_acquire: ; AIX32-PWR8-LABEL: cas_acqrel_acquire:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
; AIX32-PWR8-NEXT: stw r0, 4(r1) ; AIX32-PWR8-NEXT: stw r0, 4(r1)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_acqrel_acquire_check_succ: ; PWR7-LABEL: cas_acqrel_acquire_check_succ:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1) ; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -144(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 144 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: .cfi_offset r29, -24 ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: .cfi_offset r30, -16 ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: std r29, 120(r1) # 8-byte Folded Spill ; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r30, r5 ; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: mr r29, r4 ; PWR7-NEXT: li r7, 4
; PWR7-NEXT: lwsync ; PWR7-NEXT: li r8, 2
; PWR7-NEXT: bl __sync_val_compare_and_swap_16 ; PWR7-NEXT: bl __atomic_compare_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: xor r3, r3, r29 ; PWR7-NEXT: addi r1, r1, 128
; PWR7-NEXT: xor r4, r4, r30
; PWR7-NEXT: lwsync
; PWR7-NEXT: or r3, r4, r3
; PWR7-NEXT: ld r30, 128(r1) # 8-byte Folded Reload
; PWR7-NEXT: ld r29, 120(r1) # 8-byte Folded Reload
; PWR7-NEXT: cntlzd r3, r3
; PWR7-NEXT: rldicl r3, r3, 58, 63
; PWR7-NEXT: addi r1, r1, 144
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: cas_acqrel_acquire_check_succ: ; LE-PWR8-LABEL: cas_acqrel_acquire_check_succ:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: .LBB11_1: # %entry ; LE-PWR8-NEXT: .LBB11_1: # %entry
Show All 21 Lines
; LE-PWR8-NEXT: rldicl r3, r3, 58, 63 ; LE-PWR8-NEXT: rldicl r3, r3, 58, 63
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_acqrel_acquire_check_succ: ; AIX64-PWR8-LABEL: cas_acqrel_acquire_check_succ:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1) ; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -128(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r31, 120(r1) # 8-byte Folded Spill ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: mr r31, r5 ; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r30, r4 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: lwsync ; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: bl .__sync_val_compare_and_swap_16[PR] ; AIX64-PWR8-NEXT: li r7, 4
; AIX64-PWR8-NEXT: li r8, 2
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: xor r3, r3, r30
; AIX64-PWR8-NEXT: xor r4, r4, r31
; AIX64-PWR8-NEXT: lwsync
; AIX64-PWR8-NEXT: or r3, r4, r3
; AIX64-PWR8-NEXT: ld r31, 120(r1) # 8-byte Folded Reload
; AIX64-PWR8-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
; AIX64-PWR8-NEXT: cntlzd r3, r3
; AIX64-PWR8-NEXT: rldicl r3, r3, 58, 63
; AIX64-PWR8-NEXT: addi r1, r1, 128 ; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; AIX32-PWR8-LABEL: cas_acqrel_acquire_check_succ: ; AIX32-PWR8-LABEL: cas_acqrel_acquire_check_succ:
; AIX32-PWR8: # %bb.0: # %entry ; AIX32-PWR8: # %bb.0: # %entry
; AIX32-PWR8-NEXT: mflr r0 ; AIX32-PWR8-NEXT: mflr r0
Show All 30 Lines

llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll

Show All 28 Lines
; CHECK-NEXT: [[TMP6:%.*]] = and i128 [[VAL64]], -1 ; CHECK-NEXT: [[TMP6:%.*]] = and i128 [[VAL64]], -1
; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i128 [[CMPVAL_SHIFTED]], [[TMP6]] ; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i128 [[CMPVAL_SHIFTED]], [[TMP6]]
; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i128, i1 } [[TMP5]], i1 [[SUCCESS]], 1 ; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i128, i1 } [[TMP5]], i1 [[SUCCESS]], 1
; CHECK-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP7]], 1 ; CHECK-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP7]], 1
; CHECK-NEXT: ret i1 [[SUCC]] ; CHECK-NEXT: ret i1 [[SUCC]]
; ;
; PWR7-LABEL: @test_cmpxchg_seq_cst( ; PWR7-LABEL: @test_cmpxchg_seq_cst(
; PWR7-NEXT: entry: ; PWR7-NEXT: entry:
; PWR7-NEXT: call void @llvm.ppc.sync() ; PWR7-NEXT: [[TMP0:%.*]] = bitcast i128* [[ADDR:%.*]] to i8*
; PWR7-NEXT: [[PAIR:%.*]] = cmpxchg weak i128* [[ADDR:%.*]], i128 [[DESIRE:%.*]], i128 [[NEW:%.*]] monotonic monotonic, align 16 ; PWR7-NEXT: [[TMP1:%.*]] = alloca i128, align 8
; PWR7-NEXT: call void @llvm.ppc.lwsync() ; PWR7-NEXT: [[TMP2:%.*]] = bitcast i128* [[TMP1]] to i8*
; PWR7-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[PAIR]], 1 ; PWR7-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP2]])
; PWR7-NEXT: store i128 [[DESIRE:%.*]], i128* [[TMP1]], align 8
; PWR7-NEXT: [[TMP3:%.*]] = alloca i128, align 8
; PWR7-NEXT: [[TMP4:%.*]] = bitcast i128* [[TMP3]] to i8*
; PWR7-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP4]])
; PWR7-NEXT: store i128 [[NEW:%.*]], i128* [[TMP3]], align 8
; PWR7-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP0]], i8* [[TMP2]], i8* [[TMP4]], i32 5, i32 5)
; PWR7-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP4]])
; PWR7-NEXT: [[TMP6:%.*]] = load i128, i128* [[TMP1]], align 8
; PWR7-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP2]])
; PWR7-NEXT: [[TMP7:%.*]] = insertvalue { i128, i1 } undef, i128 [[TMP6]], 0
; PWR7-NEXT: [[TMP8:%.*]] = insertvalue { i128, i1 } [[TMP7]], i1 [[TMP5]], 1
; PWR7-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP8]], 1
; PWR7-NEXT: ret i1 [[SUCC]] ; PWR7-NEXT: ret i1 [[SUCC]]
; ;
entry: entry:
%pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst %pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst
%succ = extractvalue {i128, i1} %pair, 1 %succ = extractvalue {i128, i1} %pair, 1
ret i1 %succ ret i1 %succ
} }