[AMDGPU] Only count global-to-global as indirect accesses

[foad]

Summary

Previously any load (global, local or constant) feeding into a
global load or store would be counted as an indirect access. This
patch only counts global loads feeding into a global load or store.
The rationale is that the latency for global loads is generally
much larger than the other kinds.

As a side effect this makes it easier to write small kernels test
cases that are not counted as having indirect accesses, despite
the fact that arguments to the kernel are accessed with an SMEM
load.

[foad]

I'm really not sure what the "indirect access" heuristic was intended for, but at least this "fixes" test_indirect_through_phi and makes it possible to write a simple test case for D83676.

[arsenm]

LGTM. I still think this pass needs to be moved to a machine analysis

[uabelho]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

156

I think this was the last use of the isConstantAddr method. gcc now warns with

23:46:06 ../lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp:339:6: warning: 'bool {anonymous}::AMDGPUPerfHint::isConstantAddr(const llvm::Value*) const' defined but not used [-Wunused-function]
23:46:06   339 | bool AMDGPUPerfHint::isConstantAddr(const Value *V) const {
23:46:06       |      ^~~~~~~~~~~~~~

Should the unused isConstantAddr method be removed?

[foad]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

156

Sorry about that, but I am hoping to land D83676 soon (it was approved once, just waiting for confirmation that it's still OK) which will start using isConstantAddr again.

[uabelho]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

156

Ok, good to know. Thanks!

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

while (!WorkSet.empty()) {
     const Value *V = *WorkSet.begin();
     WorkSet.erase(*WorkSet.begin());
     if (!Visited.insert(V).second)
       continue;
     LLVM_DEBUG(dbgs() << "  check: " << *V << '\n');
 
     if (auto LD = dyn_cast<LoadInst>(V)) {
       auto M = LD->getPointerOperand();
-      if (isGlobalAddr(M) || isLocalAddr(M) || isConstantAddr(M)) {
+      if (isGlobalAddr(M)) {
         LLVM_DEBUG(dbgs() << "    is IA\n");
         return true;
       }
       continue;
     }
 
     if (auto GEP = dyn_cast<GetElementPtrInst>(V)) {
       auto P = GEP->getPointerOperand();

llvm/test/CodeGen/AMDGPU/perfhint.ll

bb:
   %tmp17 = extractelement <4 x i32> %tmp4, i32 3
   %tmp18 = sext i32 %tmp17 to i64
   %tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
   %tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
   store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
   ret void
 }
 
-; FIXME: This test was intended to be WaveLimiterHint : 0
 ; GCN-LABEL: {{^}}test_indirect_through_phi:
 ; GCN: MemoryBound: 0
-; GCN: WaveLimiterHint : 1
+; GCN: WaveLimiterHint : 0
 define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
 bb:
   %load = load float, float addrspace(1)* %arg, align 8
   %load.f = bitcast float %load to i32
   %n = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb

llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll

 ; RUN: llc -march=amdgcn -mcpu=tahiti -enable-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
 ; RUN: llc -march=amdgcn -mcpu=tahiti -enable-amdgpu-aa=0 -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MAXOCC %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -misched=gcn-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -misched=gcn-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
 
 ; SI-MINREG: NumSgprs: {{[1-9]$}}
 ; SI-MINREG: NumVgprs: {{[1-9]$}}
 
-; SI-MAXOCC: NumSgprs: {{[0-4][0-9]$}}
-; SI-MAXOCC: NumVgprs: {{[0-4][0-9]$}}
+; SI-MAXOCC: NumSgprs: {{[1-4]?[0-9]$}}
+; SI-MAXOCC: NumVgprs: {{[1-4]?[0-9]$}}
 
 ; stores may alias loads
 ; VI: NumSgprs: {{[0-9]$}}
 ; VI: NumVgprs: {{[1-3][0-9]$}}
 
 define amdgpu_kernel void @load_fma_store(float addrspace(3)* nocapture readonly %in_arg, float addrspace(1)* nocapture %out_arg) {
 bb:
   %adr.a.0 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 20004