Revert "[AMDGPU] Only count global-to-global as indirect accesses"

[david-salinas]

Summary

This reverts commit c246b7bd4a5191d48f68ce12b50e03bfadd2a0b5.

[david-salinas]

Reverting this change because it causes a performance degradtion in kernels with Local addr space.

[kzhuravl]

Adding Jay

[david-salinas]

patch to re-add isConstantAddr

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

#endif
   /// y = a[i+1000];
   /// z = a[i+2000];
   /// In the above example, the second and third memory access will be marked
   /// large stride memory access.
   bool isLargeStride(const Instruction *Inst);
 
   bool isGlobalAddr(const Value *V) const;
   bool isLocalAddr(const Value *V) const;
+  bool isConstantAddr(const Value *V) const;
   bool isGlobalLoadUsedInBB(const Instruction &) const;
 };
 
 static std::pair<const Value *, const Type *> getMemoryInstrPtrAndType(
     const Instruction *Inst) {
   if (auto LI = dyn_cast<LoadInst>(Inst))
     return {LI->getPointerOperand(), LI->getType()};
   if (auto SI = dyn_cast<StoreInst>(Inst))
while (!WorkSet.empty()) {
     const Value *V = *WorkSet.begin();
     WorkSet.erase(*WorkSet.begin());
     if (!Visited.insert(V).second)
       continue;
     LLVM_DEBUG(dbgs() << "  check: " << *V << '\n');
 
     if (auto LD = dyn_cast<LoadInst>(V)) {
       auto M = LD->getPointerOperand();
-      if (isGlobalAddr(M)) {
+      if (isGlobalAddr(M) || isLocalAddr(M) || isConstantAddr(M)) {
         LLVM_DEBUG(dbgs() << "    is IA\n");
         return true;
       }
       continue;
     }
 
     if (auto GEP = dyn_cast<GetElementPtrInst>(V)) {
       auto P = GEP->getPointerOperand();

 }
 
 bool AMDGPUPerfHint::isLocalAddr(const Value *V) const {
   if (auto PT = dyn_cast<PointerType>(V->getType()))
     return PT->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
   return false;
 }
 
+bool AMDGPUPerfHint::isConstantAddr(const Value *V) const {
+  if (auto PT = dyn_cast<PointerType>(V->getType())) {
+    unsigned As = PT->getAddressSpace();
+    return As == AMDGPUAS::CONSTANT_ADDRESS ||
+           As == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
+  }
+  return false;
+}
+
 bool AMDGPUPerfHint::isLargeStride(const Instruction *Inst) {
   LLVM_DEBUG(dbgs() << "[isLargeStride] " << *Inst << '\n');
 
   MemAccessInfo MAI = makeMemAccessInfo(const_cast<Instruction *>(Inst));
   bool IsLargeStride = MAI.isLargeStride(LastAccess);
   if (MAI.Base)
     LastAccess = std::move(MAI);
 

llvm/test/CodeGen/AMDGPU/perfhint.ll

bb:
   %tmp17 = extractelement <4 x i32> %tmp4, i32 3
   %tmp18 = sext i32 %tmp17 to i64
   %tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
   %tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
   store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
   ret void
 }
 
+; FIXME: This test was intended to be WaveLimiterHint : 0
 ; GCN-LABEL: {{^}}test_indirect_through_phi:
 ; GCN: MemoryBound: 0
-; GCN: WaveLimiterHint : 0
+; GCN: WaveLimiterHint : 1
 define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
 bb:
   %load = load float, float addrspace(1)* %arg, align 8
   %load.f = bitcast float %load to i32
   %n = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb

llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll

 ; RUN: llc -march=amdgcn -mcpu=tahiti -enable-amdgpu-aa=0 -misched=gcn-iterative-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MINREG %s
 ; RUN: llc -march=amdgcn -mcpu=tahiti -enable-amdgpu-aa=0 -misched=gcn-iterative-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck --check-prefix=SI-MAXOCC %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -misched=gcn-iterative-minreg -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -misched=gcn-iterative-max-occupancy-experimental -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
 
 ; SI-MINREG: NumSgprs: {{[1-9]$}}
 ; SI-MINREG: NumVgprs: {{[1-9]$}}
 
-; SI-MAXOCC: NumSgprs: {{[1-4]?[0-9]$}}
-; SI-MAXOCC: NumVgprs: {{[1-4]?[0-9]$}}
+; SI-MAXOCC: NumSgprs: {{[0-4][0-9]$}}
+; SI-MAXOCC: NumVgprs: {{[0-4][0-9]$}}
 
 ; stores may alias loads
 ; VI: NumSgprs: {{[0-9]$}}
 ; VI: NumVgprs: {{[1-3][0-9]$}}
 
 define amdgpu_kernel void @load_fma_store(float addrspace(3)* nocapture readonly %in_arg, float addrspace(1)* nocapture %out_arg) {
 bb:
   %adr.a.0 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 20004