[DAG] Allow XOR(X,MIN_SIGNED_VALUE) to perform AddLike folds

[RKSimon]

Summary

As raised on PR52267, XOR(X,MIN_SIGNED_VALUE) can be treated as ADD(X,MIN_SIGNED_VALUE), so let these cases use the 'AddLike' folds, similar to how we perform no-common-bits OR(X,Y) cases.

define i8 @src(i8 %x) {
%0:
  %r = xor i8 %x, 128
  ret i8 %r
}
=>
define i8 @tgt(i8 %x) {
%0:
  %r = add i8 %x, 128
  ret i8 %r
}
Transformation seems to be correct!

https://alive2.llvm.org/ce/z/qV46E2

[craig.topper]

What about (add (xor X, MIN_SIGNED), C). Should we check for the XOR inside of visitAddLike for constant folding? I believe we check for ISD::OR with no common bits in there. I'm fine if you want to do it as a separate patch.

[RKSimon]

Add isAddLike() helper to match addlike(addlike(x,y),z) patterns

[RKSimon]

llvm/test/CodeGen/X86/movmsk-cmp.ll

4548 ↗

(On Diff #419398)

Looks like we're missing this fold, but I haven't had time to investigate yet:

----------------------------------------
define i1 @src(i8 %a) {
%0:
  %x = xor i8 %a, 1
  %r = icmp eq i8 %x, 2
  ret i1 %r
}
=>
define i1 @tgt(i8 %a) {
%0:
  %r = icmp eq i8 %a, 3
  ret i1 %r
}
Transformation seems to be correct!

[RKSimon]

rebase

[RKSimon]

rebase

[RKSimon]

rebase - regressions are now fixed

[lebedev.ri]

Seems fine to me.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitXOR(SDNode *N) {
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 
   // reassociate xor
   if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags()))
     return RXOR;
 
+  // look for AddLike folds:
+  // XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE)
+  if (auto *N1C = dyn_cast<ConstantSDNode>(N1))
+    if (N1C->isMinSignedValue())
+      if (SDValue Combined = visitADDLike(N))
+        return Combined;
+
   // fold !(x cc y) -> (x !cc y)
   unsigned N0Opcode = N0.getOpcode();
   SDValue LHS, RHS, CC;
   if (TLI.isConstTrueVal(N1) &&
       isSetCCEquivalent(N0, LHS, RHS, CC, /*MatchStrict*/ true)) {
     ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
                                                LHS.getValueType());
     if (!LegalOperations ||

llvm/test/CodeGen/X86/xor-lea.ll

; X64-NEXT:    retq
   %s = add i8 %x, %y
   %r = xor i8 %s, 128
   ret i8 %r
 }
 
 define i16 @xor_sub_sminval_i16(i16 %x) {
 ; X86-LABEL: xor_sub_sminval_i16:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    addl $-2, %eax
-; X86-NEXT:    xorl $32768, %eax # imm = 0x8000
+; X86-NEXT:    movl $32766, %eax # imm = 0x7FFE
+; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: xor_sub_sminval_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    leal -2(%rdi), %eax
-; X64-NEXT:    xorl $32768, %eax # imm = 0x8000
+; X64-NEXT:    leal 32766(%rdi), %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %s = sub i16 %x, 2
   %r = xor i16 %s, 32768
   ret i16 %r
 }
 
 define i32 @xor_add_sminval_i32(i32 %x) {
 ; X86-LABEL: xor_add_sminval_i32:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl $512, %eax # imm = 0x200
+; X86-NEXT:    movl $-2147483136, %eax # imm = 0x80000200
 ; X86-NEXT:    addl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    xorl $-2147483648, %eax # imm = 0x80000000
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: xor_add_sminval_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    leal 512(%rdi), %eax
-; X64-NEXT:    xorl $-2147483648, %eax # imm = 0x80000000
+; X64-NEXT:    leal -2147483136(%rdi), %eax
 ; X64-NEXT:    retq
   %s = add i32 %x, 512
   %r = xor i32 %s, 2147483648
   ret i32 %r
 }
 
 define i64 @xor_add_sminval_i64(i64 %x, i64 %y) {
 ; X86-LABEL: xor_add_sminval_i64: