[DAG] SimplifySetCC - relax fold (X^C1) == C2 --> X == C1^C2

[RKSimon]

Summary

Remove limitation that wouldn't perform the fold if all the inverted bits are known zero

The thumb2 changes look to be benign, although it does show that the TEQ/TST isel patterns could probably be improved?

Fixes movmsk regression in D122754

I'm not sure who is actively reviewing MIPS codegen at the moment, and thats the one case which shows a notable improvement :-(

[RKSimon]

rebase

[dmgreen]

The Arm changes sound OK. The cmp might actually be better than a teq if it can be shrunk into a smaller instruction - it sounds like we might have some inefficiencies there.

LGTM. https://alive2.llvm.org/ce/z/A_auBq

[sdardis]

These MIPS changes look OK to me.

[RKSimon]

Thanks everyone - I'll commit this tomorrow

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
           // Turn (X+C1) == C2 --> X == C2-C1
           if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse())
             return DAG.getSetCC(
                 dl, VT, N0.getOperand(0),
                 DAG.getConstant(RHSC->getAPIntValue() - LHSR->getAPIntValue(),
                                 dl, N0.getValueType()),
                 Cond);
 
-          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
-          // If we know that all of the inverted bits are zero, don't bother
-          // performing the inversion.
-          if (N0.getOpcode() == ISD::XOR &&
-              DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
+          // Turn (X^C1) == C2 --> X == C1^C2
+          if (N0.getOpcode() == ISD::XOR && N0.getNode()->hasOneUse())
             return DAG.getSetCC(
                 dl, VT, N0.getOperand(0),
                 DAG.getConstant(LHSR->getAPIntValue() ^ RHSC->getAPIntValue(),
                                 dl, N0.getValueType()),
                 Cond);
         }
 
         // Turn (C1-X) == C2 --> X == C1-C2

llvm/test/CodeGen/Mips/countleading.ll

entry:
   ret i64 %tmp1
 }
 
 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 
 define i64 @ctlo_i64(i64 %X) nounwind readnone {
 ; MIPS32-R1-R2-LABEL: ctlo_i64:
 ; MIPS32-R1-R2:       # %bb.0: # %entry
-; MIPS32-R1-R2-NEXT:    addiu $1, $zero, -1
-; MIPS32-R1-R2-NEXT:    xor $1, $5, $1
+; MIPS32-R1-R2-NEXT:    not $1, $5
 ; MIPS32-R1-R2-NEXT:    clo $3, $5
 ; MIPS32-R1-R2-NEXT:    clo $2, $4
 ; MIPS32-R1-R2-NEXT:    addiu $2, $2, 32
 ; MIPS32-R1-R2-NEXT:    movn $2, $3, $1
 ; MIPS32-R1-R2-NEXT:    jr $ra
 ; MIPS32-R1-R2-NEXT:    addiu $3, $zero, 0
 ;
 ; MIPS32-R6-LABEL: ctlo_i64:
 ; MIPS32-R6:       # %bb.0: # %entry
-; MIPS32-R6-NEXT:    addiu $1, $zero, -1
-; MIPS32-R6-NEXT:    xor $1, $5, $1
-; MIPS32-R6-NEXT:    sltu $1, $zero, $1
-; MIPS32-R6-NEXT:    clo $2, $4
-; MIPS32-R6-NEXT:    addiu $2, $2, 32
-; MIPS32-R6-NEXT:    seleqz $2, $2, $1
-; MIPS32-R6-NEXT:    clo $3, $5
-; MIPS32-R6-NEXT:    selnez $1, $3, $1
-; MIPS32-R6-NEXT:    or $2, $1, $2
+; MIPS32-R6-NEXT:    not $1, $5
+; MIPS32-R6-NEXT:    clo $2, $5
+; MIPS32-R6-NEXT:    selnez $2, $2, $1
+; MIPS32-R6-NEXT:    clo $3, $4
+; MIPS32-R6-NEXT:    addiu $3, $3, 32
+; MIPS32-R6-NEXT:    seleqz $1, $3, $1
+; MIPS32-R6-NEXT:    or $2, $2, $1
 ; MIPS32-R6-NEXT:    jr $ra
 ; MIPS32-R6-NEXT:    addiu $3, $zero, 0
 ;
 ; MIPS64-GT-R1-LABEL: ctlo_i64:
 ; MIPS64-GT-R1:       # %bb.0: # %entry
 ; MIPS64-GT-R1-NEXT:    jr $ra
 ; MIPS64-GT-R1-NEXT:    dclo $2, $4
 ;

llvm/test/CodeGen/Thumb2/thumb2-teq.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 ; These tests would be improved by 'movs r0, #0' being rematerialized below the
 ; test as 'mov.w r0, #0'.
 
 ; 0x000000bb = 187
 define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #187
+; CHECK-NEXT:    cmp r0, #187
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 187
     %tmp1 = icmp eq i32 0, %tmp
     %ret = select i1 %tmp1, i32 42, i32 24
     ret i32 %ret
 }
 
 ; 0x00aa00aa = 11141290
 define i32 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #11141290
+; CHECK-NEXT:    cmp.w r0, #11141290
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 11141290
     %tmp1 = icmp eq i32 %tmp, 0
     %ret = select i1 %tmp1, i32 42, i32 24
     ret i32 %ret
 }
 
 ; 0xcc00cc00 = 3422604288
 define i32 @f6(i32 %a) {
 ; CHECK-LABEL: f6:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #-872363008
+; CHECK-NEXT:    cmp.w r0, #-872363008
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 3422604288
     %tmp1 = icmp eq i32 0, %tmp
     %ret = select i1 %tmp1, i32 42, i32 24
     ret i32 %ret
 }
 
 ; 0xdddddddd = 3722304989
 define i32 @f7(i32 %a) {
 ; CHECK-LABEL: f7:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #-572662307
+; CHECK-NEXT:    cmp.w r0, #-572662307
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 3722304989
     %tmp1 = icmp eq i32 %tmp, 0
     %ret = select i1 %tmp1, i32 42, i32 24
     ret i32 %ret
 }
 
 ; 0x00110000 = 1114112
 define i32 @f10(i32 %a) {
 ; CHECK-LABEL: f10:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    movs r1, #24
-; CHECK-NEXT:    teq.w r0, #1114112
+; CHECK-NEXT:    cmp.w r0, #1114112
 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    moveq r1, #42
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 1114112
     %tmp1 = icmp eq i32 0, %tmp
     %ret = select i1 %tmp1, i32 42, i32 24
     ret i32 %ret
 }
 
 ; 0x000000bb = 187
 define i1 @f12(i32 %a) {
 ; CHECK-LABEL: f12:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #187
+; CHECK-NEXT:    subs r0, #187
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 187
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
 
 ; 0x00aa00aa = 11141290
 define i1 @f13(i32 %a) {
 ; CHECK-LABEL: f13:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #11141290
+; CHECK-NEXT:    sub.w r0, r0, #11141290
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 11141290
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
 
 ; 0xcc00cc00 = 3422604288
 define i1 @f16(i32 %a) {
 ; CHECK-LABEL: f16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #-872363008
+; CHECK-NEXT:    sub.w r0, r0, #-872363008
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 3422604288
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
 
 ; 0xdddddddd = 3722304989
 define i1 @f17(i32 %a) {
 ; CHECK-LABEL: f17:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #-572662307
+; CHECK-NEXT:    sub.w r0, r0, #-572662307
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 3722304989
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
 
 ; 0x00110000 = 1114112
 define i1 @f18(i32 %a) {
 ; CHECK-LABEL: f18:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #1114112
+; CHECK-NEXT:    sub.w r0, r0, #1114112
 ; CHECK-NEXT:    clz r0, r0
 ; CHECK-NEXT:    lsrs r0, r0, #5
 ; CHECK-NEXT:    bx lr
     %tmp = xor i32 %a, 1114112
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
 

llvm/test/CodeGen/X86/peep-test-3.ll

 
 define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
 ; CHECK-LABEL: xor:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl %eax, %ecx
 ; CHECK-NEXT:    andl $3, %ecx
 ; CHECK-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    xorl $1, %ecx
+; CHECK-NEXT:    cmpl $1, %ecx
 ; CHECK-NEXT:    je .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %bb
 ; CHECK-NEXT:    movl $0, (%eax)
 ; CHECK-NEXT:  .LBB1_2: # %return
 ; CHECK-NEXT:    retl
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
   %1 = and i32 %0, 3                              ; <i32> [#uses=1]