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Differential D122723

[RISCV] [NFC] Add Immediate tests for the cmov instruction
ClosedPublic

Authored by Miss_Grape on Mar 30 2022, 4:52 AM.

Details

Reviewers
craig.topper
benshi001
Commits
rGa3d510220f7b: [RISCV] [NFC] Add Immediate tests for the cmov instruction

Diff Detail

Unit TestsFailed

TimeTest
310 msx64 debian > BOLT.X86::asm-dump.c
360 msx64 debian > BOLT.X86::exceptions-args.test
310 msx64 debian > BOLT.X86::inline-debug-info.test
70 msx64 debian > BOLT.X86::plt-sec-8-byte.test
60 msx64 debian > BOLT.X86::plt-sec.test
View Full Test Results (8 Failed)

Event Timeline

Miss_Grape created this revision.Mar 30 2022, 4:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2022, 4:52 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
Miss_Grape requested review of this revision.Mar 30 2022, 4:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2022, 4:52 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald Transcript
Miss_Grape added reviewers: craig.topper, benshi001.Mar 30 2022, 4:53 AM
Herald added a subscriber: StephenFan. · View Herald TranscriptMar 30 2022, 4:53 AM
Miss_Grape updated this revision to Diff 419116.Mar 30 2022, 5:27 AM
Miss_Grape updated this revision to Diff 419122.Mar 30 2022, 5:56 AM
Miss_Grape updated this revision to Diff 419123.Mar 30 2022, 6:01 AM
Miss_Grape retitled this revision from WIP [RISCV] [NFC] Add tests for cmov to [RISCV] [NFC] Add Immediate tests for the cmov instruction.
craig.topper added inline comments.Mar 30 2022, 9:30 AM
llvm/test/CodeGen/RISCV/i32-icmp.ll
211

Why are you changing unsigned constants to signed? Wasn't unsigned requested in the previous review?

Harbormaster completed remote builds in B156943: Diff 419123.Mar 30 2022, 5:06 PM
Miss_Grape updated this revision to Diff 419308.Mar 30 2022, 7:00 PM

Why are you changing unsigned constants to signed? Wasn't unsigned requested in the previous review?

Fixed

Miss_Grape updated this revision to Diff 419310.Mar 30 2022, 7:11 PM
Miss_Grape added a child revision: D122644: [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z).
Miss_Grape removed a child revision: D122644: [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z).
Harbormaster completed remote builds in B157084: Diff 419310.Mar 31 2022, 6:02 AM
Miss_Grape added a comment.Apr 5 2022, 7:02 PM

ping

craig.topper accepted this revision.Apr 5 2022, 7:23 PM

LGTM

This revision is now accepted and ready to land.Apr 5 2022, 7:23 PM
This revision was landed with ongoing or failed builds.Apr 5 2022, 8:09 PM
Closed by commit rGa3d510220f7b: [RISCV] [NFC] Add Immediate tests for the cmov instruction (authored by Miss_Grape, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGa3d510220f7b: [RISCV] [NFC] Add Immediate tests for the cmov instruction.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
24 lines
66 lines
542 lines
425 lines

Diff 419123

llvm/test/CodeGen/RISCV/i32-icmp.ll

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
} }
define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind { define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_ugt_constant_neg_2049: ; RV32I-LABEL: icmp_ugt_constant_neg_2049:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048 ; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp ugt i32 %a, -2049
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Why are you changing unsigned constants to signed? Wasn't unsigned requested in the previous review?

craig.topper: Why are you changing unsigned constants to signed? Wasn't unsigned requested in the previous…
%1 = icmp ugt i32 %a, 4294965247
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ugt_constant_neg_2050(i32 %a) nounwind { define i32 @icmp_ugt_constant_neg_2050(i32 %a) nounwind {
; RV32I-LABEL: icmp_ugt_constant_neg_2050: ; RV32I-LABEL: icmp_ugt_constant_neg_2050:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575 ; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2046 ; RV32I-NEXT: addi a1, a1, 2046
; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965246 signed extend is -2050 %1 = icmp ugt i32 %a, -2050
%1 = icmp ugt i32 %a, 4294965246
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_uge(i32 %a, i32 %b) nounwind { define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_uge: ; RV32I-LABEL: icmp_uge:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
Show All 37 Lines
} }
define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind { define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_neg_2048: ; RV32I-LABEL: icmp_uge_constant_neg_2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048 ; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965248 signed extend is -2048 %1 = icmp uge i32 %a, -2048
%1 = icmp uge i32 %a, 4294965248
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind { define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_uge_constant_neg_2049: ; RV32I-LABEL: icmp_uge_constant_neg_2049:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575 ; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2046 ; RV32I-NEXT: addi a1, a1, 2046
; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp uge i32 %a, -2049
%1 = icmp uge i32 %a, 4294965247
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ult(i32 %a, i32 %b) nounwind { define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ult: ; RV32I-LABEL: icmp_ult:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
Show All 34 Lines; RV32I-NEXT: ret
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind { define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_neg_2048: ; RV32I-LABEL: icmp_ult_constant_neg_2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048 ; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965248 signed extend is -2048 %1 = icmp ult i32 %a, -2048
%1 = icmp ult i32 %a, 4294965248
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind { define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_ult_constant_neg_2049: ; RV32I-LABEL: icmp_ult_constant_neg_2049:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575 ; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047 ; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp ult i32 %a, -2049
%1 = icmp ult i32 %a, 4294965247
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ule(i32 %a, i32 %b) nounwind { define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ule: ; RV32I-LABEL: icmp_ule:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: sltu a0, a1, a0
Show All 35 Lines; RV32I-NEXT: ret
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind { define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind {
; RV32I-LABEL: icmp_ule_constant_neg_2049: ; RV32I-LABEL: icmp_ule_constant_neg_2049:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, -2048 ; RV32I-NEXT: sltiu a0, a0, -2048
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp ule i32 %a, -2049
%1 = icmp ule i32 %a, 4294965247
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind { define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind {
; RV32I-LABEL: icmp_ule_constant_neg_2050: ; RV32I-LABEL: icmp_ule_constant_neg_2050:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1048575 ; RV32I-NEXT: lui a1, 1048575
; RV32I-NEXT: addi a1, a1, 2047 ; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; 4294965246 signed extend is -2050 %1 = icmp ule i32 %a, -2050
%1 = icmp ule i32 %a, 4294965246
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @icmp_sgt(i32 %a, i32 %b) nounwind { define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sgt: ; RV32I-LABEL: icmp_sgt:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0 ; RV32I-NEXT: slt a0, a1, a0
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/i64-icmp.ll

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%1 = icmp ugt i64 %a, 2046 %1 = icmp ugt i64 %a, 2046
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind { define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2049: ; RV64I-LABEL: icmp_ugt_constant_neg_2049:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527 ; RV64I-NEXT: sltiu a0, a0, -2048
; RV64I-NEXT: slli a1, a1, 20 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp ugt i64 %a, -2049
%1 = icmp ugt i64 %a, 4294965247
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind { define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2050: ; RV64I-LABEL: icmp_ugt_constant_neg_2050:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1025 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: slli a1, a1, 33 ; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0 ; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965246 signed extend is -2050 %1 = icmp ugt i64 %a, -2050
%1 = icmp ugt i64 %a, 4294965246
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_uge(i64 %a, i64 %b) nounwind { define i64 @icmp_uge(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_uge: ; RV64I-LABEL: icmp_uge:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1 ; RV64I-NEXT: sltu a0, a0, a1
Show All 34 Lines; RV64I-NEXT: ret
%1 = icmp uge i64 %a, 2048 %1 = icmp uge i64 %a, 2048
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind { define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2048: ; RV64I-LABEL: icmp_uge_constant_neg_2048:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527 ; RV64I-NEXT: sltiu a0, a0, -2048
; RV64I-NEXT: slli a1, a1, 20 ; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965248 signed extend is -2048 %1 = icmp uge i64 %a, -2048
%1 = icmp uge i64 %a, 4294965248
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind { define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2049: ; RV64I-LABEL: icmp_uge_constant_neg_2049:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1025 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: slli a1, a1, 33 ; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a1, a0 ; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp uge i64 %a, -2049
%1 = icmp uge i64 %a, 4294965247
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ult(i64 %a, i64 %b) nounwind { define i64 @icmp_ult(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ult: ; RV64I-LABEL: icmp_ult:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1 ; RV64I-NEXT: sltu a0, a0, a1
Show All 32 Lines; RV64I-NEXT: ret
%1 = icmp ult i64 %a, 2048 %1 = icmp ult i64 %a, 2048
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind { define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2048: ; RV64I-LABEL: icmp_ult_constant_neg_2048:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: sltiu a0, a0, -2048
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -2048
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965248 signed extend is -2048 %1 = icmp ult i64 %a, -2048
%1 = icmp ult i64 %a, 4294965248
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind { define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2049: ; RV64I-LABEL: icmp_ult_constant_neg_2049:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: slli a1, a1, 20 ; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a0, a1 ; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp ult i64 %a, -2049
%1 = icmp ult i64 %a, 4294965247
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ule(i64 %a, i64 %b) nounwind { define i64 @icmp_ule(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ule: ; RV64I-LABEL: icmp_ule:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a1, a0 ; RV64I-NEXT: sltu a0, a1, a0
Show All 33 Lines; RV64I-NEXT: ret
%1 = icmp ule i64 %a, 2047 %1 = icmp ule i64 %a, 2047
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind { define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2049: ; RV64I-LABEL: icmp_ule_constant_neg_2049:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1 ; RV64I-NEXT: sltiu a0, a0, -2048
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -2048
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965247 signed extend is -2049 %1 = icmp ule i64 %a, -2049
%1 = icmp ule i64 %a, 4294965247
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind { define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2050: ; RV64I-LABEL: icmp_ule_constant_neg_2050:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1046527 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: slli a1, a1, 20 ; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sltu a0, a0, a1 ; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; 4294965246 signed extend is -2050 %1 = icmp ule i64 %a, -2050
%1 = icmp ule i64 %a, 4294965246
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_sgt(i64 %a, i64 %b) nounwind { define i64 @icmp_sgt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sgt: ; RV64I-LABEL: icmp_sgt:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a1, a0 ; RV64I-NEXT: slt a0, a1, a0
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32zbt.ll

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; RV32ZBT-NEXT: cmix a1, a3, a1, a5 ; RV32ZBT-NEXT: cmix a1, a3, a1, a5
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%xor = xor i64 %a, %c %xor = xor i64 %a, %c
%and = and i64 %xor, %b %and = and i64 %xor, %b
%xor1 = xor i64 %and, %c %xor1 = xor i64 %and, %c
ret i64 %xor1 ret i64 %xor1
} }
define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind { define i32 @cmov_eq_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_i32: ; RV32I-LABEL: cmov_eq_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beqz a1, .LBB4_2 ; RV32I-NEXT: beq a1, a2, .LBB4_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_eq_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, %c
%cond = select i1 %tobool.not, i32 %a, i32 %d
ret i32 %cond
}
define i32 @cmov_eq_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_eq_i32_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: beqz a1, .LBB5_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_i32: ; RV32ZBT-LABEL: cmov_eq_i32_constant_zero:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmov a0, a1, a0, a2 ; RV32ZBT-NEXT: cmov a0, a1, a2, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 0 %tobool.not = icmp eq i32 %b, 0
%cond = select i1 %tobool.not, i32 %c, i32 %a %cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_eq_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_eq_i32_constant_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1
; RV32I-NEXT: addi a3, a3, -2048
; RV32I-NEXT: beq a1, a3, .LBB6_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_eq_i32_constant_2048:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: addi a1, a1, -2048
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 2048
%cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_eq_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_eq_i32_constant_neg_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, -2047
; RV32I-NEXT: beq a1, a3, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_eq_i32_constant_neg_2047:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: addi a1, a1, 2047
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, -2047
%cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ne_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ne_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: bne a1, a2, .LBB8_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ne_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a0, a3
; RV32ZBT-NEXT: ret
%tobool.not = icmp ne i32 %b, %c
%cond = select i1 %tobool.not, i32 %a, i32 %d
ret i32 %cond
}
define i32 @cmov_ne_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ne_i32_constant_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: bnez a1, .LBB9_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ne_i32_constant_zero:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool.not = icmp ne i32 %b, 0
%cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ne_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ne_i32_constant_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1
; RV32I-NEXT: addi a3, a3, -2048
; RV32I-NEXT: bne a1, a3, .LBB10_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ne_i32_constant_2048:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: addi a1, a1, -2048
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool.not = icmp ne i32 %b, 2048
%cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ne_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ne_i32_constant_neg_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, -2047
; RV32I-NEXT: bne a1, a3, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ne_i32_constant_neg_2047:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: addi a1, a1, 2047
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool.not = icmp ne i32 %b, -2047
%cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sle_i32: ; RV32I-LABEL: cmov_sle_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a2, a1, .LBB5_2 ; RV32I-NEXT: bge a2, a1, .LBB12_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB5_2: ; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sle_i32: ; RV32ZBT-LABEL: cmov_sle_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a2, a1 ; RV32ZBT-NEXT: slt a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sle_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_sle_i32_constant_2046:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, 2047
; RV32I-NEXT: blt a1, a3, .LBB13_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sle_i32_constant_2046:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slti a1, a1, 2047
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp sle i32 %b, 2046
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_sle_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_sle_i32_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, -2048
; RV32I-NEXT: blt a1, a3, .LBB14_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB14_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sle_i32_constant_neg_2049:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slti a1, a1, -2048
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp sle i32 %b, -2049
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_sgt_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sgt_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: blt a2, a1, .LBB15_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sgt_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a0, a3
; RV32ZBT-NEXT: ret
%tobool = icmp sgt i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond
}
define i32 @cmov_sgt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_sgt_i32_constant_2046:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, 2046
; RV32I-NEXT: blt a3, a1, .LBB16_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sgt_i32_constant_2046:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slti a1, a1, 2047
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp sgt i32 %b, 2046
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_sgt_i32_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1048575
; RV32I-NEXT: addi a3, a3, 2047
; RV32I-NEXT: blt a3, a1, .LBB17_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB17_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slti a1, a1, -2048
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp sgt i32 %b, -2049
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sge_i32: ; RV32I-LABEL: cmov_sge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a1, a2, .LBB6_2 ; RV32I-NEXT: bge a1, a2, .LBB18_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: .LBB18_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sge_i32: ; RV32ZBT-LABEL: cmov_sge_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a1, a2 ; RV32ZBT-NEXT: slt a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_sge_i32_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, 2046
; RV32I-NEXT: blt a3, a1, .LBB19_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slti a1, a1, 2047
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp sge i32 %b, 2047
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1048575
; RV32I-NEXT: addi a3, a3, 2047
; RV32I-NEXT: blt a3, a1, .LBB20_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB20_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slti a1, a1, -2048
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp sge i32 %b, -2048
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ule_i32: ; RV32I-LABEL: cmov_ule_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a2, a1, .LBB7_2 ; RV32I-NEXT: bgeu a2, a1, .LBB21_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB21_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_ule_i32: ; RV32ZBT-LABEL: cmov_ule_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a2, a1 ; RV32ZBT-NEXT: sltu a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_ule_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ule_i32_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a1, 11
; RV32I-NEXT: beqz a1, .LBB22_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB22_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ule_i32_constant_2047:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: srli a1, a1, 11
; RV32ZBT-NEXT: cmov a0, a1, a2, a0
; RV32ZBT-NEXT: ret
%tobool = icmp ule i32 %b, 2047
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ule_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ule_i32_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, -2048
; RV32I-NEXT: bltu a1, a3, .LBB23_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB23_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ule_i32_constant_neg_2049:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltiu a1, a1, -2048
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp ule i32 %b, -2049
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ugt_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ugt_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: bltu a2, a1, .LBB24_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB24_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ugt_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a2, a1
; RV32ZBT-NEXT: cmov a0, a1, a0, a3
; RV32ZBT-NEXT: ret
%tobool = icmp ugt i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond
}
define i32 @cmov_ugt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ugt_i32_constant_2046:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, 2046
; RV32I-NEXT: bltu a3, a1, .LBB25_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB25_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ugt_i32_constant_2046:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltiu a1, a1, 2047
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp ugt i32 %b, 2046
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_ugt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_ugt_i32_constant_neg_2049:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1048575
; RV32I-NEXT: addi a3, a3, 2047
; RV32I-NEXT: bltu a3, a1, .LBB26_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB26_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ugt_i32_constant_neg_2049:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltiu a1, a1, -2048
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp ugt i32 %b, -2049
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_uge_i32: ; RV32I-LABEL: cmov_uge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a1, a2, .LBB8_2 ; RV32I-NEXT: bgeu a1, a2, .LBB27_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: .LBB27_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_uge_i32: ; RV32ZBT-LABEL: cmov_uge_i32:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a1, a2 ; RV32ZBT-NEXT: sltu a1, a1, a2
; RV32ZBT-NEXT: cmov a0, a1, a3, a0 ; RV32ZBT-NEXT: cmov a0, a1, a3, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %a, i32 %d %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_uge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_uge_i32_constant_2047:
; RV32I: # %bb.0:
; RV32I-NEXT: li a3, 2046
; RV32I-NEXT: bltu a3, a1, .LBB28_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB28_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltiu a1, a1, 2047
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp uge i32 %b, 2047
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_uge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: cmov_uge_i32_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 1048575
; RV32I-NEXT: addi a3, a3, 2047
; RV32I-NEXT: bltu a3, a1, .LBB29_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB29_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltiu a1, a1, -2048
; RV32ZBT-NEXT: xori a1, a1, 1
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32ZBT-NEXT: ret
%tobool = icmp uge i32 %b, -2048
%cond = select i1 %tobool, i32 %a, i32 %c
ret i32 %cond
}
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov_i64: ; RV32I-LABEL: cmov_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: beqz a2, .LBB9_2 ; RV32I-NEXT: beqz a2, .LBB30_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: mv a5, a1 ; RV32I-NEXT: mv a5, a1
; RV32I-NEXT: .LBB9_2: ; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_i64: ; RV32ZBT-LABEL: cmov_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: or a2, a2, a3 ; RV32ZBT-NEXT: or a2, a2, a3
; RV32ZBT-NEXT: cmov a0, a2, a0, a4 ; RV32ZBT-NEXT: cmov a0, a2, a0, a4
; RV32ZBT-NEXT: cmov a1, a2, a1, a5 ; RV32ZBT-NEXT: cmov a1, a2, a1, a5
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 0 %tobool.not = icmp eq i64 %b, 0
%cond = select i1 %tobool.not, i64 %c, i64 %a %cond = select i1 %tobool.not, i64 %c, i64 %a
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sle_i64: ; RV32I-LABEL: cmov_sle_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB10_2 ; RV32I-NEXT: beq a3, a5, .LBB31_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a5, a3 ; RV32I-NEXT: slt a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB10_3 ; RV32I-NEXT: beqz a2, .LBB31_3
; RV32I-NEXT: j .LBB10_4 ; RV32I-NEXT: j .LBB31_4
; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: sltu a2, a4, a2 ; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB10_4 ; RV32I-NEXT: bnez a2, .LBB31_4
; RV32I-NEXT: .LBB10_3: ; RV32I-NEXT: .LBB31_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_4: ; RV32I-NEXT: .LBB31_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sle_i64: ; RV32ZBT-LABEL: cmov_sle_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a4, a2 ; RV32ZBT-NEXT: sltu a2, a4, a2
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: slt a3, a5, a3 ; RV32ZBT-NEXT: slt a3, a5, a3
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
; RV32ZBT-NEXT: cmov a0, a2, a0, a6 ; RV32ZBT-NEXT: cmov a0, a2, a0, a6
; RV32ZBT-NEXT: cmov a1, a2, a1, a7 ; RV32ZBT-NEXT: cmov a1, a2, a1, a7
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sge_i64: ; RV32I-LABEL: cmov_sge_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB11_2 ; RV32I-NEXT: beq a3, a5, .LBB32_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a3, a5 ; RV32I-NEXT: slt a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB11_3 ; RV32I-NEXT: beqz a2, .LBB32_3
; RV32I-NEXT: j .LBB11_4 ; RV32I-NEXT: j .LBB32_4
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB32_2:
; RV32I-NEXT: sltu a2, a2, a4 ; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB11_4 ; RV32I-NEXT: bnez a2, .LBB32_4
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB32_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB11_4: ; RV32I-NEXT: .LBB32_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_sge_i64: ; RV32ZBT-LABEL: cmov_sge_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a2, a4 ; RV32ZBT-NEXT: sltu a2, a2, a4
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: slt a3, a3, a5 ; RV32ZBT-NEXT: slt a3, a3, a5
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
; RV32ZBT-NEXT: cmov a0, a2, a0, a6 ; RV32ZBT-NEXT: cmov a0, a2, a0, a6
; RV32ZBT-NEXT: cmov a1, a2, a1, a7 ; RV32ZBT-NEXT: cmov a1, a2, a1, a7
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_ule_i64: ; RV32I-LABEL: cmov_ule_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB12_2 ; RV32I-NEXT: beq a3, a5, .LBB33_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a5, a3 ; RV32I-NEXT: sltu a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB12_3 ; RV32I-NEXT: beqz a2, .LBB33_3
; RV32I-NEXT: j .LBB12_4 ; RV32I-NEXT: j .LBB33_4
; RV32I-NEXT: .LBB12_2: ; RV32I-NEXT: .LBB33_2:
; RV32I-NEXT: sltu a2, a4, a2 ; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB12_4 ; RV32I-NEXT: bnez a2, .LBB33_4
; RV32I-NEXT: .LBB12_3: ; RV32I-NEXT: .LBB33_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB12_4: ; RV32I-NEXT: .LBB33_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_ule_i64: ; RV32ZBT-LABEL: cmov_ule_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a4, a2 ; RV32ZBT-NEXT: sltu a2, a4, a2
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: sltu a3, a5, a3 ; RV32ZBT-NEXT: sltu a3, a5, a3
; RV32ZBT-NEXT: xori a3, a3, 1 ; RV32ZBT-NEXT: xori a3, a3, 1
; RV32ZBT-NEXT: cmov a2, t0, a3, a2 ; RV32ZBT-NEXT: cmov a2, t0, a3, a2
; RV32ZBT-NEXT: cmov a0, a2, a0, a6 ; RV32ZBT-NEXT: cmov a0, a2, a0, a6
; RV32ZBT-NEXT: cmov a1, a2, a1, a7 ; RV32ZBT-NEXT: cmov a1, a2, a1, a7
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_uge_i64: ; RV32I-LABEL: cmov_uge_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB13_2 ; RV32I-NEXT: beq a3, a5, .LBB34_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a3, a5 ; RV32I-NEXT: sltu a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB13_3 ; RV32I-NEXT: beqz a2, .LBB34_3
; RV32I-NEXT: j .LBB13_4 ; RV32I-NEXT: j .LBB34_4
; RV32I-NEXT: .LBB13_2: ; RV32I-NEXT: .LBB34_2:
; RV32I-NEXT: sltu a2, a2, a4 ; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB13_4 ; RV32I-NEXT: bnez a2, .LBB34_4
; RV32I-NEXT: .LBB13_3: ; RV32I-NEXT: .LBB34_3:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB13_4: ; RV32I-NEXT: .LBB34_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: cmov_uge_i64: ; RV32ZBT-LABEL: cmov_uge_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5 ; RV32ZBT-NEXT: xor t0, a3, a5
; RV32ZBT-NEXT: sltu a2, a2, a4 ; RV32ZBT-NEXT: sltu a2, a2, a4
; RV32ZBT-NEXT: xori a2, a2, 1 ; RV32ZBT-NEXT: xori a2, a2, 1
; RV32ZBT-NEXT: sltu a3, a3, a5 ; RV32ZBT-NEXT: sltu a3, a3, a5
Show All 37 Lines
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshl_i64: ; RV32I-LABEL: fshl_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a5, a4, 5 ; RV32I-NEXT: srli a5, a4, 5
; RV32I-NEXT: andi a6, a5, 1 ; RV32I-NEXT: andi a6, a5, 1
; RV32I-NEXT: mv a5, a3 ; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: bnez a6, .LBB15_2 ; RV32I-NEXT: bnez a6, .LBB36_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: .LBB15_2: ; RV32I-NEXT: .LBB36_2:
; RV32I-NEXT: sll a7, a5, a4 ; RV32I-NEXT: sll a7, a5, a4
; RV32I-NEXT: bnez a6, .LBB15_4 ; RV32I-NEXT: bnez a6, .LBB36_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB15_4: ; RV32I-NEXT: .LBB36_4:
; RV32I-NEXT: srli a2, a2, 1 ; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: not a3, a4 ; RV32I-NEXT: not a3, a4
; RV32I-NEXT: srl a2, a2, a3 ; RV32I-NEXT: srl a2, a2, a3
; RV32I-NEXT: or a2, a7, a2 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: bnez a6, .LBB15_6 ; RV32I-NEXT: bnez a6, .LBB36_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB15_6: ; RV32I-NEXT: .LBB36_6:
; RV32I-NEXT: sll a0, a0, a4 ; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: srli a1, a5, 1 ; RV32I-NEXT: srli a1, a5, 1
; RV32I-NEXT: srl a1, a1, a3 ; RV32I-NEXT: srl a1, a1, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: fshl_i64: ; RV32ZBT-LABEL: fshl_i64:
Show All 40 Lines
; extensions introduce instructions that can match more efficiently this pattern. ; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)
define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshr_i64: ; RV32I-LABEL: fshr_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a5, a4, 32 ; RV32I-NEXT: andi a5, a4, 32
; RV32I-NEXT: beqz a5, .LBB17_2 ; RV32I-NEXT: beqz a5, .LBB38_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB17_2: ; RV32I-NEXT: .LBB38_2:
; RV32I-NEXT: srl a2, a2, a4 ; RV32I-NEXT: srl a2, a2, a4
; RV32I-NEXT: beqz a5, .LBB17_4 ; RV32I-NEXT: beqz a5, .LBB38_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB17_4: ; RV32I-NEXT: .LBB38_4:
; RV32I-NEXT: slli a7, a3, 1 ; RV32I-NEXT: slli a7, a3, 1
; RV32I-NEXT: not a6, a4 ; RV32I-NEXT: not a6, a4
; RV32I-NEXT: sll a7, a7, a6 ; RV32I-NEXT: sll a7, a7, a6
; RV32I-NEXT: or a2, a7, a2 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: srl a3, a3, a4 ; RV32I-NEXT: srl a3, a3, a4
; RV32I-NEXT: beqz a5, .LBB17_6 ; RV32I-NEXT: beqz a5, .LBB38_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB17_6: ; RV32I-NEXT: .LBB38_6:
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: sll a0, a0, a6 ; RV32I-NEXT: sll a0, a0, a6
; RV32I-NEXT: or a1, a0, a3 ; RV32I-NEXT: or a1, a0, a3
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: fshr_i64: ; RV32ZBT-LABEL: fshr_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
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; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a2, a3, a0, 27 ; RV32ZBT-NEXT: fsri a2, a3, a0, 27
; RV32ZBT-NEXT: fsri a1, a0, a1, 27 ; RV32ZBT-NEXT: fsri a1, a0, a1, 27
; RV32ZBT-NEXT: mv a0, a2 ; RV32ZBT-NEXT: mv a0, a2
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5) %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/rv64zbt.ll

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; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2 ; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 0 %tobool.not = icmp eq i64 %b, 0
%cond = select i1 %tobool.not, i64 %c, i64 %a %cond = select i1 %tobool.not, i64 %c, i64 %a
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_eq_i64_constant_2048(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_eq_i64_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1
; RV64I-NEXT: addiw a3, a3, -2048
; RV64I-NEXT: beq a1, a3, .LBB10_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_eq_i64_constant_2048:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: addi a1, a1, -2048
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, 2048
%cond = select i1 %tobool.not, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_eq_i64_constant_neg_2047(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_eq_i64_constant_neg_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, -2047
; RV64I-NEXT: beq a1, a3, .LBB11_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_eq_i64_constant_neg_2047:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: addi a1, a1, 2047
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
; RV64ZBT-NEXT: ret
%tobool.not = icmp eq i64 %b, -2047
%cond = select i1 %tobool.not, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ne_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ne_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: bne a1, a2, .LBB12_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB12_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ne_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: xor a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a0, a3
; RV64ZBT-NEXT: ret
%tobool.not = icmp ne i64 %b, %c
%cond = select i1 %tobool.not, i64 %a, i64 %d
ret i64 %cond
}
define i64 @cmov_ne_i64_constant_zero(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ne_i64_constant_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: bnez a1, .LBB13_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB13_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ne_i64_constant_zero:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool.not = icmp ne i64 %b, 0
%cond = select i1 %tobool.not, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ne_i64_constant_2048(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ne_i64_constant_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1
; RV64I-NEXT: addiw a3, a3, -2048
; RV64I-NEXT: bne a1, a3, .LBB14_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB14_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ne_i64_constant_2048:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: addi a1, a1, -2048
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool.not = icmp ne i64 %b, 2048
%cond = select i1 %tobool.not, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ne_i64_constant_neg_2047(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ne_i64_constant_neg_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, -2047
; RV64I-NEXT: bne a1, a3, .LBB15_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB15_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ne_i64_constant_neg_2047:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: addi a1, a1, 2047
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool.not = icmp ne i64 %b, -2047
%cond = select i1 %tobool.not, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sle_i64: ; RV64I-LABEL: cmov_sle_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB10_2 ; RV64I-NEXT: bge a2, a1, .LBB16_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: .LBB16_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_sle_i64: ; RV64ZBT-LABEL: cmov_sle_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1 ; RV64ZBT-NEXT: slt a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sle_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_sle_i64_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, 2047
; RV64I-NEXT: blt a1, a3, .LBB17_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB17_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sle_i64_constant_2046:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slti a1, a1, 2047
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp sle i64 %b, 2046
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_sle_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_sle_i64_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, -2048
; RV64I-NEXT: blt a1, a3, .LBB18_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB18_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sle_i64_constant_neg_2049:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slti a1, a1, -2048
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp sle i64 %b, -2049
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_sgt_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sgt_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: blt a2, a1, .LBB19_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sgt_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a0, a3
; RV64ZBT-NEXT: ret
%tobool = icmp sgt i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond
}
define i64 @cmov_sgt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_sgt_i64_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, 2046
; RV64I-NEXT: blt a3, a1, .LBB20_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB20_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sgt_i64_constant_2046:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slti a1, a1, 2047
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp sgt i64 %b, 2046
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_sgt_i64_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048575
; RV64I-NEXT: addiw a3, a3, 2047
; RV64I-NEXT: blt a3, a1, .LBB21_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB21_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slti a1, a1, -2048
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp sgt i64 %b, -2049
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sge_i64: ; RV64I-LABEL: cmov_sge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB11_2 ; RV64I-NEXT: bge a1, a2, .LBB22_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB11_2: ; RV64I-NEXT: .LBB22_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_sge_i64: ; RV64ZBT-LABEL: cmov_sge_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2 ; RV64ZBT-NEXT: slt a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_sge_i64_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, 2046
; RV64I-NEXT: blt a3, a1, .LBB23_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB23_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sge_i64_constant_2047:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slti a1, a1, 2047
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp sge i64 %b, 2047
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_sge_i64_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048575
; RV64I-NEXT: addiw a3, a3, 2047
; RV64I-NEXT: blt a3, a1, .LBB24_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB24_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slti a1, a1, -2048
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp sge i64 %b, -2048
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ule_i64: ; RV64I-LABEL: cmov_ule_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB12_2 ; RV64I-NEXT: bgeu a2, a1, .LBB25_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB12_2: ; RV64I-NEXT: .LBB25_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_ule_i64: ; RV64ZBT-LABEL: cmov_ule_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1 ; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ule_i64_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a1, 11
; RV64I-NEXT: beqz a1, .LBB26_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB26_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ule_i64_constant_2047:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: srli a1, a1, 11
; RV64ZBT-NEXT: cmov a0, a1, a2, a0
; RV64ZBT-NEXT: ret
%tobool = icmp ule i64 %b, 2047
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ule_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ule_i64_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, -2048
; RV64I-NEXT: bltu a1, a3, .LBB27_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB27_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ule_i64_constant_neg_2049:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltiu a1, a1, -2048
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp ule i64 %b, -2049
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ugt_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ugt_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: bltu a2, a1, .LBB28_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB28_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ugt_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64ZBT-NEXT: cmov a0, a1, a0, a3
; RV64ZBT-NEXT: ret
%tobool = icmp ugt i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond
}
define i64 @cmov_ugt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ugt_i64_constant_2046:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, 2046
; RV64I-NEXT: bltu a3, a1, .LBB29_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB29_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ugt_i64_constant_2046:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltiu a1, a1, 2047
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp ugt i64 %b, 2046
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_ugt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_ugt_i64_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048575
; RV64I-NEXT: addiw a3, a3, 2047
; RV64I-NEXT: bltu a3, a1, .LBB30_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB30_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ugt_i64_constant_neg_2049:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltiu a1, a1, -2048
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp ugt i64 %b, -2049
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_uge_i64: ; RV64I-LABEL: cmov_uge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB13_2 ; RV64I-NEXT: bgeu a1, a2, .LBB31_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB13_2: ; RV64I-NEXT: .LBB31_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBT-LABEL: cmov_uge_i64: ; RV64ZBT-LABEL: cmov_uge_i64:
; RV64ZBT: # %bb.0: ; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2 ; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64ZBT-NEXT: cmov a0, a1, a3, a0 ; RV64ZBT-NEXT: cmov a0, a1, a3, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
%tobool = icmp uge i64 %b, %c %tobool = icmp uge i64 %b, %c
%cond = select i1 %tobool, i64 %a, i64 %d %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_uge_i64_constant_2047:
; RV64I: # %bb.0:
; RV64I-NEXT: li a3, 2046
; RV64I-NEXT: bltu a3, a1, .LBB32_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB32_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_uge_i64_constant_2047:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltiu a1, a1, 2047
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp uge i64 %b, 2047
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
define i64 @cmov_uge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_uge_i64_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a3, 1048575
; RV64I-NEXT: addiw a3, a3, 2047
; RV64I-NEXT: bltu a3, a1, .LBB33_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB33_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_uge_i64_constant_neg_2048:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltiu a1, a1, -2048
; RV64ZBT-NEXT: xori a1, a1, 1
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64ZBT-NEXT: ret
%tobool = icmp uge i64 %b, -2048
%cond = select i1 %tobool, i64 %a, i64 %c
ret i64 %cond
}
declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshl.i32(i32, i32, i32)
define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: fshl_i32: ; RV64I-LABEL: fshl_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
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