[RISCV] [NFC] Add Immediate tests for the cmov instruction

[craig.topper]

llvm/test/CodeGen/RISCV/i32-icmp.ll

211

Why are you changing unsigned constants to signed? Wasn't unsigned requested in the previous review?

[Miss_Grape]

Why are you changing unsigned constants to signed? Wasn't unsigned requested in the previous review?

Fixed

[Miss_Grape]

ping

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/i32-icmp.ll

 }
 
 define i32 @icmp_ugt_constant_neg_2049(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ugt_constant_neg_2049:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltiu a0, a0, -2048
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp ugt i32 %a, 4294965247
+  %1 = icmp ugt i32 %a, -2049
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_ugt_constant_neg_2050(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ugt_constant_neg_2050:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1048575
 ; RV32I-NEXT:    addi a1, a1, 2046
 ; RV32I-NEXT:    sltu a0, a1, a0
 ; RV32I-NEXT:    ret
-; 4294965246 signed extend is -2050
-  %1 = icmp ugt i32 %a, 4294965246
+  %1 = icmp ugt i32 %a, -2050
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1

 }
 
 define i32 @icmp_uge_constant_neg_2048(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_uge_constant_neg_2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltiu a0, a0, -2048
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
-; 4294965248 signed extend is -2048
-  %1 = icmp uge i32 %a, 4294965248
+  %1 = icmp uge i32 %a, -2048
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_uge_constant_neg_2049(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_uge_constant_neg_2049:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1048575
 ; RV32I-NEXT:    addi a1, a1, 2046
 ; RV32I-NEXT:    sltu a0, a1, a0
 ; RV32I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp uge i32 %a, 4294965247
+  %1 = icmp uge i32 %a, -2049
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
; RV32I-NEXT:    ret
   ret i32 %2
 }
 
 define i32 @icmp_ult_constant_neg_2048(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ult_constant_neg_2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltiu a0, a0, -2048
 ; RV32I-NEXT:    ret
-; 4294965248 signed extend is -2048
-  %1 = icmp ult i32 %a, 4294965248
+  %1 = icmp ult i32 %a, -2048
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_ult_constant_neg_2049(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ult_constant_neg_2049:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1048575
 ; RV32I-NEXT:    addi a1, a1, 2047
 ; RV32I-NEXT:    sltu a0, a0, a1
 ; RV32I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp ult i32 %a, 4294965247
+  %1 = icmp ult i32 %a, -2049
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
; RV32I-NEXT:    ret
   ret i32 %2
 }
 
 define i32 @icmp_ule_constant_neg_2049(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ule_constant_neg_2049:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltiu a0, a0, -2048
 ; RV32I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp ule i32 %a, 4294965247
+  %1 = icmp ule i32 %a, -2049
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_ule_constant_neg_2050(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ule_constant_neg_2050:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1048575
 ; RV32I-NEXT:    addi a1, a1, 2047
 ; RV32I-NEXT:    sltu a0, a0, a1
 ; RV32I-NEXT:    ret
-; 4294965246 signed extend is -2050
-  %1 = icmp ule i32 %a, 4294965246
+  %1 = icmp ule i32 %a, -2050
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: icmp_sgt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0

llvm/test/CodeGen/RISCV/i64-icmp.ll

; RV64I-NEXT:    ret
   %1 = icmp ugt i64 %a, 2046
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ugt_constant_neg_2049:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1046527
-; RV64I-NEXT:    slli a1, a1, 20
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    sltiu a0, a0, -2048
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp ugt i64 %a, 4294965247
+  %1 = icmp ugt i64 %a, -2049
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ugt_constant_neg_2050:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -1025
-; RV64I-NEXT:    slli a1, a1, 33
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    lui a1, 1048575
+; RV64I-NEXT:    addiw a1, a1, 2046
 ; RV64I-NEXT:    sltu a0, a1, a0
 ; RV64I-NEXT:    ret
-; 4294965246 signed extend is -2050
-  %1 = icmp ugt i64 %a, 4294965246
+  %1 = icmp ugt i64 %a, -2050
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_uge(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: icmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
   %1 = icmp uge i64 %a, 2048
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_uge_constant_neg_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1046527
-; RV64I-NEXT:    slli a1, a1, 20
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    sltiu a0, a0, -2048
+; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
-; 4294965248 signed extend is -2048
-  %1 = icmp uge i64 %a, 4294965248
+  %1 = icmp uge i64 %a, -2048
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_uge_constant_neg_2049:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -1025
-; RV64I-NEXT:    slli a1, a1, 33
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    lui a1, 1048575
+; RV64I-NEXT:    addiw a1, a1, 2046
 ; RV64I-NEXT:    sltu a0, a1, a0
 ; RV64I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp uge i64 %a, 4294965247
+  %1 = icmp uge i64 %a, -2049
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ult(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: icmp_ult:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
   %1 = icmp ult i64 %a, 2048
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ult_constant_neg_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    addi a1, a1, -2048
-; RV64I-NEXT:    sltu a0, a0, a1
+; RV64I-NEXT:    sltiu a0, a0, -2048
 ; RV64I-NEXT:    ret
-; 4294965248 signed extend is -2048
-  %1 = icmp ult i64 %a, 4294965248
+  %1 = icmp ult i64 %a, -2048
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ult_constant_neg_2049:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1046527
-; RV64I-NEXT:    slli a1, a1, 20
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    lui a1, 1048575
+; RV64I-NEXT:    addiw a1, a1, 2047
 ; RV64I-NEXT:    sltu a0, a0, a1
 ; RV64I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp ult i64 %a, 4294965247
+  %1 = icmp ult i64 %a, -2049
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ule(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: icmp_ule:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
   %1 = icmp ule i64 %a, 2047
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ule_constant_neg_2049:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    addi a1, a1, -2048
-; RV64I-NEXT:    sltu a0, a0, a1
+; RV64I-NEXT:    sltiu a0, a0, -2048
 ; RV64I-NEXT:    ret
-; 4294965247 signed extend is -2049
-  %1 = icmp ule i64 %a, 4294965247
+  %1 = icmp ule i64 %a, -2049
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ule_constant_neg_2050:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1046527
-; RV64I-NEXT:    slli a1, a1, 20
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    lui a1, 1048575
+; RV64I-NEXT:    addiw a1, a1, 2047
 ; RV64I-NEXT:    sltu a0, a0, a1
 ; RV64I-NEXT:    ret
-; 4294965246 signed extend is -2050
-  %1 = icmp ule i64 %a, 4294965246
+  %1 = icmp ule i64 %a, -2050
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_sgt(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: icmp_sgt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a1, a0

llvm/test/CodeGen/RISCV/rv32zbt.ll

 ; RV32ZBT-NEXT:    cmix a1, a3, a1, a5
 ; RV32ZBT-NEXT:    ret
   %xor = xor i64 %a, %c
   %and = and i64 %xor, %b
   %xor1 = xor i64 %and, %c
   ret i64 %xor1
 }
 
-define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind {
-; RV32I-LABEL: cmov_i32:
+define i32 @cmov_eq_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; RV32I-LABEL: cmov_eq_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a1, .LBB4_2
+; RV32I-NEXT:    beq a1, a2, .LBB4_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a2, a0
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB4_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_eq_i32:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    xor a1, a1, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a3, a0
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp eq i32 %b, %c
+  %cond = select i1 %tobool.not, i32 %a, i32 %d
+  ret i32 %cond
+}
+
+define i32 @cmov_eq_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_eq_i32_constant_zero:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    beqz a1, .LBB5_2
+; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB5_2:
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBT-LABEL: cmov_i32:
+; RV32ZBT-LABEL: cmov_eq_i32_constant_zero:
 ; RV32ZBT:       # %bb.0:
-; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
 ; RV32ZBT-NEXT:    ret
   %tobool.not = icmp eq i32 %b, 0
-  %cond = select i1 %tobool.not, i32 %c, i32 %a
+  %cond = select i1 %tobool.not, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_eq_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_eq_i32_constant_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a3, 1
+; RV32I-NEXT:    addi a3, a3, -2048
+; RV32I-NEXT:    beq a1, a3, .LBB6_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB6_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_eq_i32_constant_2048:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    addi a1, a1, -2048
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp eq i32 %b, 2048
+  %cond = select i1 %tobool.not, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_eq_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_eq_i32_constant_neg_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, -2047
+; RV32I-NEXT:    beq a1, a3, .LBB7_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB7_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_eq_i32_constant_neg_2047:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    addi a1, a1, 2047
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp eq i32 %b, -2047
+  %cond = select i1 %tobool.not, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_ne_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; RV32I-LABEL: cmov_ne_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bne a1, a2, .LBB8_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:  .LBB8_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    xor a1, a1, a2
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a3
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp ne i32 %b, %c
+  %cond = select i1 %tobool.not, i32 %a, i32 %d
+  ret i32 %cond
+}
+
+define i32 @cmov_ne_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ne_i32_constant_zero:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bnez a1, .LBB9_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB9_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32_constant_zero:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp ne i32 %b, 0
+  %cond = select i1 %tobool.not, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_ne_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ne_i32_constant_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a3, 1
+; RV32I-NEXT:    addi a3, a3, -2048
+; RV32I-NEXT:    bne a1, a3, .LBB10_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB10_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32_constant_2048:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    addi a1, a1, -2048
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp ne i32 %b, 2048
+  %cond = select i1 %tobool.not, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_ne_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ne_i32_constant_neg_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, -2047
+; RV32I-NEXT:    bne a1, a3, .LBB11_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB11_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32_constant_neg_2047:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    addi a1, a1, 2047
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool.not = icmp ne i32 %b, -2047
+  %cond = select i1 %tobool.not, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_sle_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bge a2, a1, .LBB5_2
+; RV32I-NEXT:    bge a2, a1, .LBB12_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:  .LBB5_2:
+; RV32I-NEXT:  .LBB12_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sle_i32:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slt a1, a2, a1
 ; RV32ZBT-NEXT:    cmov a0, a1, a3, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sle i32 %b, %c
   %cond = select i1 %tobool, i32 %a, i32 %d
   ret i32 %cond
 }
 
+define i32 @cmov_sle_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sle_i32_constant_2046:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, 2047
+; RV32I-NEXT:    blt a1, a3, .LBB13_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB13_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_sle_i32_constant_2046:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    slti a1, a1, 2047
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp sle i32 %b, 2046
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_sle_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sle_i32_constant_neg_2049:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, -2048
+; RV32I-NEXT:    blt a1, a3, .LBB14_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB14_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_sle_i32_constant_neg_2049:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    slti a1, a1, -2048
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp sle i32 %b, -2049
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
 define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_sge_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bge a1, a2, .LBB6_2
+; RV32I-NEXT:    bge a1, a2, .LBB15_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:  .LBB6_2:
+; RV32I-NEXT:  .LBB15_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sge_i32:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slt a1, a1, a2
 ; RV32ZBT-NEXT:    cmov a0, a1, a3, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i32 %b, %c
   %cond = select i1 %tobool, i32 %a, i32 %d
   ret i32 %cond
 }
 
+define i32 @cmov_sge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sge_i32_constant_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, 2046
+; RV32I-NEXT:    blt a3, a1, .LBB16_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB16_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    slti a1, a1, 2047
+; RV32ZBT-NEXT:    xori a1, a1, 1
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp sge i32 %b, 2047
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a3, 1048575
+; RV32I-NEXT:    addi a3, a3, 2047
+; RV32I-NEXT:    blt a3, a1, .LBB17_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB17_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    slti a1, a1, -2048
+; RV32ZBT-NEXT:    xori a1, a1, 1
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp sge i32 %b, -2048
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
 define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_ule_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bgeu a2, a1, .LBB7_2
+; RV32I-NEXT:    bgeu a2, a1, .LBB18_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:  .LBB7_2:
+; RV32I-NEXT:  .LBB18_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_ule_i32:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltu a1, a2, a1
 ; RV32ZBT-NEXT:    cmov a0, a1, a3, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ule i32 %b, %c
   %cond = select i1 %tobool, i32 %a, i32 %d
   ret i32 %cond
 }
 
+define i32 @cmov_ule_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ule_i32_constant_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a1, a1, 11
+; RV32I-NEXT:    beqz a1, .LBB19_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB19_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_ule_i32_constant_2047:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    srli a1, a1, 11
+; RV32ZBT-NEXT:    cmov a0, a1, a2, a0
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp ule i32 %b, 2047
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_ule_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ule_i32_constant_neg_2049:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, -2048
+; RV32I-NEXT:    bltu a1, a3, .LBB20_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB20_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_ule_i32_constant_neg_2049:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    sltiu a1, a1, -2048
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp ule i32 %b, -2049
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
 define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 ; RV32I-LABEL: cmov_uge_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bgeu a1, a2, .LBB8_2
+; RV32I-NEXT:    bgeu a1, a2, .LBB21_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:  .LBB8_2:
+; RV32I-NEXT:  .LBB21_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_uge_i32:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    sltu a1, a1, a2
 ; RV32ZBT-NEXT:    cmov a0, a1, a3, a0
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp uge i32 %b, %c
   %cond = select i1 %tobool, i32 %a, i32 %d
   ret i32 %cond
 }
 
+define i32 @cmov_uge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_uge_i32_constant_2047:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a3, 2046
+; RV32I-NEXT:    bltu a3, a1, .LBB22_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB22_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    sltiu a1, a1, 2047
+; RV32ZBT-NEXT:    xori a1, a1, 1
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp uge i32 %b, 2047
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
+define i32 @cmov_uge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_uge_i32_constant_neg_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a3, 1048575
+; RV32I-NEXT:    addi a3, a3, 2047
+; RV32I-NEXT:    bltu a3, a1, .LBB23_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:  .LBB23_2:
+; RV32I-NEXT:    ret
+;
+; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    sltiu a1, a1, -2048
+; RV32ZBT-NEXT:    xori a1, a1, 1
+; RV32ZBT-NEXT:    cmov a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
+  %tobool = icmp uge i32 %b, -2048
+  %cond = select i1 %tobool, i32 %a, i32 %c
+  ret i32 %cond
+}
+
 define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: cmov_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    or a2, a2, a3
-; RV32I-NEXT:    beqz a2, .LBB9_2
+; RV32I-NEXT:    beqz a2, .LBB24_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    mv a5, a1
-; RV32I-NEXT:  .LBB9_2:
+; RV32I-NEXT:  .LBB24_2:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_i64:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    or a2, a2, a3
 ; RV32ZBT-NEXT:    cmov a0, a2, a0, a4
 ; RV32ZBT-NEXT:    cmov a1, a2, a1, a5
 ; RV32ZBT-NEXT:    ret
   %tobool.not = icmp eq i64 %b, 0
   %cond = select i1 %tobool.not, i64 %c, i64 %a
   ret i64 %cond
 }
 
 define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_sle_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a3, a5, .LBB10_2
+; RV32I-NEXT:    beq a3, a5, .LBB25_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a2, a5, a3
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    beqz a2, .LBB10_3
-; RV32I-NEXT:    j .LBB10_4
-; RV32I-NEXT:  .LBB10_2:
+; RV32I-NEXT:    beqz a2, .LBB25_3
+; RV32I-NEXT:    j .LBB25_4
+; RV32I-NEXT:  .LBB25_2:
 ; RV32I-NEXT:    sltu a2, a4, a2
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    bnez a2, .LBB10_4
-; RV32I-NEXT:  .LBB10_3:
+; RV32I-NEXT:    bnez a2, .LBB25_4
+; RV32I-NEXT:  .LBB25_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
-; RV32I-NEXT:  .LBB10_4:
+; RV32I-NEXT:  .LBB25_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sle_i64:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a4, a2
 ; RV32ZBT-NEXT:    xori a2, a2, 1
 ; RV32ZBT-NEXT:    slt a3, a5, a3
 ; RV32ZBT-NEXT:    xori a3, a3, 1
 ; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
 ; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
 ; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sle i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_sge_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a3, a5, .LBB11_2
+; RV32I-NEXT:    beq a3, a5, .LBB26_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a2, a3, a5
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    beqz a2, .LBB11_3
-; RV32I-NEXT:    j .LBB11_4
-; RV32I-NEXT:  .LBB11_2:
+; RV32I-NEXT:    beqz a2, .LBB26_3
+; RV32I-NEXT:    j .LBB26_4
+; RV32I-NEXT:  .LBB26_2:
 ; RV32I-NEXT:    sltu a2, a2, a4
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    bnez a2, .LBB11_4
-; RV32I-NEXT:  .LBB11_3:
+; RV32I-NEXT:    bnez a2, .LBB26_4
+; RV32I-NEXT:  .LBB26_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
-; RV32I-NEXT:  .LBB11_4:
+; RV32I-NEXT:  .LBB26_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sge_i64:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a2, a4
 ; RV32ZBT-NEXT:    xori a2, a2, 1
 ; RV32ZBT-NEXT:    slt a3, a3, a5
 ; RV32ZBT-NEXT:    xori a3, a3, 1
 ; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
 ; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
 ; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_ule_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a3, a5, .LBB12_2
+; RV32I-NEXT:    beq a3, a5, .LBB27_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a2, a5, a3
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    beqz a2, .LBB12_3
-; RV32I-NEXT:    j .LBB12_4
-; RV32I-NEXT:  .LBB12_2:
+; RV32I-NEXT:    beqz a2, .LBB27_3
+; RV32I-NEXT:    j .LBB27_4
+; RV32I-NEXT:  .LBB27_2:
 ; RV32I-NEXT:    sltu a2, a4, a2
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    bnez a2, .LBB12_4
-; RV32I-NEXT:  .LBB12_3:
+; RV32I-NEXT:    bnez a2, .LBB27_4
+; RV32I-NEXT:  .LBB27_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
-; RV32I-NEXT:  .LBB12_4:
+; RV32I-NEXT:  .LBB27_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_ule_i64:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a4, a2
 ; RV32ZBT-NEXT:    xori a2, a2, 1
 ; RV32ZBT-NEXT:    sltu a3, a5, a3
 ; RV32ZBT-NEXT:    xori a3, a3, 1
 ; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
 ; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
 ; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ule i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_uge_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a3, a5, .LBB13_2
+; RV32I-NEXT:    beq a3, a5, .LBB28_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a2, a3, a5
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    beqz a2, .LBB13_3
-; RV32I-NEXT:    j .LBB13_4
-; RV32I-NEXT:  .LBB13_2:
+; RV32I-NEXT:    beqz a2, .LBB28_3
+; RV32I-NEXT:    j .LBB28_4
+; RV32I-NEXT:  .LBB28_2:
 ; RV32I-NEXT:    sltu a2, a2, a4
 ; RV32I-NEXT:    xori a2, a2, 1
-; RV32I-NEXT:    bnez a2, .LBB13_4
-; RV32I-NEXT:  .LBB13_3:
+; RV32I-NEXT:    bnez a2, .LBB28_4
+; RV32I-NEXT:  .LBB28_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
-; RV32I-NEXT:  .LBB13_4:
+; RV32I-NEXT:  .LBB28_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_uge_i64:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a2, a4
 ; RV32ZBT-NEXT:    xori a2, a2, 1
 ; RV32ZBT-NEXT:    sltu a3, a3, a5

 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: fshl_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a5, a4, 5
 ; RV32I-NEXT:    andi a6, a5, 1
 ; RV32I-NEXT:    mv a5, a3
-; RV32I-NEXT:    bnez a6, .LBB15_2
+; RV32I-NEXT:    bnez a6, .LBB30_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a5, a0
-; RV32I-NEXT:  .LBB15_2:
+; RV32I-NEXT:  .LBB30_2:
 ; RV32I-NEXT:    sll a7, a5, a4
-; RV32I-NEXT:    bnez a6, .LBB15_4
+; RV32I-NEXT:    bnez a6, .LBB30_4
 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:  .LBB15_4:
+; RV32I-NEXT:  .LBB30_4:
 ; RV32I-NEXT:    srli a2, a2, 1
 ; RV32I-NEXT:    not a3, a4
 ; RV32I-NEXT:    srl a2, a2, a3
 ; RV32I-NEXT:    or a2, a7, a2
-; RV32I-NEXT:    bnez a6, .LBB15_6
+; RV32I-NEXT:    bnez a6, .LBB30_6
 ; RV32I-NEXT:  # %bb.5:
 ; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB15_6:
+; RV32I-NEXT:  .LBB30_6:
 ; RV32I-NEXT:    sll a0, a0, a4
 ; RV32I-NEXT:    srli a1, a5, 1
 ; RV32I-NEXT:    srl a1, a1, a3
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: fshl_i64:

 ; extensions introduce instructions that can match more efficiently this pattern.
 
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: fshr_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a5, a4, 32
-; RV32I-NEXT:    beqz a5, .LBB17_2
+; RV32I-NEXT:    beqz a5, .LBB32_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:  .LBB17_2:
+; RV32I-NEXT:  .LBB32_2:
 ; RV32I-NEXT:    srl a2, a2, a4
-; RV32I-NEXT:    beqz a5, .LBB17_4
+; RV32I-NEXT:    beqz a5, .LBB32_4
 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:  .LBB17_4:
+; RV32I-NEXT:  .LBB32_4:
 ; RV32I-NEXT:    slli a7, a3, 1
 ; RV32I-NEXT:    not a6, a4
 ; RV32I-NEXT:    sll a7, a7, a6
 ; RV32I-NEXT:    or a2, a7, a2
 ; RV32I-NEXT:    srl a3, a3, a4
-; RV32I-NEXT:    beqz a5, .LBB17_6
+; RV32I-NEXT:    beqz a5, .LBB32_6
 ; RV32I-NEXT:  # %bb.5:
 ; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB17_6:
+; RV32I-NEXT:  .LBB32_6:
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    sll a0, a0, a6
 ; RV32I-NEXT:    or a1, a0, a3
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: fshr_i64:
 ; RV32ZBT:       # %bb.0:

 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    fsri a2, a3, a0, 27
 ; RV32ZBT-NEXT:    fsri a1, a0, a1, 27
 ; RV32ZBT-NEXT:    mv a0, a2
 ; RV32ZBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }
+