[RISCV] Add pattern for vnsrl.wi and vnsra.wi instructions

[Jimerlife]

Summary

Add pattern for vnsrl.wi and vnsra.wi instructions

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

799–800

It feels to me like we should just have one VPatBinarySDNode_V_WV_WX_WI since the individual WV, WX, and WI patterns are only ever used in conjunction with one another.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

676

The new pattern and the existing patterns are all checking for the VL being exactly X0. Why is that?

[Jimerlife]

update code, combine one class VPatBinarySDNode_V_WV_WX_WI

[Jimerlife]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

676

This patch https://reviews.llvm.org/D118845 move VLMax to X0

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

676

That wasn't what I was referring to. Most of the patterns in this file use VLOpFrag not X0 so that they work for fixed vectors and VP intrinsics too. This pattern only works VLMax scalable vectors.

[Jimerlife]

Address comments

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2,
         (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK")
             (vti_m1.Vector VR:$merge),
             (vti.Vector vti.RegClass:$rs1),
             (vti_m1.Vector VR:$rs2),
             (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
   }
 }
 
-multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instruction_name> {
+multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
   foreach vti = AllWidenableIntVectors in {
     def : Pat<
       (vti.Vti.Vector
         (riscv_trunc_vector_vl
           (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
               (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
-          (riscv_vmset_vl X0),
-          X0)),
+          (riscv_vmset_vl VLOpFrag),
+          VLOpFrag)),
       (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
         vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
         vti.Vti.AVL, vti.Vti.Log2SEW)>;
-  }
-}
-
-multiclass VPatBinarySDNodeExt_V_WX<SDNode op, PatFrags extop, string instruction_name> {
-  foreach vti = AllWidenableIntVectors in {
     def : Pat<
       (vti.Vti.Vector
         (riscv_trunc_vector_vl
           (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
               (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
-          (riscv_vmset_vl X0),
-          X0)),
+          (riscv_vmset_vl VLOpFrag),
+          VLOpFrag)),
       (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
         vti.Wti.RegClass:$rs2, GPR:$rs1,
         vti.Vti.AVL, vti.Vti.Log2SEW)>;
   }
 }
 
-
-multiclass VPatBinarySDNode_V_WV<SDNode op, string instruction_name> {
-  defm : VPatBinarySDNodeExt_V_WV<op, sext_oneuse, instruction_name>;
-  defm : VPatBinarySDNodeExt_V_WV<op, zext_oneuse, instruction_name>;
+multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> {
+  defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>;
+  defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>;
+  foreach vti = AllWidenableIntVectors in {
+    def : Pat<
+      (vti.Vti.Vector
+        (riscv_trunc_vector_vl
+          (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+              (vti.Wti.Vector (SplatPat_uimm5 uimm5:$rs1))),
+          (riscv_vmset_vl VLOpFrag),
+          VLOpFrag)),
+      (!cast<Instruction>(instruction_name#"_WI_"#vti.Vti.LMul.MX)
+        vti.Wti.RegClass:$rs2, uimm5:$rs1,
+        vti.Vti.AVL, vti.Vti.Log2SEW)>;
   }
-
-multiclass VPatBinarySDNode_V_WX<SDNode op, string instruction_name> {
-  defm : VPatBinarySDNodeExt_V_WX<op, sext_oneuse, instruction_name>;
-  defm : VPatBinarySDNodeExt_V_WX<op, zext_oneuse, instruction_name>;
 }
 
 multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
   foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
     defvar vti = vtiToWti.Vti;
     defvar wti = vtiToWti.Wti;
     defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
     def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
foreach vti = AllIntegerVectors in {
   def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1),
                           (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)),
                           (vti.Mask true_mask),
                           VLOpFrag),
             (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
                  vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
 }
 
 // 12.7. Vector Narrowing Integer Right Shift Instructions
-defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">;
-defm : VPatBinarySDNode_V_WX<srl, "PseudoVNSRL">;
-defm : VPatBinarySDNode_V_WV<sra, "PseudoVNSRA">;
-defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">;
+defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">;
+defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">;
 
 foreach vtiTowti = AllWidenableIntVectors in {
   defvar vti = vtiTowti.Vti;
   defvar wti = vtiTowti.Wti;
   def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),
                                                (vti.Mask true_mask),
                                                VLOpFrag)),
             (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX)

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

; RV64-NEXT:    ret
   %v47 = trunc <2 x i32> %v46 to <2 x i16>
   %v48 = and <2 x i16> %v44, %v47
   ret <2 x i16> %v48
 }
 
 define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) {
 ; CHECK-LABEL: scalable:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vsrl.vi v8, v8, 16
-; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT:    vnsrl.wx v8, v8, zero
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v8, 16
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vand.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %v41 = insertelement <vscale x 2 x i32> poison, i32 16, i32 0
   %v42 = shufflevector <vscale x 2 x i32> %v41, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %v43 = lshr <vscale x 2 x i32> %x, %v42
   %v44 = trunc <vscale x 2 x i32> %v43 to <vscale x 2 x i16>
   %v45 =  insertelement <vscale x 2 x i32> poison, i32 -32768, i32 0
   %v46 = shufflevector <vscale x 2 x i32> %v45, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %v47 = trunc <vscale x 2 x i32> %v46 to <vscale x 2 x i16>
   %v48 = and <vscale x 2 x i16> %v44, %v47
   ret <vscale x 2 x i16> %v48
 }

llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv1i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v9, v9
-; RV32D-NEXT:    vsrl.vi v9, v9, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v9, v9, zero
+; RV32D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v9, v9, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    vrsub.vx v8, v9, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv1i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v9, v9
-; RV64D-NEXT:    vsrl.vi v9, v9, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v9, v9, zero
+; RV64D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v9, v9, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    vrsub.vx v8, v9, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i8> @llvm.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false)

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv2i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v9, v9
-; RV32D-NEXT:    vsrl.vi v9, v9, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v9, v9, zero
+; RV32D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v9, v9, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    vrsub.vx v8, v9, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv2i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v9, v9
-; RV64D-NEXT:    vsrl.vi v9, v9, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v9, v9, zero
+; RV64D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v9, v9, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    vrsub.vx v8, v9, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i8> @llvm.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false)

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv4i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v10, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v10, v10
-; RV32D-NEXT:    vsrl.vi v10, v10, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v9, v10, zero
+; RV32D-NEXT:    vnsrl.wi v9, v10, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v9, v9, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    vrsub.vx v8, v9, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv4i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v10, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v10, v10
-; RV64D-NEXT:    vsrl.vi v10, v10, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v9, v10, zero
+; RV64D-NEXT:    vnsrl.wi v9, v10, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v9, v9, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    vrsub.vx v8, v9, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i8> @llvm.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false)

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv8i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v12, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v12, v12
-; RV32D-NEXT:    vsrl.vi v12, v12, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v12, zero
+; RV32D-NEXT:    vnsrl.wi v10, v12, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v9, v10, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    vrsub.vx v8, v9, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv8i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v12, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v12, v12
-; RV64D-NEXT:    vsrl.vi v12, v12, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v12, zero
+; RV64D-NEXT:    vnsrl.wi v10, v12, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v9, v10, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    vrsub.vx v8, v9, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i8> @llvm.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false)

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv16i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v16, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v16, v16
-; RV32D-NEXT:    vsrl.vi v16, v16, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v16, zero
+; RV32D-NEXT:    vnsrl.wi v12, v16, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v10, v12, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    vrsub.vx v8, v10, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv16i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v16, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v16, v16
-; RV64D-NEXT:    vsrl.vi v16, v16, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v16, zero
+; RV64D-NEXT:    vnsrl.wi v12, v16, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v10, v12, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    vrsub.vx v8, v10, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false)

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv1i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV32D-NEXT:    vsrl.vi v9, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v9, v9, zero
+; RV32D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v9, v9, a0
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv1i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV64D-NEXT:    vsrl.vi v9, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v9, v9, zero
+; RV64D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v9, v9, a0
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i16> @llvm.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
   ret <vscale x 1 x i16> %a

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv2i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV32D-NEXT:    vsrl.vi v9, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v9, v9, zero
+; RV32D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v9, v9, a0
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv2i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV64D-NEXT:    vsrl.vi v9, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v9, v9, zero
+; RV64D-NEXT:    vnsrl.wi v9, v9, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v9, v9, a0
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
   ret <vscale x 2 x i16> %a

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv4i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32D-NEXT:    vsrl.vi v10, v10, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v9, v10, zero
+; RV32D-NEXT:    vnsrl.wi v9, v10, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v9, v9, a0
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv4i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64D-NEXT:    vsrl.vi v10, v10, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v9, v10, zero
+; RV64D-NEXT:    vnsrl.wi v9, v10, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v9, v9, a0
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v9, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i16> @llvm.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
   ret <vscale x 4 x i16> %a

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv8i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV32D-NEXT:    vsrl.vi v12, v12, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v12, zero
+; RV32D-NEXT:    vnsrl.wi v10, v12, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v10, v10, a0
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v10, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv8i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV64D-NEXT:    vsrl.vi v12, v12, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v12, zero
+; RV64D-NEXT:    vnsrl.wi v10, v12, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v10, v10, a0
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v10, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
   ret <vscale x 8 x i16> %a

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_nxv16i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV32D-NEXT:    vsrl.vi v16, v16, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v16, zero
+; RV32D-NEXT:    vnsrl.wi v12, v16, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v12, v12, a0
 ; RV32D-NEXT:    vmseq.vi v0, v8, 0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v12, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_nxv16i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV64D-NEXT:    vsrl.vi v16, v16, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v16, zero
+; RV64D-NEXT:    vnsrl.wi v12, v16, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v12, v12, a0
 ; RV64D-NEXT:    vmseq.vi v0, v8, 0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v12, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i16> @llvm.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
   ret <vscale x 16 x i16> %a

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv1i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv1i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i8> @llvm.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
   ret <vscale x 1 x i8> %a
 }

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv2i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv2i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i8> @llvm.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
   ret <vscale x 2 x i8> %a
 }

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv4i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v10, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v8, zero
+; RV32D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v10, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv4i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v10, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v8, zero
+; RV64D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v10, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i8> @llvm.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
   ret <vscale x 4 x i8> %a
 }

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv8i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v12, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v8, zero
+; RV32D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v12, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv8i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v12, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v8, zero
+; RV64D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v12, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i8> @llvm.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
   ret <vscale x 8 x i8> %a
 }

 ; RV64I-NEXT:    vand.vi v8, v8, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv16i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v16, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v16, v8, zero
+; RV32D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v16, zero
 ; RV32D-NEXT:    li a0, 134
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv16i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v16, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v16, v8, zero
+; RV64D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v16, zero
 ; RV64D-NEXT:    li a0, 134
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
   ret <vscale x 16 x i8> %a
 }

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv1i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv1i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i16> @llvm.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv2i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 142
 ; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv2i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 142
 ; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv4i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v10, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV32D-NEXT:    li a0, 142
-; RV32D-NEXT:    vrsub.vx v8, v10, a0
+; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv4i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v10, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV64D-NEXT:    li a0, 142
-; RV64D-NEXT:    vrsub.vx v8, v10, a0
+; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i16> @llvm.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
 ; RV32I-LABEL: ctlz_zero_undef_nxv8i16:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv8i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v12, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV32D-NEXT:    li a0, 142
-; RV32D-NEXT:    vrsub.vx v8, v12, a0
+; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv8i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v12, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV64D-NEXT:    li a0, 142
-; RV64D-NEXT:    vrsub.vx v8, v12, a0
+; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
 ; RV32I-LABEL: ctlz_zero_undef_nxv16i16:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    vmul.vx v8, v8, a0
 ; RV64I-NEXT:    vsrl.vi v8, v8, 8
 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: ctlz_zero_undef_nxv16i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v16, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v16, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV32D-NEXT:    li a0, 142
-; RV32D-NEXT:    vrsub.vx v8, v16, a0
+; RV32D-NEXT:    vrsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: ctlz_zero_undef_nxv16i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v16, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v16, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV64D-NEXT:    li a0, 142
-; RV64D-NEXT:    vrsub.vx v8, v16, a0
+; RV64D-NEXT:    vrsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i16> @llvm.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
 ; RV32-LABEL: ctlz_zero_undef_nxv32i16:
 ; RV32:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv1i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
   ret <vscale x 1 x i8> %a

 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv2i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
   ret <vscale x 2 x i8> %a

 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v10, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v8, zero
+; RV32D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v10, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv4i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v10, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v8, zero
+; RV64D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v10, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
   ret <vscale x 4 x i8> %a

 ; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v12, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v8, zero
+; RV32D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v12, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv8i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v12, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v8, zero
+; RV64D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v12, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
   ret <vscale x 8 x i8> %a

 ; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vmv.v.i v10, 0
 ; RV32D-NEXT:    vmseq.vv v0, v10, v8
 ; RV32D-NEXT:    vrsub.vi v10, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v10
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v16, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v16, v8, zero
+; RV32D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v16, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv16i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
 ; RV64D-NEXT:    vmv.v.i v10, 0
 ; RV64D-NEXT:    vmseq.vv v0, v10, v8
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v16, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v16, v8, zero
+; RV64D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v16, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
   ret <vscale x 16 x i8> %a

 ; RV32D-LABEL: cttz_nxv1i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv1i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
   ret <vscale x 1 x i16> %a
 }

 ; RV32D-LABEL: cttz_nxv2i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv2i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
   ret <vscale x 2 x i16> %a
 }

 ; RV32D-LABEL: cttz_nxv4i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV32D-NEXT:    vmv.v.i v9, 0
 ; RV32D-NEXT:    vmseq.vv v0, v9, v8
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v10, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV32D-NEXT:    li a0, 127
-; RV32D-NEXT:    vsub.vx v8, v10, a0
+; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv4i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV64D-NEXT:    vmv.v.i v9, 0
 ; RV64D-NEXT:    vmseq.vv v0, v9, v8
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v10, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV64D-NEXT:    li a0, 127
-; RV64D-NEXT:    vsub.vx v8, v10, a0
+; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
   ret <vscale x 4 x i16> %a
 }
 declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
 

 ; RV32D-LABEL: cttz_nxv8i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV32D-NEXT:    vmv.v.i v10, 0
 ; RV32D-NEXT:    vmseq.vv v0, v10, v8
 ; RV32D-NEXT:    vrsub.vi v10, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v10
 ; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v12, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV32D-NEXT:    li a0, 127
-; RV32D-NEXT:    vsub.vx v8, v12, a0
+; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv8i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV64D-NEXT:    vmv.v.i v10, 0
 ; RV64D-NEXT:    vmseq.vv v0, v10, v8
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v12, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV64D-NEXT:    li a0, 127
-; RV64D-NEXT:    vsub.vx v8, v12, a0
+; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
   ret <vscale x 8 x i16> %a
 }
 declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
 

 ; RV32D-LABEL: cttz_nxv16i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV32D-NEXT:    vmv.v.i v12, 0
 ; RV32D-NEXT:    vmseq.vv v0, v12, v8
 ; RV32D-NEXT:    vrsub.vi v12, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v12
 ; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v16, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v16, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV32D-NEXT:    li a0, 127
-; RV32D-NEXT:    vsub.vx v8, v16, a0
+; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    li a0, 16
 ; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_nxv16i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV64D-NEXT:    vmv.v.i v12, 0
 ; RV64D-NEXT:    vmseq.vv v0, v12, v8
 ; RV64D-NEXT:    vrsub.vi v12, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v12
 ; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v16, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v16, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV64D-NEXT:    li a0, 127
-; RV64D-NEXT:    vsub.vx v8, v16, a0
+; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    li a0, 16
 ; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
   ret <vscale x 16 x i16> %a
 }
 declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
 

 ; RV32D-LABEL: cttz_zero_undef_nxv1i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv1i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
   ret <vscale x 1 x i8> %a
 }

 ; RV32D-LABEL: cttz_zero_undef_nxv2i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v9, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv2i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v9, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v8, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
   ret <vscale x 2 x i8> %a
 }

 ; RV32D-LABEL: cttz_zero_undef_nxv4i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v10, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v8, zero
+; RV32D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v10, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv4i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v10, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v8, zero
+; RV64D-NEXT:    vnsrl.wi v10, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v10, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
   ret <vscale x 4 x i8> %a
 }

 ; RV32D-LABEL: cttz_zero_undef_nxv8i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v12, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v8, zero
+; RV32D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v12, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv8i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v12, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v8, zero
+; RV64D-NEXT:    vnsrl.wi v12, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v12, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
   ret <vscale x 8 x i8> %a
 }

 ; RV32D-LABEL: cttz_zero_undef_nxv16i8:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vrsub.vi v10, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v10
 ; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
 ; RV32D-NEXT:    vzext.vf4 v16, v8
 ; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
-; RV32D-NEXT:    vsrl.vi v8, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v16, v8, zero
+; RV32D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV32D-NEXT:    vnsrl.wx v8, v16, zero
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv16i8:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
 ; RV64D-NEXT:    vzext.vf4 v16, v8
 ; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
-; RV64D-NEXT:    vsrl.vi v8, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v16, v8, zero
+; RV64D-NEXT:    vnsrl.wi v16, v8, 23
 ; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
 ; RV64D-NEXT:    vnsrl.wx v8, v16, zero
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
   ret <vscale x 16 x i8> %a
 }

 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_zero_undef_nxv1i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv1i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {

 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_zero_undef_nxv2i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v9, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v8, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV32D-NEXT:    li a0, 127
 ; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv2i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v9, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v8, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v9, 23
 ; RV64D-NEXT:    li a0, 127
 ; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {

 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_zero_undef_nxv4i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v9
 ; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v10, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV32D-NEXT:    vnsrl.wx v10, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV32D-NEXT:    li a0, 127
-; RV32D-NEXT:    vsub.vx v8, v10, a0
+; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv4i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
 ; RV64D-NEXT:    vrsub.vi v9, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v9
 ; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v10, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; RV64D-NEXT:    vnsrl.wx v10, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v10, 23
 ; RV64D-NEXT:    li a0, 127
-; RV64D-NEXT:    vsub.vx v8, v10, a0
+; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
 ; RV32I-LABEL: cttz_zero_undef_nxv8i16:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_zero_undef_nxv8i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV32D-NEXT:    vrsub.vi v10, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v10
 ; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v12, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV32D-NEXT:    vnsrl.wx v12, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV32D-NEXT:    li a0, 127
-; RV32D-NEXT:    vsub.vx v8, v12, a0
+; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv8i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
 ; RV64D-NEXT:    vrsub.vi v10, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v10
 ; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v12, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
-; RV64D-NEXT:    vnsrl.wx v12, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v12, 23
 ; RV64D-NEXT:    li a0, 127
-; RV64D-NEXT:    vsub.vx v8, v12, a0
+; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
 ; RV32I-LABEL: cttz_zero_undef_nxv16i16:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ret
 ;
 ; RV32D-LABEL: cttz_zero_undef_nxv16i16:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV32D-NEXT:    vrsub.vi v12, v8, 0
 ; RV32D-NEXT:    vand.vv v8, v8, v12
 ; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV32D-NEXT:    vsrl.vi v8, v16, 23
-; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV32D-NEXT:    vnsrl.wx v16, v8, zero
+; RV32D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV32D-NEXT:    li a0, 127
-; RV32D-NEXT:    vsub.vx v8, v16, a0
+; RV32D-NEXT:    vsub.vx v8, v8, a0
 ; RV32D-NEXT:    ret
 ;
 ; RV64D-LABEL: cttz_zero_undef_nxv16i16:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
 ; RV64D-NEXT:    vrsub.vi v12, v8, 0
 ; RV64D-NEXT:    vand.vv v8, v8, v12
 ; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
-; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
-; RV64D-NEXT:    vsrl.vi v8, v16, 23
-; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
-; RV64D-NEXT:    vnsrl.wx v16, v8, zero
+; RV64D-NEXT:    vnsrl.wi v8, v16, 23
 ; RV64D-NEXT:    li a0, 127
-; RV64D-NEXT:    vsub.vx v8, v16, a0
+; RV64D-NEXT:    vsub.vx v8, v8, a0
 ; RV64D-NEXT:    ret
   %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
 ; RV32-LABEL: cttz_zero_undef_nxv32i16:
 ; RV32:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
+define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv1i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsra.wi v8, v8, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = ashr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
 define <vscale x 2 x i32> @vnsra_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv2i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vnsra.wv v11, v8, v10
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = ashr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
+define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv2i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsra.wi v10, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = ashr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
 define <vscale x 4 x i32> @vnsra_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv4i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vnsra.wv v14, v8, v12
 ; CHECK-NEXT:    vmv.v.v v8, v14
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = ashr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
+define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv4i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsra.wi v12, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = ashr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
 define <vscale x 8 x i32> @vnsra_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv8i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vnsra.wv v20, v8, v16
 ; CHECK-NEXT:    vmv.v.v v8, v20
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = ashr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
+define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv8i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsra.wi v16, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = ashr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
 define <vscale x 1 x i32> @vnsra_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv1i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsra.wv v8, v8, v9
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vc
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = ashr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
+define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv1i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsra.wi v8, v8, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = ashr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
 define <vscale x 2 x i32> @vnsra_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv2i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vnsra.wv v11, v8, v10
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = ashr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
+define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv2i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsra.wi v10, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = ashr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
 define <vscale x 4 x i32> @vnsra_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv4i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vnsra.wv v14, v8, v12
 ; CHECK-NEXT:    vmv.v.v v8, v14
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = ashr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
+define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv4i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsra.wi v12, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = ashr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
 define <vscale x 8 x i32> @vnsra_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
 ; CHECK-LABEL: vnsra_wv_nxv8i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vnsra.wv v20, v8, v16
 ; CHECK-NEXT:    vmv.v.v v8, v20
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = ashr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
+
+define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vnsra_wi_i32_nxv8i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsra.wi v16, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = ashr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
+define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v8, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = lshr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
 define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv2i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v11, v8, v10
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = lshr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
+define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wi v10, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = lshr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
 define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv4i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v14, v8, v12
 ; CHECK-NEXT:    vmv.v.v v8, v14
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = lshr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
+define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v12, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = lshr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
 define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv8i32_sext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v20, v8, v16
 ; CHECK-NEXT:    vmv.v.v v8, v20
 ; CHECK-NEXT:    ret
   %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
+define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsrl.wi v16, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = lshr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}
+
 define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv1i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v8, v8, v9
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vc
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
   %x = lshr <vscale x 1 x i64> %va, %vb
   %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
   ret <vscale x 1 x i32> %y
 }
 
+define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v8, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+  %x = lshr <vscale x 1 x i64> %va, %vb
+  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %y
+}
+
 define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv2i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v11, v8, v10
 ; CHECK-NEXT:    vmv.v.v v8, v11
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
   %x = lshr <vscale x 2 x i64> %va, %vb
   %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
   ret <vscale x 2 x i32> %y
 }
 
+define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wi v10, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+  %x = lshr <vscale x 2 x i64> %va, %vb
+  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %y
+}
+
 define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv4i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v14, v8, v12
 ; CHECK-NEXT:    vmv.v.v v8, v14
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
   %x = lshr <vscale x 4 x i64> %va, %vb
   %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %y
 }
 
+define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v12, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+  %x = lshr <vscale x 4 x i64> %va, %vb
+  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %y
+}
+
 define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
 ; CHECK-LABEL: vnsrl_wv_nxv8i32_zext:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
 ; CHECK-NEXT:    vnsrl.wv v20, v8, v16
 ; CHECK-NEXT:    vmv.v.v v8, v20
 ; CHECK-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
+
+define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vnsrl.wi v16, v8, 15
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+  %x = lshr <vscale x 8 x i64> %va, %vb
+  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %y
+}