[AArch64] Use first op of FADDPv* instead of implicit def.

[fhahn]

Summary

This patch updates the FADDPv* patterns that only use the lower half of
the result register. For those patterns, the second operand does not
matter because its results won't be used.

Instead of introducing new implicit defs for those operands, just use
the first operand. The problem with using new implicit defs is that
register allocation can introduce unnecessary dependencies by using a
different register than the first operand.

For motivating cases, see the changes in the fadd_reduction_*_in_loop
cases. Without this change, the first faddp in the loop has an
unnecessary additional dependency through v0, which is also used for
a cross-iteration reduction.

This can noticeable impact performance. For slightly bigger loops,
this change can improve performance by 15%.

[t.p.northover]

Looks like a sensible change to me, but could you commit it with a small comment explaining? I think I remember puzzling over these patterns a little when someone asked about them, and with this change the actual dataflow we care about is even less apparent.

[fhahn]

In D120706#3350754, @t.p.northover wrote:

Looks like a sensible change to me, but could you commit it with a small comment explaining? I think I remember puzzling over these patterns a little when someone asked about them, and with this change the actual dataflow we care about is even less apparent.

Thanks Tim!

I added a comment in the latest update. It would be great if you could take a quick look to double-check if it is helpful.

[sdesmalen]

I've seen this in other places as well where introducing explicit implicit defs leads to less efficient register allocation, so I can see this is an improvement.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm FMAXP   : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">;
 defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">;
 defm FMINP   : SIMDFPPairwiseScalar<1, 0b01111, "fminp">;
 
 let Predicates = [HasFullFP16] in {
 def : Pat<(f16 (vecreduce_fadd (v8f16 V128:$Rn))),
             (FADDPv2i16p
               (EXTRACT_SUBREG
-                 (FADDPv8f16 (FADDPv8f16 V128:$Rn, (v8f16 (IMPLICIT_DEF))), (v8f16 (IMPLICIT_DEF))),
+                 (FADDPv8f16 (FADDPv8f16 V128:$Rn, V128:$Rn), V128:$Rn),
                dsub))>;
 def : Pat<(f16 (vecreduce_fadd (v4f16 V64:$Rn))),
-          (FADDPv2i16p (FADDPv4f16 V64:$Rn, (v4f16 (IMPLICIT_DEF))))>;
+          (FADDPv2i16p (FADDPv4f16 V64:$Rn, V64:$Rn))>;
 }
 def : Pat<(f32 (vecreduce_fadd (v4f32 V128:$Rn))),
           (FADDPv2i32p
             (EXTRACT_SUBREG
-              (FADDPv4f32 V128:$Rn, (v4f32 (IMPLICIT_DEF))),
+              (FADDPv4f32 V128:$Rn, V128:$Rn),
              dsub))>;
 def : Pat<(f32 (vecreduce_fadd (v2f32 V64:$Rn))),
           (FADDPv2i32p V64:$Rn)>;
 def : Pat<(f64 (vecreduce_fadd (v2f64 V128:$Rn))),
           (FADDPv2i64p V128:$Rn)>;
 
 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
           (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;

llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

; CHECKNOFP16-NEXT:    ret
   %r = call fast half @llvm.vector.reduce.fadd.f16.v4f16(half -0.0, <4 x half> %bin.rdx)
   ret half %r
 }
 
 
 define half @add_H(<8 x half> %bin.rdx)  {
 ; FULLFP16-LABEL: add_H:
 ; FULLFP16:       // %bb.0:
-; FULLFP16-NEXT:    faddp v0.8h, v0.8h, v0.8h
-; FULLFP16-NEXT:    faddp v0.8h, v0.8h, v0.8h
+; FULLFP16-NEXT:    faddp v1.8h, v0.8h, v0.8h
+; FULLFP16-NEXT:    faddp v0.8h, v1.8h, v0.8h
 ; FULLFP16-NEXT:    faddp h0, v0.2h
 ; FULLFP16-NEXT:    ret
 ;
 ; CHECKNOFP16-LABEL: add_H:
 ; CHECKNOFP16:       // %bb.0:
 ; CHECKNOFP16-NEXT:    mov h1, v0.h[1]
 ; CHECKNOFP16-NEXT:    fcvt s2, h0
 ; CHECKNOFP16-NEXT:    fcvt s1, h1
; CHECK-NEXT:    ret
   %r = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %bin.rdx)
   ret double %r
 }
 
 define half @add_2H(<16 x half> %bin.rdx)  {
 ; FULLFP16-LABEL: add_2H:
 ; FULLFP16:       // %bb.0:
 ; FULLFP16-NEXT:    fadd v0.8h, v0.8h, v1.8h
-; FULLFP16-NEXT:    faddp v0.8h, v0.8h, v0.8h
-; FULLFP16-NEXT:    faddp v0.8h, v0.8h, v0.8h
+; FULLFP16-NEXT:    faddp v1.8h, v0.8h, v0.8h
+; FULLFP16-NEXT:    faddp v0.8h, v1.8h, v0.8h
 ; FULLFP16-NEXT:    faddp h0, v0.2h
 ; FULLFP16-NEXT:    ret
 ;
 ; CHECKNOFP16-LABEL: add_2H:
 ; CHECKNOFP16:       // %bb.0:
 ; CHECKNOFP16-NEXT:    mov h2, v1.h[1]
 ; CHECKNOFP16-NEXT:    mov h3, v0.h[1]
 ; CHECKNOFP16-NEXT:    fcvt s4, h1

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    mov x8, xzr
 ; CHECK-NEXT:  .LBB9_1: // %loop
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldr q1, [x0, x8]
 ; CHECK-NEXT:    add x8, x8, #16
 ; CHECK-NEXT:    cmp w8, #112
-; CHECK-NEXT:    faddp v1.4s, v1.4s, v0.4s
+; CHECK-NEXT:    faddp v1.4s, v1.4s, v1.4s
 ; CHECK-NEXT:    faddp s1, v1.2s
 ; CHECK-NEXT:    fadd s0, s1, s0
 ; CHECK-NEXT:    b.ne .LBB9_1
 ; CHECK-NEXT:  // %bb.2: // %exit
 ; CHECK-NEXT:    ret
 entry:
   br label %loop
 

 ; FULLFP16:       // %bb.0: // %entry
 ; FULLFP16-NEXT:    movi d0, #0000000000000000
 ; FULLFP16-NEXT:    mov x8, xzr
 ; FULLFP16-NEXT:  .LBB10_1: // %loop
 ; FULLFP16-NEXT:    // =>This Inner Loop Header: Depth=1
 ; FULLFP16-NEXT:    ldr d1, [x0, x8]
 ; FULLFP16-NEXT:    add x8, x8, #8
 ; FULLFP16-NEXT:    cmp w8, #56
-; FULLFP16-NEXT:    faddp v1.4h, v1.4h, v0.4h
+; FULLFP16-NEXT:    faddp v1.4h, v1.4h, v1.4h
 ; FULLFP16-NEXT:    faddp h1, v1.2h
 ; FULLFP16-NEXT:    fadd h0, h1, h0
 ; FULLFP16-NEXT:    b.ne .LBB10_1
 ; FULLFP16-NEXT:  // %bb.2: // %exit
 ; FULLFP16-NEXT:    ret
 ;
 ; CHECKNOFP16-LABEL: fadd_reduction_v4f16_in_loop:
 ; CHECKNOFP16:       // %bb.0: // %entry

 ; FULLFP16:       // %bb.0: // %entry
 ; FULLFP16-NEXT:    movi d0, #0000000000000000
 ; FULLFP16-NEXT:    mov x8, xzr
 ; FULLFP16-NEXT:  .LBB11_1: // %loop
 ; FULLFP16-NEXT:    // =>This Inner Loop Header: Depth=1
 ; FULLFP16-NEXT:    ldr q1, [x0, x8]
 ; FULLFP16-NEXT:    add x8, x8, #8
 ; FULLFP16-NEXT:    cmp w8, #56
-; FULLFP16-NEXT:    faddp v1.8h, v1.8h, v0.8h
-; FULLFP16-NEXT:    faddp v1.8h, v1.8h, v0.8h
+; FULLFP16-NEXT:    faddp v2.8h, v1.8h, v1.8h
+; FULLFP16-NEXT:    faddp v1.8h, v2.8h, v1.8h
 ; FULLFP16-NEXT:    faddp h1, v1.2h
 ; FULLFP16-NEXT:    fadd h0, h1, h0
 ; FULLFP16-NEXT:    b.ne .LBB11_1
 ; FULLFP16-NEXT:  // %bb.2: // %exit
 ; FULLFP16-NEXT:    ret
 ;
 ; CHECKNOFP16-LABEL: fadd_reduction_v8f16_in_loop:
 ; CHECKNOFP16:       // %bb.0: // %entry