[AArch64] Add isel for bitcasting between bfloat and half types.

[mgabka]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

7549

shouldn't it be guarded by HasBF16 ?

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

7549

No, generally only instructions need to be guarded by feature flags. This mirrors how we handle bf16 patterns for SVE for things like bitcasts, loads, stores and shuffles because for each of those cases, how the bits are interpreted is not significant.

If it turns out that for some reason the bf16 type is not legal then these patterns will just get ignored.

[mgabka]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (isTypeLegal(OpVT) && !isTypeLegal(ArgVT)) {
       return getSVESafeBitCast(OpVT, ExtResult, DAG);
     }
     return getSVESafeBitCast(OpVT, Op.getOperand(0), DAG);
   }
 
   if (OpVT != MVT::f16 && OpVT != MVT::bf16)
     return SDValue();
 
+  // Bitcasts between f16 and bf16 are legal.
+  if (ArgVT == MVT::f16 || ArgVT == MVT::bf16)
+    return Op;
+
   assert(ArgVT == MVT::i16);
   SDLoc DL(Op);
 
   Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
   Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
   return SDValue(
       DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, OpVT, Op,
                          DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
           (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
           (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
           (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
           (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
 
+def : Pat<(f16 (bitconvert (bf16 FPR16:$src))), (f16 FPR16:$src)>;
+def : Pat<(bf16 (bitconvert (f16 FPR16:$src))), (bf16 FPR16:$src)>;
+
 let Predicates = [IsLE] in {
 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v8i8  FPR64:$src))), (v1i64 FPR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v4bf16 FPR64:$src))), (v1i64 FPR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
 }

llvm/test/CodeGen/AArch64/bf16.ll

; CHECK: str q0, [x0], #16
   store <8 x bfloat> %val, <8 x bfloat>* %ptr
   %res.tmp = insertvalue { <8 x bfloat>, <8 x bfloat>* } undef, <8 x bfloat> %val, 0
 
   %next = getelementptr <8 x bfloat>, <8 x bfloat>* %ptr, i32 1
   %res = insertvalue { <8 x bfloat>, <8 x bfloat>* } %res.tmp, <8 x bfloat>* %next, 1
 
   ret { <8 x bfloat>, <8 x bfloat>* } %res
 }
+
+define bfloat @test_bitcast_halftobfloat(half %a) nounwind {
+; CHECK-LABEL: test_bitcast_halftobfloat:
+; CHECK-NEXT: ret
+  %r = bitcast half %a to bfloat
+  ret bfloat %r
+}
+
+define half @test_bitcast_bfloattohalf(bfloat %a) nounwind {
+; CHECK-LABEL: test_bitcast_bfloattohalf:
+; CHECK-NEXT: ret
+  %r = bitcast bfloat %a to half
+  ret half %r
+}