[Spill2Reg][8/9] Added code generation support for 8/16bit spills/reloads in x86

[craig.topper]

llvm/test/CodeGen/X86/spill2reg_end_to_end_8bit.ll

70

This code looks invalid. movb can't have a %eax destination

[vporpo]

llvm/test/CodeGen/X86/spill2reg_end_to_end_8bit.ll

70

Yes, this patch needs more work. I need to update it.

[vporpo]

Refactored the patch and fixed illegal instructions.

[craig.topper]

llvm/lib/Target/X86/X86InstrInfo.cpp

9588

Should use the AVX or AVX512 opcodes when available?

Are you limiting to VR128 regclass or do you allow VR128X with AVX512?

llvm/test/CodeGen/X86/spill2reg_end_to_end_16bit.ll

70–71

Why is X86FixupBWInsts.cpp failing to convert this load to movzwl?

[vporpo]

llvm/lib/Target/X86/X86InstrInfo.cpp

9588

I am trying to avoid the frequency throttling associated with using wide vector instructions. But I guess AVX should be safe ? Not sure about AVX512 though, won't it cause frequency drops if I use that instead?
I am currently using VR128.

llvm/test/CodeGen/X86/spill2reg_end_to_end_16bit.ll

70–71

XF86FixupBWInsts.cpp:208 checks whether the super reg %eax is live after movw D0(%rip), %ax. In the original code it is not live, but in our case it is because movd is reading from %eax. So it bails and does not replace the register.
Hmm not sure how we could fix this though.

[vporpo]

Removed the subregs from the movd instructions.
Also added simple mir tests for 8/16 bits.

[vporpo]

Updated tests.

[vporpo]

Rebased.