Differential D118951

[Spill2Reg][9/9] Using AVX opcodes when available.
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Authored by vporpo on Feb 3 2022, 3:14 PM.

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Reviewers: None

Summary

This patch updates the vector spill/reload instructions to use the AVX
opcodes by default if the targets supports it. This can be turned off
with the -spill2reg-no-avx flag.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

vporpo created this revision.Feb 3 2022, 3:14 PM

Herald added subscribers: pengfei, hiraditya, qcolombet. · View Herald TranscriptFeb 3 2022, 3:14 PM

vporpo requested review of this revision.Feb 3 2022, 3:14 PM

Herald added a project: Restricted Project. · View Herald TranscriptFeb 3 2022, 3:14 PM

Herald added a subscriber: llvm-commits. · View Herald Transcript

vporpo added a parent revision: D118305: [Spill2Reg][8/9] Added code generation support for 8/16bit spills/reloads in x86.Feb 3 2022, 3:14 PM

Harbormaster completed remote builds in B147520: Diff 405816.Feb 3 2022, 3:15 PM

vporpo retitled this revision from [Spill2Reg] Using AVX opcodes when available. to [Spill2Reg][9/9] Using AVX opcodes when available..Feb 4 2022, 9:51 AM

Revision Contents
Changeset List

Path

Size

llvm/

include/

llvm/

CodeGen/

TargetInstrInfo.h

21 lines

lib/

CodeGen/

7 lines

Target/

X86/

9 lines

X86InstrInfo.cpp

40 lines

test/

CodeGen/

X86/

spill2reg_end_to_end_16bit.ll

85 lines

spill2reg_end_to_end_32bit.ll

85 lines

spill2reg_end_to_end_64bit.ll

85 lines

spill2reg_end_to_end_8bit.ll

85 lines

spill2reg_simple_1_16bit.mir

7 lines

spill2reg_simple_1_32bit.mir

8 lines

spill2reg_simple_1_64bit.mir

14 lines

spill2reg_simple_1_8bit.mir

7 lines

Diff 405816

llvm/include/llvm/CodeGen/TargetInstrInfo.h

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llvm/lib/CodeGen/Spill2Reg.cpp

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llvm/lib/Target/X86/X86InstrInfo.h

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llvm/lib/Target/X86/X86InstrInfo.cpp

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llvm/test/CodeGen/X86/spill2reg_end_to_end_16bit.ll

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llvm/test/CodeGen/X86/spill2reg_end_to_end_32bit.ll

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llvm/test/CodeGen/X86/spill2reg_end_to_end_64bit.ll

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llvm/test/CodeGen/X86/spill2reg_end_to_end_8bit.ll

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llvm/test/CodeGen/X86/spill2reg_simple_1_16bit.mir

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llvm/test/CodeGen/X86/spill2reg_simple_1_32bit.mir

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llvm/test/CodeGen/X86/spill2reg_simple_1_64bit.mir

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llvm/test/CodeGen/X86/spill2reg_simple_1_8bit.mir

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