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[Spill2Reg][3/9] Code generation part 1.
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Authored by vporpo on Jan 26 2022, 5:44 PM.

Details

Reviewers
Carrot
arsenm
Summary

This adds the main structure of the code generation phase of Spill2Reg.
Iterate through the spills/reloads collected earlier and generate the
new instructions.

Diff Detail

Event Timeline

vporpo created this revision.Jan 26 2022, 5:44 PM
vporpo requested review of this revision.Jan 26 2022, 5:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 26 2022, 5:44 PM
wxiao3 added a subscriber: wxiao3.Jan 26 2022, 7:18 PM
vporpo retitled this revision from [Spill2Reg] Code generation part 1. to [Spill2Reg][3/9] Code generation part 1..Feb 4 2022, 9:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptThu, Jun 16, 11:57 AM
Herald added a subscriber: jsji. · View Herald Transcript
Carrot added inline comments.Fri, Jun 17, 11:36 AM
llvm/include/llvm/CodeGen/TargetInstrInfo.h
2029

For different sized registers we may spill to different vector register class. For example on ARM with NEON, 32 bit value can be spilled to S registers, 64 bit value can be spilled to D registers.

2032

Other functions use ! instead of ().

vporpo marked an inline comment as done.Fri, Jun 17, 2:12 PM
vporpo added inline comments.
llvm/include/llvm/CodeGen/TargetInstrInfo.h
2029

I added an additional argument to this function to pass the hard register being spilled, such that each target can decide which vector register class to use.

vporpo updated this revision to Diff 438033.Fri, Jun 17, 2:13 PM

Addressed comments.