This adds the main structure of the code generation phase of Spill2Reg.
Iterate through the spills/reloads collected earlier and generate the
new instructions.
Details
Details
Diff Detail
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
llvm/include/llvm/CodeGen/TargetInstrInfo.h | ||
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2029 | I added an additional argument to this function to pass the hard register being spilled, such that each target can decide which vector register class to use. |
For different sized registers we may spill to different vector register class. For example on ARM with NEON, 32 bit value can be spilled to S registers, 64 bit value can be spilled to D registers.