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Differential D118295

[RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.
ClosedPublic

Authored by craig.topper on Jan 26 2022, 4:40 PM.

Details

Reviewers
rogfer01
frasercrmck
khchen
eopXD
arcbbb
kito-cheng
Commits
rGb3bec6e4530b: [RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.
Summary

This matches what the spec uses for the vncvt.x.x.w assembly
pseudoinstruction.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 26 2022, 4:40 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald TranscriptJan 26 2022, 4:40 PM
craig.topper requested review of this revision.Jan 26 2022, 4:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 26 2022, 4:40 PM
Herald added subscribers: • pcwang-thead, MaskRay. · View Herald Transcript
kito-cheng accepted this revision.Jan 26 2022, 5:50 PM

LGTM

This revision is now accepted and ready to land.Jan 26 2022, 5:50 PM
This revision was landed with ongoing or failed builds.Jan 26 2022, 6:38 PM
Closed by commit rGb3bec6e4530b: [RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGb3bec6e4530b: [RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate..
Harbormaster completed remote builds in B145874: Diff 403439.Jan 27 2022, 7:00 AM

Revision Contents

Diff 403463

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

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defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">; defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">;
foreach vtiTowti = AllWidenableIntVectors in { foreach vtiTowti = AllWidenableIntVectors in {
defvar vti = vtiTowti.Vti; defvar vti = vtiTowti.Vti;
defvar wti = vtiTowti.Wti; defvar wti = vtiTowti.Wti;
def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX)
wti.RegClass:$rs1, 0, GPR:$vl, vti.Log2SEW)>; wti.RegClass:$rs1, X0, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector def : Pat<(vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(wti.Vector (wti.Vector
(riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), (riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2),
true_mask, VLOpFrag)), true_mask, VLOpFrag)), true_mask, VLOpFrag)), true_mask, VLOpFrag)),
(!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX) (!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX)
wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
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llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

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define <2 x i16> @fixedlen(<2 x i32> %x) { define <2 x i16> @fixedlen(<2 x i32> %x) {
; RV32-LABEL: fixedlen: ; RV32-LABEL: fixedlen:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vsrl.vi v8, v8, 16 ; RV32-NEXT: vsrl.vi v8, v8, 16
; RV32-NEXT: lui a0, 1048568 ; RV32-NEXT: lui a0, 1048568
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fixedlen: ; RV64-LABEL: fixedlen:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vsrl.vi v8, v8, 16 ; RV64-NEXT: vsrl.vi v8, v8, 16
; RV64-NEXT: lui a0, 131071 ; RV64-NEXT: lui a0, 131071
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: ret ; RV64-NEXT: ret
%v41 = insertelement <2 x i32> undef, i32 16, i32 0 %v41 = insertelement <2 x i32> undef, i32 16, i32 0
%v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer %v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer
%v43 = lshr <2 x i32> %x, %v42 %v43 = lshr <2 x i32> %x, %v42
%v44 = trunc <2 x i32> %v43 to <2 x i16> %v44 = trunc <2 x i32> %v43 to <2 x i16>
%v45 = insertelement <2 x i32> undef, i32 -32768, i32 0 %v45 = insertelement <2 x i32> undef, i32 -32768, i32 0
%v46 = shufflevector <2 x i32> %v45, <2 x i32> undef, <2 x i32> zeroinitializer %v46 = shufflevector <2 x i32> %v45, <2 x i32> undef, <2 x i32> zeroinitializer
%v47 = trunc <2 x i32> %v46 to <2 x i16> %v47 = trunc <2 x i32> %v46 to <2 x i16>
%v48 = and <2 x i16> %v44, %v47 %v48 = and <2 x i16> %v44, %v47
ret <2 x i16> %v48 ret <2 x i16> %v48
} }
define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) { define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) {
; CHECK-LABEL: scalable: ; CHECK-LABEL: scalable:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vsrl.vi v8, v8, 16 ; CHECK-NEXT: vsrl.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v41 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0 %v41 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
%v42 = shufflevector <vscale x 2 x i32> %v41, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer %v42 = shufflevector <vscale x 2 x i32> %v41, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%v43 = lshr <vscale x 2 x i32> %x, %v42 %v43 = lshr <vscale x 2 x i32> %x, %v42
%v44 = trunc <vscale x 2 x i32> %v43 to <vscale x 2 x i16> %v44 = trunc <vscale x 2 x i32> %v43 to <vscale x 2 x i16>
%v45 = insertelement <vscale x 2 x i32> undef, i32 -32768, i32 0 %v45 = insertelement <vscale x 2 x i32> undef, i32 -32768, i32 0
%v46 = shufflevector <vscale x 2 x i32> %v45, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer %v46 = shufflevector <vscale x 2 x i32> %v45, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%v47 = trunc <vscale x 2 x i32> %v46 to <vscale x 2 x i16> %v47 = trunc <vscale x 2 x i32> %v46 to <vscale x 2 x i16>
%v48 = and <vscale x 2 x i16> %v44, %v47 %v48 = and <vscale x 2 x i16> %v44, %v47
ret <vscale x 2 x i16> %v48 ret <vscale x 2 x i16> %v48
} }

llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll

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; ;
; RV32D-LABEL: ctlz_nxv1i8: ; RV32D-LABEL: ctlz_nxv1i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v9, v9 ; RV32D-NEXT: vfcvt.f.xu.v v9, v9
; RV32D-NEXT: vsrl.vi v9, v9, 23 ; RV32D-NEXT: vsrl.vi v9, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vrsub.vx v8, v9, a0 ; RV32D-NEXT: vrsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv1i8: ; RV64D-LABEL: ctlz_nxv1i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v9, v9 ; RV64D-NEXT: vfcvt.f.xu.v v9, v9
; RV64D-NEXT: vsrl.vi v9, v9, 23 ; RV64D-NEXT: vsrl.vi v9, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vrsub.vx v8, v9, a0 ; RV64D-NEXT: vrsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false) %a = call <vscale x 1 x i8> @llvm.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
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; ;
; RV32D-LABEL: ctlz_nxv2i8: ; RV32D-LABEL: ctlz_nxv2i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v9, v9 ; RV32D-NEXT: vfcvt.f.xu.v v9, v9
; RV32D-NEXT: vsrl.vi v9, v9, 23 ; RV32D-NEXT: vsrl.vi v9, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vrsub.vx v8, v9, a0 ; RV32D-NEXT: vrsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv2i8: ; RV64D-LABEL: ctlz_nxv2i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v9, v9 ; RV64D-NEXT: vfcvt.f.xu.v v9, v9
; RV64D-NEXT: vsrl.vi v9, v9, 23 ; RV64D-NEXT: vsrl.vi v9, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vrsub.vx v8, v9, a0 ; RV64D-NEXT: vrsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false) %a = call <vscale x 2 x i8> @llvm.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
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; ;
; RV32D-LABEL: ctlz_nxv4i8: ; RV32D-LABEL: ctlz_nxv4i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32D-NEXT: vzext.vf4 v10, v8 ; RV32D-NEXT: vzext.vf4 v10, v8
; RV32D-NEXT: vfcvt.f.xu.v v10, v10 ; RV32D-NEXT: vfcvt.f.xu.v v10, v10
; RV32D-NEXT: vsrl.vi v10, v10, 23 ; RV32D-NEXT: vsrl.vi v10, v10, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v10, 0 ; RV32D-NEXT: vnsrl.wx v9, v10, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vrsub.vx v8, v9, a0 ; RV32D-NEXT: vrsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv4i8: ; RV64D-LABEL: ctlz_nxv4i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vzext.vf4 v10, v8 ; RV64D-NEXT: vzext.vf4 v10, v8
; RV64D-NEXT: vfcvt.f.xu.v v10, v10 ; RV64D-NEXT: vfcvt.f.xu.v v10, v10
; RV64D-NEXT: vsrl.vi v10, v10, 23 ; RV64D-NEXT: vsrl.vi v10, v10, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v10, 0 ; RV64D-NEXT: vnsrl.wx v9, v10, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vrsub.vx v8, v9, a0 ; RV64D-NEXT: vrsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false) %a = call <vscale x 4 x i8> @llvm.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
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; ;
; RV32D-LABEL: ctlz_nxv8i8: ; RV32D-LABEL: ctlz_nxv8i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV32D-NEXT: vzext.vf4 v12, v8 ; RV32D-NEXT: vzext.vf4 v12, v8
; RV32D-NEXT: vfcvt.f.xu.v v12, v12 ; RV32D-NEXT: vfcvt.f.xu.v v12, v12
; RV32D-NEXT: vsrl.vi v12, v12, 23 ; RV32D-NEXT: vsrl.vi v12, v12, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v12, 0 ; RV32D-NEXT: vnsrl.wx v10, v12, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v10, 0 ; RV32D-NEXT: vnsrl.wx v9, v10, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vrsub.vx v8, v9, a0 ; RV32D-NEXT: vrsub.vx v8, v9, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv8i8: ; RV64D-LABEL: ctlz_nxv8i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vzext.vf4 v12, v8 ; RV64D-NEXT: vzext.vf4 v12, v8
; RV64D-NEXT: vfcvt.f.xu.v v12, v12 ; RV64D-NEXT: vfcvt.f.xu.v v12, v12
; RV64D-NEXT: vsrl.vi v12, v12, 23 ; RV64D-NEXT: vsrl.vi v12, v12, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v12, 0 ; RV64D-NEXT: vnsrl.wx v10, v12, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v10, 0 ; RV64D-NEXT: vnsrl.wx v9, v10, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vrsub.vx v8, v9, a0 ; RV64D-NEXT: vrsub.vx v8, v9, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false) %a = call <vscale x 8 x i8> @llvm.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
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; ;
; RV32D-LABEL: ctlz_nxv16i8: ; RV32D-LABEL: ctlz_nxv16i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV32D-NEXT: vzext.vf4 v16, v8 ; RV32D-NEXT: vzext.vf4 v16, v8
; RV32D-NEXT: vfcvt.f.xu.v v16, v16 ; RV32D-NEXT: vfcvt.f.xu.v v16, v16
; RV32D-NEXT: vsrl.vi v16, v16, 23 ; RV32D-NEXT: vsrl.vi v16, v16, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v16, 0 ; RV32D-NEXT: vnsrl.wx v12, v16, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v12, 0 ; RV32D-NEXT: vnsrl.wx v10, v12, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: vrsub.vx v8, v10, a0 ; RV32D-NEXT: vrsub.vx v8, v10, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv16i8: ; RV64D-LABEL: ctlz_nxv16i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV64D-NEXT: vzext.vf4 v16, v8 ; RV64D-NEXT: vzext.vf4 v16, v8
; RV64D-NEXT: vfcvt.f.xu.v v16, v16 ; RV64D-NEXT: vfcvt.f.xu.v v16, v16
; RV64D-NEXT: vsrl.vi v16, v16, 23 ; RV64D-NEXT: vsrl.vi v16, v16, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v16, 0 ; RV64D-NEXT: vnsrl.wx v12, v16, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v12, 0 ; RV64D-NEXT: vnsrl.wx v10, v12, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: vrsub.vx v8, v10, a0 ; RV64D-NEXT: vrsub.vx v8, v10, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false) %a = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
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; ;
; RV32D-LABEL: ctlz_nxv1i16: ; RV32D-LABEL: ctlz_nxv1i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vsrl.vi v9, v9, 23 ; RV32D-NEXT: vsrl.vi v9, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v9, v9, a0 ; RV32D-NEXT: vrsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv1i16: ; RV64D-LABEL: ctlz_nxv1i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vsrl.vi v9, v9, 23 ; RV64D-NEXT: vsrl.vi v9, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v9, v9, a0 ; RV64D-NEXT: vrsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false) %a = call <vscale x 1 x i16> @llvm.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
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; ;
; RV32D-LABEL: ctlz_nxv2i16: ; RV32D-LABEL: ctlz_nxv2i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vsrl.vi v9, v9, 23 ; RV32D-NEXT: vsrl.vi v9, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v9, v9, a0 ; RV32D-NEXT: vrsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv2i16: ; RV64D-LABEL: ctlz_nxv2i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vsrl.vi v9, v9, 23 ; RV64D-NEXT: vsrl.vi v9, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v9, v9, a0 ; RV64D-NEXT: vrsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false) %a = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
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; ;
; RV32D-LABEL: ctlz_nxv4i16: ; RV32D-LABEL: ctlz_nxv4i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vsrl.vi v10, v10, 23 ; RV32D-NEXT: vsrl.vi v10, v10, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v10, 0 ; RV32D-NEXT: vnsrl.wx v9, v10, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v9, v9, a0 ; RV32D-NEXT: vrsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv4i16: ; RV64D-LABEL: ctlz_nxv4i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vsrl.vi v10, v10, 23 ; RV64D-NEXT: vsrl.vi v10, v10, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v10, 0 ; RV64D-NEXT: vnsrl.wx v9, v10, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v9, v9, a0 ; RV64D-NEXT: vrsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false) %a = call <vscale x 4 x i16> @llvm.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
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; ;
; RV32D-LABEL: ctlz_nxv8i16: ; RV32D-LABEL: ctlz_nxv8i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vsrl.vi v12, v12, 23 ; RV32D-NEXT: vsrl.vi v12, v12, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v12, 0 ; RV32D-NEXT: vnsrl.wx v10, v12, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v10, v10, a0 ; RV32D-NEXT: vrsub.vx v10, v10, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv8i16: ; RV64D-LABEL: ctlz_nxv8i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vsrl.vi v12, v12, 23 ; RV64D-NEXT: vsrl.vi v12, v12, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v12, 0 ; RV64D-NEXT: vnsrl.wx v10, v12, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v10, v10, a0 ; RV64D-NEXT: vrsub.vx v10, v10, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v10, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false) %a = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
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; ;
; RV32D-LABEL: ctlz_nxv16i16: ; RV32D-LABEL: ctlz_nxv16i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vsrl.vi v16, v16, 23 ; RV32D-NEXT: vsrl.vi v16, v16, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v16, 0 ; RV32D-NEXT: vnsrl.wx v12, v16, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v12, v12, a0 ; RV32D-NEXT: vrsub.vx v12, v12, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv16i16: ; RV64D-LABEL: ctlz_nxv16i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vsrl.vi v16, v16, 23 ; RV64D-NEXT: vsrl.vi v16, v16, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v16, 0 ; RV64D-NEXT: vnsrl.wx v12, v16, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v12, v12, a0 ; RV64D-NEXT: vrsub.vx v12, v12, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v12, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false) %a = call <vscale x 16 x i16> @llvm.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
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; RV32D-LABEL: ctlz_nxv1i32: ; RV32D-LABEL: ctlz_nxv1i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32D-NEXT: vsrl.vx v9, v9, a0 ; RV32D-NEXT: vsrl.vx v9, v9, a0
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v9, v9, a0 ; RV32D-NEXT: vrsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv1i32: ; RV64D-LABEL: ctlz_nxv1i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64D-NEXT: vsrl.vx v9, v9, a0 ; RV64D-NEXT: vsrl.vx v9, v9, a0
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v9, 0 ; RV64D-NEXT: vnsrl.wx v9, v9, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v9, v9, a0 ; RV64D-NEXT: vrsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 false) %a = call <vscale x 1 x i32> @llvm.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
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; RV32D-LABEL: ctlz_nxv2i32: ; RV32D-LABEL: ctlz_nxv2i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32D-NEXT: vsrl.vx v10, v10, a0 ; RV32D-NEXT: vsrl.vx v10, v10, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v10, 0 ; RV32D-NEXT: vnsrl.wx v9, v10, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v9, v9, a0 ; RV32D-NEXT: vrsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv2i32: ; RV64D-LABEL: ctlz_nxv2i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64D-NEXT: vsrl.vx v10, v10, a0 ; RV64D-NEXT: vsrl.vx v10, v10, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v9, v10, 0 ; RV64D-NEXT: vnsrl.wx v9, v10, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v9, v9, a0 ; RV64D-NEXT: vrsub.vx v9, v9, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 false) %a = call <vscale x 2 x i32> @llvm.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
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; RV32D-LABEL: ctlz_nxv4i32: ; RV32D-LABEL: ctlz_nxv4i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32D-NEXT: vsrl.vx v12, v12, a0 ; RV32D-NEXT: vsrl.vx v12, v12, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v12, 0 ; RV32D-NEXT: vnsrl.wx v10, v12, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v10, v10, a0 ; RV32D-NEXT: vrsub.vx v10, v10, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv4i32: ; RV64D-LABEL: ctlz_nxv4i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64D-NEXT: vsrl.vx v12, v12, a0 ; RV64D-NEXT: vsrl.vx v12, v12, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v12, 0 ; RV64D-NEXT: vnsrl.wx v10, v12, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v10, v10, a0 ; RV64D-NEXT: vrsub.vx v10, v10, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v10, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 false) %a = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
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; RV32D-LABEL: ctlz_nxv8i32: ; RV32D-LABEL: ctlz_nxv8i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32D-NEXT: vsrl.vx v16, v16, a0 ; RV32D-NEXT: vsrl.vx v16, v16, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v16, 0 ; RV32D-NEXT: vnsrl.wx v12, v16, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v12, v12, a0 ; RV32D-NEXT: vrsub.vx v12, v12, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_nxv8i32: ; RV64D-LABEL: ctlz_nxv8i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64D-NEXT: vsrl.vx v16, v16, a0 ; RV64D-NEXT: vsrl.vx v16, v16, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v16, 0 ; RV64D-NEXT: vnsrl.wx v12, v16, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v12, v12, a0 ; RV64D-NEXT: vrsub.vx v12, v12, a0
; RV64D-NEXT: vmseq.vi v0, v8, 0 ; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v12, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 false) %a = call <vscale x 8 x i32> @llvm.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv1i8: ; RV32D-LABEL: ctlz_zero_undef_nxv1i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v9
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv1i8: ; RV64D-LABEL: ctlz_zero_undef_nxv1i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v8, v9
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true) %a = call <vscale x 1 x i8> @llvm.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) { define <vscale x 2 x i8> @ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv2i8: ; RV32D-LABEL: ctlz_zero_undef_nxv2i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v9
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv2i8: ; RV64D-LABEL: ctlz_zero_undef_nxv2i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v8, v9
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true) %a = call <vscale x 2 x i8> @llvm.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) { define <vscale x 4 x i8> @ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv4i8: ; RV32D-LABEL: ctlz_zero_undef_nxv4i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32D-NEXT: vzext.vf4 v10, v8 ; RV32D-NEXT: vzext.vf4 v10, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v10 ; RV32D-NEXT: vfcvt.f.xu.v v8, v10
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v10, 0 ; RV32D-NEXT: vnsrl.wx v8, v10, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv4i8: ; RV64D-LABEL: ctlz_zero_undef_nxv4i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vzext.vf4 v10, v8 ; RV64D-NEXT: vzext.vf4 v10, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v10 ; RV64D-NEXT: vfcvt.f.xu.v v8, v10
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v10, 0 ; RV64D-NEXT: vnsrl.wx v8, v10, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true) %a = call <vscale x 4 x i8> @llvm.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) { define <vscale x 8 x i8> @ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv8i8: ; RV32D-LABEL: ctlz_zero_undef_nxv8i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV32D-NEXT: vzext.vf4 v12, v8 ; RV32D-NEXT: vzext.vf4 v12, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v12 ; RV32D-NEXT: vfcvt.f.xu.v v8, v12
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v12, 0 ; RV32D-NEXT: vnsrl.wx v8, v12, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv8i8: ; RV64D-LABEL: ctlz_zero_undef_nxv8i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vzext.vf4 v12, v8 ; RV64D-NEXT: vzext.vf4 v12, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v12 ; RV64D-NEXT: vfcvt.f.xu.v v8, v12
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v12, 0 ; RV64D-NEXT: vnsrl.wx v8, v12, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true) %a = call <vscale x 8 x i8> @llvm.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) { define <vscale x 16 x i8> @ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv16i8: ; RV32D-LABEL: ctlz_zero_undef_nxv16i8:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV32D-NEXT: vzext.vf4 v16, v8 ; RV32D-NEXT: vzext.vf4 v16, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v16 ; RV32D-NEXT: vfcvt.f.xu.v v8, v16
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v16, 0 ; RV32D-NEXT: vnsrl.wx v8, v16, zero
; RV32D-NEXT: li a0, 134 ; RV32D-NEXT: li a0, 134
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv16i8: ; RV64D-LABEL: ctlz_zero_undef_nxv16i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV64D-NEXT: vzext.vf4 v16, v8 ; RV64D-NEXT: vzext.vf4 v16, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v16 ; RV64D-NEXT: vfcvt.f.xu.v v8, v16
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v16, 0 ; RV64D-NEXT: vnsrl.wx v8, v16, zero
; RV64D-NEXT: li a0, 134 ; RV64D-NEXT: li a0, 134
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true) %a = call <vscale x 16 x i8> @llvm.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) { define <vscale x 32 x i8> @ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv1i16: ; RV32D-LABEL: ctlz_zero_undef_nxv1i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vsrl.vi v8, v9, 23 ; RV32D-NEXT: vsrl.vi v8, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv1i16: ; RV64D-LABEL: ctlz_zero_undef_nxv1i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vsrl.vi v8, v9, 23 ; RV64D-NEXT: vsrl.vi v8, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true) %a = call <vscale x 1 x i16> @llvm.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) { define <vscale x 2 x i16> @ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv2i16: ; RV32D-LABEL: ctlz_zero_undef_nxv2i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vsrl.vi v8, v9, 23 ; RV32D-NEXT: vsrl.vi v8, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv2i16: ; RV64D-LABEL: ctlz_zero_undef_nxv2i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vsrl.vi v8, v9, 23 ; RV64D-NEXT: vsrl.vi v8, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true) %a = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) { define <vscale x 4 x i16> @ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv4i16: ; RV32D-LABEL: ctlz_zero_undef_nxv4i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vsrl.vi v8, v10, 23 ; RV32D-NEXT: vsrl.vi v8, v10, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v8, v10, a0 ; RV32D-NEXT: vrsub.vx v8, v10, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv4i16: ; RV64D-LABEL: ctlz_zero_undef_nxv4i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vsrl.vi v8, v10, 23 ; RV64D-NEXT: vsrl.vi v8, v10, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v8, v10, a0 ; RV64D-NEXT: vrsub.vx v8, v10, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true) %a = call <vscale x 4 x i16> @llvm.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) { define <vscale x 8 x i16> @ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv8i16: ; RV32D-LABEL: ctlz_zero_undef_nxv8i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vsrl.vi v8, v12, 23 ; RV32D-NEXT: vsrl.vi v8, v12, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v8, v12, a0 ; RV32D-NEXT: vrsub.vx v8, v12, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv8i16: ; RV64D-LABEL: ctlz_zero_undef_nxv8i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vsrl.vi v8, v12, 23 ; RV64D-NEXT: vsrl.vi v8, v12, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v8, v12, a0 ; RV64D-NEXT: vrsub.vx v8, v12, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true) %a = call <vscale x 8 x i16> @llvm.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) { define <vscale x 16 x i16> @ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
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; ;
; RV32D-LABEL: ctlz_zero_undef_nxv16i16: ; RV32D-LABEL: ctlz_zero_undef_nxv16i16:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vsrl.vi v8, v16, 23 ; RV32D-NEXT: vsrl.vi v8, v16, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: li a0, 142 ; RV32D-NEXT: li a0, 142
; RV32D-NEXT: vrsub.vx v8, v16, a0 ; RV32D-NEXT: vrsub.vx v8, v16, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv16i16: ; RV64D-LABEL: ctlz_zero_undef_nxv16i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vsrl.vi v8, v16, 23 ; RV64D-NEXT: vsrl.vi v8, v16, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: li a0, 142 ; RV64D-NEXT: li a0, 142
; RV64D-NEXT: vrsub.vx v8, v16, a0 ; RV64D-NEXT: vrsub.vx v8, v16, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true) %a = call <vscale x 16 x i16> @llvm.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) { define <vscale x 32 x i16> @ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
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; RV32D-LABEL: ctlz_zero_undef_nxv1i32: ; RV32D-LABEL: ctlz_zero_undef_nxv1i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32D-NEXT: vsrl.vx v8, v9, a0 ; RV32D-NEXT: vsrl.vx v8, v9, a0
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v8, v8, a0 ; RV32D-NEXT: vrsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv1i32: ; RV64D-LABEL: ctlz_zero_undef_nxv1i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64D-NEXT: vsrl.vx v8, v9, a0 ; RV64D-NEXT: vsrl.vx v8, v9, a0
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v8, v8, a0 ; RV64D-NEXT: vrsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 true) %a = call <vscale x 1 x i32> @llvm.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) { define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
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; RV32D-LABEL: ctlz_zero_undef_nxv2i32: ; RV32D-LABEL: ctlz_zero_undef_nxv2i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32D-NEXT: vsrl.vx v8, v10, a0 ; RV32D-NEXT: vsrl.vx v8, v10, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v8, v10, a0 ; RV32D-NEXT: vrsub.vx v8, v10, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv2i32: ; RV64D-LABEL: ctlz_zero_undef_nxv2i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64D-NEXT: vsrl.vx v8, v10, a0 ; RV64D-NEXT: vsrl.vx v8, v10, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v8, v10, a0 ; RV64D-NEXT: vrsub.vx v8, v10, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 true) %a = call <vscale x 2 x i32> @llvm.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) { define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
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; RV32D-LABEL: ctlz_zero_undef_nxv4i32: ; RV32D-LABEL: ctlz_zero_undef_nxv4i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32D-NEXT: vsrl.vx v8, v12, a0 ; RV32D-NEXT: vsrl.vx v8, v12, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v8, v12, a0 ; RV32D-NEXT: vrsub.vx v8, v12, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv4i32: ; RV64D-LABEL: ctlz_zero_undef_nxv4i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64D-NEXT: vsrl.vx v8, v12, a0 ; RV64D-NEXT: vsrl.vx v8, v12, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v8, v12, a0 ; RV64D-NEXT: vrsub.vx v8, v12, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 true) %a = call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) { define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
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; RV32D-LABEL: ctlz_zero_undef_nxv8i32: ; RV32D-LABEL: ctlz_zero_undef_nxv8i32:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32D-NEXT: vsrl.vx v8, v16, a0 ; RV32D-NEXT: vsrl.vx v8, v16, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: li a0, 1054 ; RV32D-NEXT: li a0, 1054
; RV32D-NEXT: vrsub.vx v8, v16, a0 ; RV32D-NEXT: vrsub.vx v8, v16, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: ctlz_zero_undef_nxv8i32: ; RV64D-LABEL: ctlz_zero_undef_nxv8i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64D-NEXT: vsrl.vx v8, v16, a0 ; RV64D-NEXT: vsrl.vx v8, v16, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: li a0, 1054 ; RV64D-NEXT: li a0, 1054
; RV64D-NEXT: vrsub.vx v8, v16, a0 ; RV64D-NEXT: vrsub.vx v8, v16, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 true) %a = call <vscale x 8 x i32> @llvm.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) { define <vscale x 16 x i32> @ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
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llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

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; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v9
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i8: ; RV64D-LABEL: cttz_nxv1i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v8, v9
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false) %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1) declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
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; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v9
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i8: ; RV64D-LABEL: cttz_nxv2i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v8, v9
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false) %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1) declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
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; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vzext.vf4 v10, v8 ; RV32D-NEXT: vzext.vf4 v10, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v10 ; RV32D-NEXT: vfcvt.f.xu.v v8, v10
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v10, 0 ; RV32D-NEXT: vnsrl.wx v8, v10, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i8: ; RV64D-LABEL: cttz_nxv4i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vzext.vf4 v10, v8 ; RV64D-NEXT: vzext.vf4 v10, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v10 ; RV64D-NEXT: vfcvt.f.xu.v v8, v10
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v10, 0 ; RV64D-NEXT: vnsrl.wx v8, v10, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false) %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1) declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
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; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vzext.vf4 v12, v8 ; RV32D-NEXT: vzext.vf4 v12, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v12 ; RV32D-NEXT: vfcvt.f.xu.v v8, v12
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v12, 0 ; RV32D-NEXT: vnsrl.wx v8, v12, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i8: ; RV64D-LABEL: cttz_nxv8i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vzext.vf4 v12, v8 ; RV64D-NEXT: vzext.vf4 v12, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v12 ; RV64D-NEXT: vfcvt.f.xu.v v8, v12
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v12, 0 ; RV64D-NEXT: vnsrl.wx v8, v12, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false) %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1) declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
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; RV32D-NEXT: vmseq.vv v0, v10, v8 ; RV32D-NEXT: vmseq.vv v0, v10, v8
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vzext.vf4 v16, v8 ; RV32D-NEXT: vzext.vf4 v16, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v16 ; RV32D-NEXT: vfcvt.f.xu.v v8, v16
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v16, 0 ; RV32D-NEXT: vnsrl.wx v8, v16, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV32D-NEXT: vmerge.vim v8, v8, 8, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv16i8: ; RV64D-LABEL: cttz_nxv16i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV64D-NEXT: vmv.v.i v10, 0 ; RV64D-NEXT: vmv.v.i v10, 0
; RV64D-NEXT: vmseq.vv v0, v10, v8 ; RV64D-NEXT: vmseq.vv v0, v10, v8
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vzext.vf4 v16, v8 ; RV64D-NEXT: vzext.vf4 v16, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v16 ; RV64D-NEXT: vfcvt.f.xu.v v8, v16
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v16, 0 ; RV64D-NEXT: vnsrl.wx v8, v16, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: vmerge.vim v8, v8, 8, v0 ; RV64D-NEXT: vmerge.vim v8, v8, 8, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false) %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1) declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
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; RV32D-NEXT: vmv.v.i v9, 0 ; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vsrl.vi v8, v9, 23 ; RV32D-NEXT: vsrl.vi v8, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i16: ; RV64D-LABEL: cttz_nxv1i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vsrl.vi v8, v9, 23 ; RV64D-NEXT: vsrl.vi v8, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false) %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
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; RV32D-NEXT: vmv.v.i v9, 0 ; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vsrl.vi v8, v9, 23 ; RV32D-NEXT: vsrl.vi v8, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i16: ; RV64D-LABEL: cttz_nxv2i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vsrl.vi v8, v9, 23 ; RV64D-NEXT: vsrl.vi v8, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false) %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
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; RV32D-NEXT: vmv.v.i v9, 0 ; RV32D-NEXT: vmv.v.i v9, 0
; RV32D-NEXT: vmseq.vv v0, v9, v8 ; RV32D-NEXT: vmseq.vv v0, v9, v8
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vsrl.vi v8, v10, 23 ; RV32D-NEXT: vsrl.vi v8, v10, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v10, a0 ; RV32D-NEXT: vsub.vx v8, v10, a0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i16: ; RV64D-LABEL: cttz_nxv4i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vsrl.vi v8, v10, 23 ; RV64D-NEXT: vsrl.vi v8, v10, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v10, a0 ; RV64D-NEXT: vsub.vx v8, v10, a0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false) %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; RV32D-NEXT: vmv.v.i v10, 0 ; RV32D-NEXT: vmv.v.i v10, 0
; RV32D-NEXT: vmseq.vv v0, v10, v8 ; RV32D-NEXT: vmseq.vv v0, v10, v8
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vsrl.vi v8, v12, 23 ; RV32D-NEXT: vsrl.vi v8, v12, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v12, a0 ; RV32D-NEXT: vsub.vx v8, v12, a0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i16: ; RV64D-LABEL: cttz_nxv8i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV64D-NEXT: vmv.v.i v10, 0 ; RV64D-NEXT: vmv.v.i v10, 0
; RV64D-NEXT: vmseq.vv v0, v10, v8 ; RV64D-NEXT: vmseq.vv v0, v10, v8
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vsrl.vi v8, v12, 23 ; RV64D-NEXT: vsrl.vi v8, v12, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v12, a0 ; RV64D-NEXT: vsub.vx v8, v12, a0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false) %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
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; RV32D-NEXT: vmv.v.i v12, 0 ; RV32D-NEXT: vmv.v.i v12, 0
; RV32D-NEXT: vmseq.vv v0, v12, v8 ; RV32D-NEXT: vmseq.vv v0, v12, v8
; RV32D-NEXT: vrsub.vi v12, v8, 0 ; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12 ; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vsrl.vi v8, v16, 23 ; RV32D-NEXT: vsrl.vi v8, v16, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v16, a0 ; RV32D-NEXT: vsub.vx v8, v16, a0
; RV32D-NEXT: li a0, 16 ; RV32D-NEXT: li a0, 16
; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv16i16: ; RV64D-LABEL: cttz_nxv16i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV64D-NEXT: vmv.v.i v12, 0 ; RV64D-NEXT: vmv.v.i v12, 0
; RV64D-NEXT: vmseq.vv v0, v12, v8 ; RV64D-NEXT: vmseq.vv v0, v12, v8
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12 ; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vsrl.vi v8, v16, 23 ; RV64D-NEXT: vsrl.vi v8, v16, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v16, a0 ; RV64D-NEXT: vsub.vx v8, v16, a0
; RV64D-NEXT: li a0, 16 ; RV64D-NEXT: li a0, 16
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false) %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
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; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v9, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v9 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v9
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32D-NEXT: vsrl.vx v9, v10, a0 ; RV32D-NEXT: vsrl.vx v9, v10, a0
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v9, 0 ; RV32D-NEXT: vnsrl.wx v9, v9, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v9, v9, a0 ; RV32D-NEXT: vsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i32: ; RV64D-LABEL: cttz_nxv1i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64D-NEXT: vsrl.vx v8, v9, a0 ; RV64D-NEXT: vsrl.vx v8, v9, a0
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false) %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
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; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v9, v8, v9 ; RV32D-NEXT: vand.vv v9, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v9 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v9
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32D-NEXT: vsrl.vx v10, v10, a0 ; RV32D-NEXT: vsrl.vx v10, v10, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v9, v10, 0 ; RV32D-NEXT: vnsrl.wx v9, v10, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v9, v9, a0 ; RV32D-NEXT: vsub.vx v9, v9, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v9, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i32: ; RV64D-LABEL: cttz_nxv2i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vmv.v.i v9, 0 ; RV64D-NEXT: vmv.v.i v9, 0
; RV64D-NEXT: vmseq.vv v0, v9, v8 ; RV64D-NEXT: vmseq.vv v0, v9, v8
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64D-NEXT: vsrl.vx v8, v10, a0 ; RV64D-NEXT: vsrl.vx v8, v10, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v10, a0 ; RV64D-NEXT: vsub.vx v8, v10, a0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false) %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v10, v8, v10 ; RV32D-NEXT: vand.vv v10, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v10 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v10
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32D-NEXT: vsrl.vx v12, v12, a0 ; RV32D-NEXT: vsrl.vx v12, v12, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v12, 0 ; RV32D-NEXT: vnsrl.wx v10, v12, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v10, v10, a0 ; RV32D-NEXT: vsub.vx v10, v10, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v10, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i32: ; RV64D-LABEL: cttz_nxv4i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vmv.v.i v10, 0 ; RV64D-NEXT: vmv.v.i v10, 0
; RV64D-NEXT: vmseq.vv v0, v10, v8 ; RV64D-NEXT: vmseq.vv v0, v10, v8
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64D-NEXT: vsrl.vx v8, v12, a0 ; RV64D-NEXT: vsrl.vx v8, v12, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v12, a0 ; RV64D-NEXT: vsub.vx v8, v12, a0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false) %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV32D-NEXT: vrsub.vi v12, v8, 0 ; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v12, v8, v12 ; RV32D-NEXT: vand.vv v12, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v12 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v12
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32D-NEXT: vsrl.vx v16, v16, a0 ; RV32D-NEXT: vsrl.vx v16, v16, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v16, 0 ; RV32D-NEXT: vnsrl.wx v12, v16, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v12, v12, a0 ; RV32D-NEXT: vsub.vx v12, v12, a0
; RV32D-NEXT: vmseq.vi v0, v8, 0 ; RV32D-NEXT: vmseq.vi v0, v8, 0
; RV32D-NEXT: li a0, 32 ; RV32D-NEXT: li a0, 32
; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0 ; RV32D-NEXT: vmerge.vxm v8, v12, a0, v0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i32: ; RV64D-LABEL: cttz_nxv8i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vmv.v.i v12, 0 ; RV64D-NEXT: vmv.v.i v12, 0
; RV64D-NEXT: vmseq.vv v0, v12, v8 ; RV64D-NEXT: vmseq.vv v0, v12, v8
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12 ; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64D-NEXT: vsrl.vx v8, v16, a0 ; RV64D-NEXT: vsrl.vx v8, v16, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v16, a0 ; RV64D-NEXT: vsub.vx v8, v16, a0
; RV64D-NEXT: li a0, 32 ; RV64D-NEXT: li a0, 32
; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64D-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false) %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
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; RV32D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v9
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv1i8: ; RV64D-LABEL: cttz_zero_undef_nxv1i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v8, v9
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true) %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) { define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vzext.vf4 v9, v8 ; RV32D-NEXT: vzext.vf4 v9, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v9
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv2i8: ; RV64D-LABEL: cttz_zero_undef_nxv2i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vzext.vf4 v9, v8 ; RV64D-NEXT: vzext.vf4 v9, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v9 ; RV64D-NEXT: vfcvt.f.xu.v v8, v9
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true) %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) { define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vzext.vf4 v10, v8 ; RV32D-NEXT: vzext.vf4 v10, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v10 ; RV32D-NEXT: vfcvt.f.xu.v v8, v10
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v10, 0 ; RV32D-NEXT: vnsrl.wx v8, v10, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv4i8: ; RV64D-LABEL: cttz_zero_undef_nxv4i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vzext.vf4 v10, v8 ; RV64D-NEXT: vzext.vf4 v10, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v10 ; RV64D-NEXT: vfcvt.f.xu.v v8, v10
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v10, 0 ; RV64D-NEXT: vnsrl.wx v8, v10, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true) %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) { define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vzext.vf4 v12, v8 ; RV32D-NEXT: vzext.vf4 v12, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v12 ; RV32D-NEXT: vfcvt.f.xu.v v8, v12
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v12, 0 ; RV32D-NEXT: vnsrl.wx v8, v12, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv8i8: ; RV64D-LABEL: cttz_zero_undef_nxv8i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vzext.vf4 v12, v8 ; RV64D-NEXT: vzext.vf4 v12, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v12 ; RV64D-NEXT: vfcvt.f.xu.v v8, v12
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v12, 0 ; RV64D-NEXT: vnsrl.wx v8, v12, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true) %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) { define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vzext.vf4 v16, v8 ; RV32D-NEXT: vzext.vf4 v16, v8
; RV32D-NEXT: vfcvt.f.xu.v v8, v16 ; RV32D-NEXT: vfcvt.f.xu.v v8, v16
; RV32D-NEXT: vsrl.vi v8, v8, 23 ; RV32D-NEXT: vsrl.vi v8, v8, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v16, 0 ; RV32D-NEXT: vnsrl.wx v8, v16, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv16i8: ; RV64D-LABEL: cttz_zero_undef_nxv16i8:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vzext.vf4 v16, v8 ; RV64D-NEXT: vzext.vf4 v16, v8
; RV64D-NEXT: vfcvt.f.xu.v v8, v16 ; RV64D-NEXT: vfcvt.f.xu.v v8, v16
; RV64D-NEXT: vsrl.vi v8, v8, 23 ; RV64D-NEXT: vsrl.vi v8, v8, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v16, 0 ; RV64D-NEXT: vnsrl.wx v8, v16, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true) %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) { define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
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; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vsrl.vi v8, v9, 23 ; RV32D-NEXT: vsrl.vi v8, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv1i16: ; RV64D-LABEL: cttz_zero_undef_nxv1i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vsrl.vi v8, v9, 23 ; RV64D-NEXT: vsrl.vi v8, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true) %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) { define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
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; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vsrl.vi v8, v9, 23 ; RV32D-NEXT: vsrl.vi v8, v9, 23
; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv2i16: ; RV64D-LABEL: cttz_zero_undef_nxv2i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vsrl.vi v8, v9, 23 ; RV64D-NEXT: vsrl.vi v8, v9, 23
; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true) %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) { define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
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; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vsrl.vi v8, v10, 23 ; RV32D-NEXT: vsrl.vi v8, v10, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v10, a0 ; RV32D-NEXT: vsub.vx v8, v10, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv4i16: ; RV64D-LABEL: cttz_zero_undef_nxv4i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vsrl.vi v8, v10, 23 ; RV64D-NEXT: vsrl.vi v8, v10, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v10, a0 ; RV64D-NEXT: vsub.vx v8, v10, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true) %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) { define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
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; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vsrl.vi v8, v12, 23 ; RV32D-NEXT: vsrl.vi v8, v12, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v12, a0 ; RV32D-NEXT: vsub.vx v8, v12, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv8i16: ; RV64D-LABEL: cttz_zero_undef_nxv8i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vsrl.vi v8, v12, 23 ; RV64D-NEXT: vsrl.vi v8, v12, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v12, a0 ; RV64D-NEXT: vsub.vx v8, v12, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true) %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) { define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
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; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV32D-NEXT: vrsub.vi v12, v8, 0 ; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12 ; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-NEXT: vsrl.vi v8, v16, 23 ; RV32D-NEXT: vsrl.vi v8, v16, 23
; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: li a0, 127 ; RV32D-NEXT: li a0, 127
; RV32D-NEXT: vsub.vx v8, v16, a0 ; RV32D-NEXT: vsub.vx v8, v16, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv16i16: ; RV64D-LABEL: cttz_zero_undef_nxv16i16:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12 ; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-NEXT: vsrl.vi v8, v16, 23 ; RV64D-NEXT: vsrl.vi v8, v16, 23
; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: li a0, 127 ; RV64D-NEXT: li a0, 127
; RV64D-NEXT: vsub.vx v8, v16, a0 ; RV64D-NEXT: vsub.vx v8, v16, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true) %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) { define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32D-NEXT: vsrl.vx v8, v9, a0 ; RV32D-NEXT: vsrl.vx v8, v9, a0
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-NEXT: vnsrl.wi v8, v8, 0 ; RV32D-NEXT: vnsrl.wx v8, v8, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v8, v8, a0 ; RV32D-NEXT: vsub.vx v8, v8, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv1i32: ; RV64D-LABEL: cttz_zero_undef_nxv1i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64D-NEXT: vsrl.vx v8, v9, a0 ; RV64D-NEXT: vsrl.vx v8, v9, a0
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-NEXT: vnsrl.wi v8, v8, 0 ; RV64D-NEXT: vnsrl.wx v8, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v8, a0 ; RV64D-NEXT: vsub.vx v8, v8, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true) %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) { define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32D-NEXT: vsrl.vx v8, v10, a0 ; RV32D-NEXT: vsrl.vx v8, v10, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-NEXT: vnsrl.wi v10, v8, 0 ; RV32D-NEXT: vnsrl.wx v10, v8, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v8, v10, a0 ; RV32D-NEXT: vsub.vx v8, v10, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv2i32: ; RV64D-LABEL: cttz_zero_undef_nxv2i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9 ; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64D-NEXT: vsrl.vx v8, v10, a0 ; RV64D-NEXT: vsrl.vx v8, v10, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-NEXT: vnsrl.wi v10, v8, 0 ; RV64D-NEXT: vnsrl.wx v10, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v10, a0 ; RV64D-NEXT: vsub.vx v8, v10, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true) %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) { define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10 ; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32D-NEXT: vsrl.vx v8, v12, a0 ; RV32D-NEXT: vsrl.vx v8, v12, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-NEXT: vnsrl.wi v12, v8, 0 ; RV32D-NEXT: vnsrl.wx v12, v8, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v8, v12, a0 ; RV32D-NEXT: vsub.vx v8, v12, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv4i32: ; RV64D-LABEL: cttz_zero_undef_nxv4i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10 ; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64D-NEXT: vsrl.vx v8, v12, a0 ; RV64D-NEXT: vsrl.vx v8, v12, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-NEXT: vnsrl.wi v12, v8, 0 ; RV64D-NEXT: vnsrl.wx v12, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v12, a0 ; RV64D-NEXT: vsub.vx v8, v12, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true) %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) { define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
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; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV32D-NEXT: vrsub.vi v12, v8, 0 ; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12 ; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV32D-NEXT: li a0, 52 ; RV32D-NEXT: li a0, 52
; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32D-NEXT: vsrl.vx v8, v16, a0 ; RV32D-NEXT: vsrl.vx v8, v16, a0
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-NEXT: vnsrl.wi v16, v8, 0 ; RV32D-NEXT: vnsrl.wx v16, v8, zero
; RV32D-NEXT: li a0, 1023 ; RV32D-NEXT: li a0, 1023
; RV32D-NEXT: vsub.vx v8, v16, a0 ; RV32D-NEXT: vsub.vx v8, v16, a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_zero_undef_nxv8i32: ; RV64D-LABEL: cttz_zero_undef_nxv8i32:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12 ; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8 ; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-NEXT: li a0, 52 ; RV64D-NEXT: li a0, 52
; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64D-NEXT: vsrl.vx v8, v16, a0 ; RV64D-NEXT: vsrl.vx v8, v16, a0
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-NEXT: vnsrl.wi v16, v8, 0 ; RV64D-NEXT: vnsrl.wx v16, v8, zero
; RV64D-NEXT: li a0, 1023 ; RV64D-NEXT: li a0, 1023
; RV64D-NEXT: vsub.vx v8, v16, a0 ; RV64D-NEXT: vsub.vx v8, v16, a0
; RV64D-NEXT: ret ; RV64D-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true) %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) { define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
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llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

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store <vscale x 1 x i1> %y, <vscale x 1 x i1>* %z store <vscale x 1 x i1> %y, <vscale x 1 x i1>* %z
ret void ret void
} }
define void @truncstore_nxv1i16_nxv1i8(<vscale x 1 x i16> %x, <vscale x 1 x i8>* %z) { define void @truncstore_nxv1i16_nxv1i8(<vscale x 1 x i16> %x, <vscale x 1 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv1i16_nxv1i8: ; CHECK-LABEL: truncstore_nxv1i16_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8> %y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
ret void ret void
} }
define <vscale x 1 x i32> @sextload_nxv1i16_nxv1i32(<vscale x 1 x i16>* %x) { define <vscale x 1 x i32> @sextload_nxv1i16_nxv1i32(<vscale x 1 x i16>* %x) {
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%z = zext <vscale x 1 x i16> %y to <vscale x 1 x i64> %z = zext <vscale x 1 x i16> %y to <vscale x 1 x i64>
ret <vscale x 1 x i64> %z ret <vscale x 1 x i64> %z
} }
define void @truncstore_nxv2i16_nxv2i8(<vscale x 2 x i16> %x, <vscale x 2 x i8>* %z) { define void @truncstore_nxv2i16_nxv2i8(<vscale x 2 x i16> %x, <vscale x 2 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv2i16_nxv2i8: ; CHECK-LABEL: truncstore_nxv2i16_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i16> %x to <vscale x 2 x i8> %y = trunc <vscale x 2 x i16> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
ret void ret void
} }
define <vscale x 2 x i32> @sextload_nxv2i16_nxv2i32(<vscale x 2 x i16>* %x) { define <vscale x 2 x i32> @sextload_nxv2i16_nxv2i32(<vscale x 2 x i16>* %x) {
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%z = zext <vscale x 2 x i16> %y to <vscale x 2 x i64> %z = zext <vscale x 2 x i16> %y to <vscale x 2 x i64>
ret <vscale x 2 x i64> %z ret <vscale x 2 x i64> %z
} }
define void @truncstore_nxv4i16_nxv4i8(<vscale x 4 x i16> %x, <vscale x 4 x i8>* %z) { define void @truncstore_nxv4i16_nxv4i8(<vscale x 4 x i16> %x, <vscale x 4 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv4i16_nxv4i8: ; CHECK-LABEL: truncstore_nxv4i16_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i16> %x to <vscale x 4 x i8> %y = trunc <vscale x 4 x i16> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
ret void ret void
} }
define <vscale x 4 x i32> @sextload_nxv4i16_nxv4i32(<vscale x 4 x i16>* %x) { define <vscale x 4 x i32> @sextload_nxv4i16_nxv4i32(<vscale x 4 x i16>* %x) {
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%z = zext <vscale x 4 x i16> %y to <vscale x 4 x i64> %z = zext <vscale x 4 x i16> %y to <vscale x 4 x i64>
ret <vscale x 4 x i64> %z ret <vscale x 4 x i64> %z
} }
define void @truncstore_nxv8i16_nxv8i8(<vscale x 8 x i16> %x, <vscale x 8 x i8>* %z) { define void @truncstore_nxv8i16_nxv8i8(<vscale x 8 x i16> %x, <vscale x 8 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv8i16_nxv8i8: ; CHECK-LABEL: truncstore_nxv8i16_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i16> %x to <vscale x 8 x i8> %y = trunc <vscale x 8 x i16> %x to <vscale x 8 x i8>
store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z
ret void ret void
} }
define <vscale x 8 x i32> @sextload_nxv8i16_nxv8i32(<vscale x 8 x i16>* %x) { define <vscale x 8 x i32> @sextload_nxv8i16_nxv8i32(<vscale x 8 x i16>* %x) {
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = zext <vscale x 8 x i16> %y to <vscale x 8 x i64> %z = zext <vscale x 8 x i16> %y to <vscale x 8 x i64>
ret <vscale x 8 x i64> %z ret <vscale x 8 x i64> %z
} }
define void @truncstore_nxv16i16_nxv16i8(<vscale x 16 x i16> %x, <vscale x 16 x i8>* %z) { define void @truncstore_nxv16i16_nxv16i8(<vscale x 16 x i16> %x, <vscale x 16 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv16i16_nxv16i8: ; CHECK-LABEL: truncstore_nxv16i16_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vs2r.v v12, (a0) ; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 16 x i16> %x to <vscale x 16 x i8> %y = trunc <vscale x 16 x i16> %x to <vscale x 16 x i8>
store <vscale x 16 x i8> %y, <vscale x 16 x i8>* %z store <vscale x 16 x i8> %y, <vscale x 16 x i8>* %z
ret void ret void
} }
define <vscale x 16 x i32> @sextload_nxv16i16_nxv16i32(<vscale x 16 x i16>* %x) { define <vscale x 16 x i32> @sextload_nxv16i16_nxv16i32(<vscale x 16 x i16>* %x) {
Show All 19 Lines; CHECK-NEXT: ret
%z = zext <vscale x 16 x i16> %y to <vscale x 16 x i32> %z = zext <vscale x 16 x i16> %y to <vscale x 16 x i32>
ret <vscale x 16 x i32> %z ret <vscale x 16 x i32> %z
} }
define void @truncstore_nxv32i16_nxv32i8(<vscale x 32 x i16> %x, <vscale x 32 x i8>* %z) { define void @truncstore_nxv32i16_nxv32i8(<vscale x 32 x i16> %x, <vscale x 32 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv32i16_nxv32i8: ; CHECK-LABEL: truncstore_nxv32i16_nxv32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vs4r.v v16, (a0) ; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 32 x i16> %x to <vscale x 32 x i8> %y = trunc <vscale x 32 x i16> %x to <vscale x 32 x i8>
store <vscale x 32 x i8> %y, <vscale x 32 x i8>* %z store <vscale x 32 x i8> %y, <vscale x 32 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv1i32_nxv1i8(<vscale x 1 x i32> %x, <vscale x 1 x i8>* %z) { define void @truncstore_nxv1i32_nxv1i8(<vscale x 1 x i32> %x, <vscale x 1 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv1i32_nxv1i8: ; CHECK-LABEL: truncstore_nxv1i32_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8> %y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv1i32_nxv1i16(<vscale x 1 x i32> %x, <vscale x 1 x i16>* %z) { define void @truncstore_nxv1i32_nxv1i16(<vscale x 1 x i32> %x, <vscale x 1 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv1i32_nxv1i16: ; CHECK-LABEL: truncstore_nxv1i32_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16> %y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16>
store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z
ret void ret void
} }
define <vscale x 1 x i64> @sextload_nxv1i32_nxv1i64(<vscale x 1 x i32>* %x) { define <vscale x 1 x i64> @sextload_nxv1i32_nxv1i64(<vscale x 1 x i32>* %x) {
Show All 21 Lines; CHECK-NEXT: ret
%z = zext <vscale x 1 x i32> %y to <vscale x 1 x i64> %z = zext <vscale x 1 x i32> %y to <vscale x 1 x i64>
ret <vscale x 1 x i64> %z ret <vscale x 1 x i64> %z
} }
define void @truncstore_nxv2i32_nxv2i8(<vscale x 2 x i32> %x, <vscale x 2 x i8>* %z) { define void @truncstore_nxv2i32_nxv2i8(<vscale x 2 x i32> %x, <vscale x 2 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv2i32_nxv2i8: ; CHECK-LABEL: truncstore_nxv2i32_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i8> %y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv2i32_nxv2i16(<vscale x 2 x i32> %x, <vscale x 2 x i16>* %z) { define void @truncstore_nxv2i32_nxv2i16(<vscale x 2 x i32> %x, <vscale x 2 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv2i32_nxv2i16: ; CHECK-LABEL: truncstore_nxv2i32_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i16> %y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i16>
store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z
ret void ret void
} }
define <vscale x 2 x i64> @sextload_nxv2i32_nxv2i64(<vscale x 2 x i32>* %x) { define <vscale x 2 x i64> @sextload_nxv2i32_nxv2i64(<vscale x 2 x i32>* %x) {
Show All 19 Lines; CHECK-NEXT: ret
%z = zext <vscale x 2 x i32> %y to <vscale x 2 x i64> %z = zext <vscale x 2 x i32> %y to <vscale x 2 x i64>
ret <vscale x 2 x i64> %z ret <vscale x 2 x i64> %z
} }
define void @truncstore_nxv4i32_nxv4i8(<vscale x 4 x i32> %x, <vscale x 4 x i8>* %z) { define void @truncstore_nxv4i32_nxv4i8(<vscale x 4 x i32> %x, <vscale x 4 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv4i32_nxv4i8: ; CHECK-LABEL: truncstore_nxv4i32_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i8> %y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv4i32_nxv4i16(<vscale x 4 x i32> %x, <vscale x 4 x i16>* %z) { define void @truncstore_nxv4i32_nxv4i16(<vscale x 4 x i32> %x, <vscale x 4 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv4i32_nxv4i16: ; CHECK-LABEL: truncstore_nxv4i32_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i16> %y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i16>
store <vscale x 4 x i16> %y, <vscale x 4 x i16>* %z store <vscale x 4 x i16> %y, <vscale x 4 x i16>* %z
ret void ret void
} }
define <vscale x 4 x i64> @sextload_nxv4i32_nxv4i64(<vscale x 4 x i32>* %x) { define <vscale x 4 x i64> @sextload_nxv4i32_nxv4i64(<vscale x 4 x i32>* %x) {
Show All 19 Lines; CHECK-NEXT: ret
%z = zext <vscale x 4 x i32> %y to <vscale x 4 x i64> %z = zext <vscale x 4 x i32> %y to <vscale x 4 x i64>
ret <vscale x 4 x i64> %z ret <vscale x 4 x i64> %z
} }
define void @truncstore_nxv8i32_nxv8i8(<vscale x 8 x i32> %x, <vscale x 8 x i8>* %z) { define void @truncstore_nxv8i32_nxv8i8(<vscale x 8 x i32> %x, <vscale x 8 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv8i32_nxv8i8: ; CHECK-LABEL: truncstore_nxv8i32_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i8> %y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i8>
store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv8i32_nxv8i16(<vscale x 8 x i32> %x, <vscale x 8 x i16>* %z) { define void @truncstore_nxv8i32_nxv8i16(<vscale x 8 x i32> %x, <vscale x 8 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv8i32_nxv8i16: ; CHECK-LABEL: truncstore_nxv8i32_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vs2r.v v12, (a0) ; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i16> %y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i16>
store <vscale x 8 x i16> %y, <vscale x 8 x i16>* %z store <vscale x 8 x i16> %y, <vscale x 8 x i16>* %z
ret void ret void
} }
define <vscale x 8 x i64> @sextload_nxv8i32_nxv8i64(<vscale x 8 x i32>* %x) { define <vscale x 8 x i64> @sextload_nxv8i32_nxv8i64(<vscale x 8 x i32>* %x) {
Show All 19 Lines; CHECK-NEXT: ret
%z = zext <vscale x 8 x i32> %y to <vscale x 8 x i64> %z = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>
ret <vscale x 8 x i64> %z ret <vscale x 8 x i64> %z
} }
define void @truncstore_nxv16i32_nxv16i8(<vscale x 16 x i32> %x, <vscale x 16 x i8>* %z) { define void @truncstore_nxv16i32_nxv16i8(<vscale x 16 x i32> %x, <vscale x 16 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv16i32_nxv16i8: ; CHECK-LABEL: truncstore_nxv16i32_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i8> %y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i8>
store <vscale x 16 x i8> %y, <vscale x 16 x i8>* %z store <vscale x 16 x i8> %y, <vscale x 16 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv16i32_nxv16i16(<vscale x 16 x i32> %x, <vscale x 16 x i16>* %z) { define void @truncstore_nxv16i32_nxv16i16(<vscale x 16 x i32> %x, <vscale x 16 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv16i32_nxv16i16: ; CHECK-LABEL: truncstore_nxv16i32_nxv16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vs4r.v v16, (a0) ; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i16> %y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i16>
store <vscale x 16 x i16> %y, <vscale x 16 x i16>* %z store <vscale x 16 x i16> %y, <vscale x 16 x i16>* %z
ret void ret void
} }
define void @truncstore_nxv1i64_nxv1i8(<vscale x 1 x i64> %x, <vscale x 1 x i8>* %z) { define void @truncstore_nxv1i64_nxv1i8(<vscale x 1 x i64> %x, <vscale x 1 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv1i64_nxv1i8: ; CHECK-LABEL: truncstore_nxv1i64_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv1i64_nxv1i16(<vscale x 1 x i64> %x, <vscale x 1 x i16>* %z) { define void @truncstore_nxv1i64_nxv1i16(<vscale x 1 x i64> %x, <vscale x 1 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv1i64_nxv1i16: ; CHECK-LABEL: truncstore_nxv1i64_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i16> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i16>
store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z
ret void ret void
} }
define void @truncstore_nxv1i64_nxv1i32(<vscale x 1 x i64> %x, <vscale x 1 x i32>* %z) { define void @truncstore_nxv1i64_nxv1i32(<vscale x 1 x i64> %x, <vscale x 1 x i32>* %z) {
; CHECK-LABEL: truncstore_nxv1i64_nxv1i32: ; CHECK-LABEL: truncstore_nxv1i64_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
store <vscale x 1 x i32> %y, <vscale x 1 x i32>* %z store <vscale x 1 x i32> %y, <vscale x 1 x i32>* %z
ret void ret void
} }
define void @truncstore_nxv2i64_nxv2i8(<vscale x 2 x i64> %x, <vscale x 2 x i8>* %z) { define void @truncstore_nxv2i64_nxv2i8(<vscale x 2 x i64> %x, <vscale x 2 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv2i64_nxv2i8: ; CHECK-LABEL: truncstore_nxv2i64_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i8> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv2i64_nxv2i16(<vscale x 2 x i64> %x, <vscale x 2 x i16>* %z) { define void @truncstore_nxv2i64_nxv2i16(<vscale x 2 x i64> %x, <vscale x 2 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv2i64_nxv2i16: ; CHECK-LABEL: truncstore_nxv2i64_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i16> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i16>
store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z
ret void ret void
} }
define void @truncstore_nxv2i64_nxv2i32(<vscale x 2 x i64> %x, <vscale x 2 x i32>* %z) { define void @truncstore_nxv2i64_nxv2i32(<vscale x 2 x i64> %x, <vscale x 2 x i32>* %z) {
; CHECK-LABEL: truncstore_nxv2i64_nxv2i32: ; CHECK-LABEL: truncstore_nxv2i64_nxv2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
store <vscale x 2 x i32> %y, <vscale x 2 x i32>* %z store <vscale x 2 x i32> %y, <vscale x 2 x i32>* %z
ret void ret void
} }
define void @truncstore_nxv4i64_nxv4i8(<vscale x 4 x i64> %x, <vscale x 4 x i8>* %z) { define void @truncstore_nxv4i64_nxv4i8(<vscale x 4 x i64> %x, <vscale x 4 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv4i64_nxv4i8: ; CHECK-LABEL: truncstore_nxv4i64_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i8> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv4i64_nxv4i16(<vscale x 4 x i64> %x, <vscale x 4 x i16>* %z) { define void @truncstore_nxv4i64_nxv4i16(<vscale x 4 x i64> %x, <vscale x 4 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv4i64_nxv4i16: ; CHECK-LABEL: truncstore_nxv4i64_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i16> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i16>
store <vscale x 4 x i16> %y, <vscale x 4 x i16>* %z store <vscale x 4 x i16> %y, <vscale x 4 x i16>* %z
ret void ret void
} }
define void @truncstore_nxv4i64_nxv4i32(<vscale x 4 x i64> %x, <vscale x 4 x i32>* %z) { define void @truncstore_nxv4i64_nxv4i32(<vscale x 4 x i64> %x, <vscale x 4 x i32>* %z) {
; CHECK-LABEL: truncstore_nxv4i64_nxv4i32: ; CHECK-LABEL: truncstore_nxv4i64_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vs2r.v v12, (a0) ; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
store <vscale x 4 x i32> %y, <vscale x 4 x i32>* %z store <vscale x 4 x i32> %y, <vscale x 4 x i32>* %z
ret void ret void
} }
define void @truncstore_nxv8i64_nxv8i8(<vscale x 8 x i64> %x, <vscale x 8 x i8>* %z) { define void @truncstore_nxv8i64_nxv8i8(<vscale x 8 x i64> %x, <vscale x 8 x i8>* %z) {
; CHECK-LABEL: truncstore_nxv8i64_nxv8i8: ; CHECK-LABEL: truncstore_nxv8i64_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i8> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i8>
store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z
ret void ret void
} }
define void @truncstore_nxv8i64_nxv8i16(<vscale x 8 x i64> %x, <vscale x 8 x i16>* %z) { define void @truncstore_nxv8i64_nxv8i16(<vscale x 8 x i64> %x, <vscale x 8 x i16>* %z) {
; CHECK-LABEL: truncstore_nxv8i64_nxv8i16: ; CHECK-LABEL: truncstore_nxv8i64_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i16> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i16>
store <vscale x 8 x i16> %y, <vscale x 8 x i16>* %z store <vscale x 8 x i16> %y, <vscale x 8 x i16>* %z
ret void ret void
} }
define void @truncstore_nxv8i64_nxv8i32(<vscale x 8 x i64> %x, <vscale x 8 x i32>* %z) { define void @truncstore_nxv8i64_nxv8i32(<vscale x 8 x i64> %x, <vscale x 8 x i32>* %z) {
; CHECK-LABEL: truncstore_nxv8i64_nxv8i32: ; CHECK-LABEL: truncstore_nxv8i64_nxv8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vs4r.v v16, (a0) ; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
store <vscale x 8 x i32> %y, <vscale x 8 x i32>* %z store <vscale x 8 x i32> %y, <vscale x 8 x i32>* %z
ret void ret void
} }
define <vscale x 1 x float> @extload_nxv1f16_nxv1f32(<vscale x 1 x half>* %x) { define <vscale x 1 x float> @extload_nxv1f16_nxv1f32(<vscale x 1 x half>* %x) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX8-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX8-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; LMULMAX8-RV32-NEXT: vzext.vf4 v12, v8 ; LMULMAX8-RV32-NEXT: vzext.vf4 v12, v8
; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v12, v12 ; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v12, v12
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v10, v12, 23 ; LMULMAX8-RV32-NEXT: vnsrl.wi v10, v12, 23
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX8-RV32-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX8-RV32-NEXT: li a1, 134 ; LMULMAX8-RV32-NEXT: li a1, 134
; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV32-NEXT: vrsub.vx v8, v9, a1 ; LMULMAX8-RV32-NEXT: vrsub.vx v8, v9, a1
; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: ctlz_v16i8: ; LMULMAX8-RV64-LABEL: ctlz_v16i8:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX8-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; LMULMAX8-RV64-NEXT: vzext.vf4 v12, v8 ; LMULMAX8-RV64-NEXT: vzext.vf4 v12, v8
; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v12, v12 ; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v12, v12
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v10, v12, 23 ; LMULMAX8-RV64-NEXT: vnsrl.wi v10, v12, 23
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX8-RV64-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX8-RV64-NEXT: li a1, 134 ; LMULMAX8-RV64-NEXT: li a1, 134
; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV64-NEXT: vrsub.vx v8, v9, a1 ; LMULMAX8-RV64-NEXT: vrsub.vx v8, v9, a1
; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV64-NEXT: ret ; LMULMAX8-RV64-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x %a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y %b = load <16 x i8>, <16 x i8>* %y
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; LMULMAX8-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; LMULMAX8-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX8-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; LMULMAX8-RV32-NEXT: vzext.vf4 v16, v8 ; LMULMAX8-RV32-NEXT: vzext.vf4 v16, v8
; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v16, v16 ; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v16, v16
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v12, v16, 23 ; LMULMAX8-RV32-NEXT: vnsrl.wi v12, v16, 23
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX8-RV32-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX8-RV32-NEXT: li a1, 134 ; LMULMAX8-RV32-NEXT: li a1, 134
; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV32-NEXT: vrsub.vx v8, v10, a1 ; LMULMAX8-RV32-NEXT: vrsub.vx v8, v10, a1
; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: ctlz_v32i8: ; LMULMAX8-RV64-LABEL: ctlz_v32i8:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: li a1, 32 ; LMULMAX8-RV64-NEXT: li a1, 32
; LMULMAX8-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; LMULMAX8-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; LMULMAX8-RV64-NEXT: vzext.vf4 v16, v8 ; LMULMAX8-RV64-NEXT: vzext.vf4 v16, v8
; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v16, v16 ; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v16, v16
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v12, v16, 23 ; LMULMAX8-RV64-NEXT: vnsrl.wi v12, v16, 23
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX8-RV64-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX8-RV64-NEXT: li a1, 134 ; LMULMAX8-RV64-NEXT: li a1, 134
; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV64-NEXT: vrsub.vx v8, v10, a1 ; LMULMAX8-RV64-NEXT: vrsub.vx v8, v10, a1
; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV64-NEXT: ret ; LMULMAX8-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x %a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y %b = load <32 x i8>, <32 x i8>* %y
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; LMULMAX8-RV32-NEXT: vrsub.vi v9, v8, 0 ; LMULMAX8-RV32-NEXT: vrsub.vi v9, v8, 0
; LMULMAX8-RV32-NEXT: vand.vv v9, v8, v9 ; LMULMAX8-RV32-NEXT: vand.vv v9, v8, v9
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; LMULMAX8-RV32-NEXT: vzext.vf4 v12, v9 ; LMULMAX8-RV32-NEXT: vzext.vf4 v12, v9
; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v12, v12 ; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v12, v12
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v10, v12, 23 ; LMULMAX8-RV32-NEXT: vnsrl.wi v10, v12, 23
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX8-RV32-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX8-RV32-NEXT: li a1, 127 ; LMULMAX8-RV32-NEXT: li a1, 127
; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV32-NEXT: vsub.vx v8, v9, a1 ; LMULMAX8-RV32-NEXT: vsub.vx v8, v9, a1
; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: cttz_v16i8: ; LMULMAX8-RV64-LABEL: cttz_v16i8:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX8-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX8-RV64-NEXT: vrsub.vi v9, v8, 0 ; LMULMAX8-RV64-NEXT: vrsub.vi v9, v8, 0
; LMULMAX8-RV64-NEXT: vand.vv v9, v8, v9 ; LMULMAX8-RV64-NEXT: vand.vv v9, v8, v9
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; LMULMAX8-RV64-NEXT: vzext.vf4 v12, v9 ; LMULMAX8-RV64-NEXT: vzext.vf4 v12, v9
; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v12, v12 ; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v12, v12
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v10, v12, 23 ; LMULMAX8-RV64-NEXT: vnsrl.wi v10, v12, 23
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX8-RV64-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX8-RV64-NEXT: li a1, 127 ; LMULMAX8-RV64-NEXT: li a1, 127
; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV64-NEXT: vsub.vx v8, v9, a1 ; LMULMAX8-RV64-NEXT: vsub.vx v8, v9, a1
; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV64-NEXT: ret ; LMULMAX8-RV64-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x %a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y %b = load <16 x i8>, <16 x i8>* %y
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; LMULMAX8-RV32-NEXT: vrsub.vi v10, v8, 0 ; LMULMAX8-RV32-NEXT: vrsub.vi v10, v8, 0
; LMULMAX8-RV32-NEXT: vand.vv v10, v8, v10 ; LMULMAX8-RV32-NEXT: vand.vv v10, v8, v10
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; LMULMAX8-RV32-NEXT: vzext.vf4 v16, v10 ; LMULMAX8-RV32-NEXT: vzext.vf4 v16, v10
; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v16, v16 ; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v16, v16
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v12, v16, 23 ; LMULMAX8-RV32-NEXT: vnsrl.wi v12, v16, 23
; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; LMULMAX8-RV32-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX8-RV32-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX8-RV32-NEXT: li a1, 127 ; LMULMAX8-RV32-NEXT: li a1, 127
; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV32-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV32-NEXT: vsub.vx v8, v10, a1 ; LMULMAX8-RV32-NEXT: vsub.vx v8, v10, a1
; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV32-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: cttz_v32i8: ; LMULMAX8-RV64-LABEL: cttz_v32i8:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: li a1, 32 ; LMULMAX8-RV64-NEXT: li a1, 32
; LMULMAX8-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; LMULMAX8-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX8-RV64-NEXT: vrsub.vi v10, v8, 0 ; LMULMAX8-RV64-NEXT: vrsub.vi v10, v8, 0
; LMULMAX8-RV64-NEXT: vand.vv v10, v8, v10 ; LMULMAX8-RV64-NEXT: vand.vv v10, v8, v10
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; LMULMAX8-RV64-NEXT: vzext.vf4 v16, v10 ; LMULMAX8-RV64-NEXT: vzext.vf4 v16, v10
; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v16, v16 ; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v16, v16
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v12, v16, 23 ; LMULMAX8-RV64-NEXT: vnsrl.wi v12, v16, 23
; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; LMULMAX8-RV64-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; LMULMAX8-RV64-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX8-RV64-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX8-RV64-NEXT: li a1, 127 ; LMULMAX8-RV64-NEXT: li a1, 127
; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0 ; LMULMAX8-RV64-NEXT: vmseq.vi v0, v8, 0
; LMULMAX8-RV64-NEXT: vsub.vx v8, v10, a1 ; LMULMAX8-RV64-NEXT: vsub.vx v8, v10, a1
; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0 ; LMULMAX8-RV64-NEXT: vmerge.vim v8, v8, 8, v0
; LMULMAX8-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX8-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX8-RV64-NEXT: ret ; LMULMAX8-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x %a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y %b = load <32 x i8>, <32 x i8>* %y
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

Show First 20 Lines • Show All 567 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <2 x i1> %y, <2 x i1>* %z store <2 x i1> %y, <2 x i1>* %z
ret void ret void
} }
define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) { define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i16_v2i8: ; CHECK-LABEL: truncstore_v2i16_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i16> %x to <2 x i8> %y = trunc <2 x i16> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z store <2 x i8> %y, <2 x i8>* %z
ret void ret void
} }
define <2 x i32> @sextload_v2i16_v2i32(<2 x i16>* %x) { define <2 x i32> @sextload_v2i16_v2i32(<2 x i16>* %x) {
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%z = zext <2 x i16> %y to <2 x i64> %z = zext <2 x i16> %y to <2 x i64>
ret <2 x i64> %z ret <2 x i64> %z
} }
define void @truncstore_v4i16_v4i8(<4 x i16> %x, <4 x i8>* %z) { define void @truncstore_v4i16_v4i8(<4 x i16> %x, <4 x i8>* %z) {
; CHECK-LABEL: truncstore_v4i16_v4i8: ; CHECK-LABEL: truncstore_v4i16_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <4 x i16> %x to <4 x i8> %y = trunc <4 x i16> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z store <4 x i8> %y, <4 x i8>* %z
ret void ret void
} }
define <4 x i32> @sextload_v4i16_v4i32(<4 x i16>* %x) { define <4 x i32> @sextload_v4i16_v4i32(<4 x i16>* %x) {
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <4 x i16> %y to <4 x i64> %z = zext <4 x i16> %y to <4 x i64>
ret <4 x i64> %z ret <4 x i64> %z
} }
define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %z) { define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %z) {
; CHECK-LABEL: truncstore_v8i16_v8i8: ; CHECK-LABEL: truncstore_v8i16_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <8 x i16> %x to <8 x i8> %y = trunc <8 x i16> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z store <8 x i8> %y, <8 x i8>* %z
ret void ret void
} }
define <8 x i32> @sextload_v8i16_v8i32(<8 x i16>* %x) { define <8 x i32> @sextload_v8i16_v8i32(<8 x i16>* %x) {
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <8 x i16> %y to <8 x i64> %z = zext <8 x i16> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) { define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i16_v16i8: ; LMULMAX1-LABEL: truncstore_v16i16_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i16_v16i8: ; LMULMAX4-LABEL: truncstore_v16i16_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX4-NEXT: vse8.v v10, (a0) ; LMULMAX4-NEXT: vse8.v v10, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i16> %x to <16 x i8> %y = trunc <16 x i16> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define <16 x i32> @sextload_v16i16_v16i32(<16 x i16>* %x) { define <16 x i32> @sextload_v16i16_v16i32(<16 x i16>* %x) {
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <16 x i16> %y to <16 x i64> %z = zext <16 x i16> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define void @truncstore_v2i32_v2i8(<2 x i32> %x, <2 x i8>* %z) { define void @truncstore_v2i32_v2i8(<2 x i32> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i32_v2i8: ; CHECK-LABEL: truncstore_v2i32_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i32> %x to <2 x i8> %y = trunc <2 x i32> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z store <2 x i8> %y, <2 x i8>* %z
ret void ret void
} }
define void @truncstore_v2i32_v2i16(<2 x i32> %x, <2 x i16>* %z) { define void @truncstore_v2i32_v2i16(<2 x i32> %x, <2 x i16>* %z) {
; CHECK-LABEL: truncstore_v2i32_v2i16: ; CHECK-LABEL: truncstore_v2i32_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i32> %x to <2 x i16> %y = trunc <2 x i32> %x to <2 x i16>
store <2 x i16> %y, <2 x i16>* %z store <2 x i16> %y, <2 x i16>* %z
ret void ret void
} }
define <2 x i64> @sextload_v2i32_v2i64(<2 x i32>* %x) { define <2 x i64> @sextload_v2i32_v2i64(<2 x i32>* %x) {
Show All 21 Lines; CHECK-NEXT: ret
%z = zext <2 x i32> %y to <2 x i64> %z = zext <2 x i32> %y to <2 x i64>
ret <2 x i64> %z ret <2 x i64> %z
} }
define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %z) { define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %z) {
; CHECK-LABEL: truncstore_v4i32_v4i8: ; CHECK-LABEL: truncstore_v4i32_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <4 x i32> %x to <4 x i8> %y = trunc <4 x i32> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z store <4 x i8> %y, <4 x i8>* %z
ret void ret void
} }
define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %z) { define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %z) {
; CHECK-LABEL: truncstore_v4i32_v4i16: ; CHECK-LABEL: truncstore_v4i32_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <4 x i32> %x to <4 x i16> %y = trunc <4 x i32> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z store <4 x i16> %y, <4 x i16>* %z
ret void ret void
} }
define <4 x i64> @sextload_v4i32_v4i64(<4 x i32>* %x) { define <4 x i64> @sextload_v4i32_v4i64(<4 x i32>* %x) {
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <4 x i32> %y to <4 x i64> %z = zext <4 x i32> %y to <4 x i64>
ret <4 x i64> %z ret <4 x i64> %z
} }
define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) { define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i8: ; LMULMAX1-LABEL: truncstore_v8i32_v8i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i32_v8i8: ; LMULMAX4-LABEL: truncstore_v8i32_v8i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v10, zero
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i8> %y = trunc <8 x i32> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z store <8 x i8> %y, <8 x i8>* %z
ret void ret void
} }
define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) { define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i16: ; LMULMAX1-LABEL: truncstore_v8i32_v8i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i32_v8i16: ; LMULMAX4-LABEL: truncstore_v8i32_v8i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX4-NEXT: vse16.v v10, (a0) ; LMULMAX4-NEXT: vse16.v v10, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i16> %y = trunc <8 x i32> %x to <8 x i16>
store <8 x i16> %y, <8 x i16>* %z store <8 x i16> %y, <8 x i16>* %z
ret void ret void
} }
define <8 x i64> @sextload_v8i32_v8i64(<8 x i32>* %x) { define <8 x i64> @sextload_v8i32_v8i64(<8 x i32>* %x) {
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <8 x i32> %y to <8 x i64> %z = zext <8 x i32> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) { define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i8: ; LMULMAX1-LABEL: truncstore_v16i32_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 12
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i32_v16i8: ; LMULMAX4-LABEL: truncstore_v16i32_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v12, zero
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i32> %x to <16 x i8> %y = trunc <16 x i32> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) { define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i16: ; LMULMAX1-LABEL: truncstore_v16i32_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v10, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i32_v16i16: ; LMULMAX4-LABEL: truncstore_v16i32_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v8, zero
; LMULMAX4-NEXT: vse16.v v12, (a0) ; LMULMAX4-NEXT: vse16.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i32> %x to <16 x i16> %y = trunc <16 x i32> %x to <16 x i16>
store <16 x i16> %y, <16 x i16>* %z store <16 x i16> %y, <16 x i16>* %z
ret void ret void
} }
define <16 x i64> @sextload_v16i32_v16i64(<16 x i32>* %x) { define <16 x i64> @sextload_v16i32_v16i64(<16 x i32>* %x) {
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <16 x i32> %y to <16 x i64> %z = zext <16 x i32> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %z) { define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i64_v2i8: ; CHECK-LABEL: truncstore_v2i64_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i8> %y = trunc <2 x i64> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z store <2 x i8> %y, <2 x i8>* %z
ret void ret void
} }
define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %z) { define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %z) {
; CHECK-LABEL: truncstore_v2i64_v2i16: ; CHECK-LABEL: truncstore_v2i64_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i16> %y = trunc <2 x i64> %x to <2 x i16>
store <2 x i16> %y, <2 x i16>* %z store <2 x i16> %y, <2 x i16>* %z
ret void ret void
} }
define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %z) { define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %z) {
; CHECK-LABEL: truncstore_v2i64_v2i32: ; CHECK-LABEL: truncstore_v2i64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i32> %y = trunc <2 x i64> %x to <2 x i32>
store <2 x i32> %y, <2 x i32>* %z store <2 x i32> %y, <2 x i32>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) { define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i8: ; LMULMAX1-LABEL: truncstore_v4i64_v4i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i8: ; LMULMAX4-LABEL: truncstore_v4i64_v4i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v10, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i8> %y = trunc <4 x i64> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z store <4 x i8> %y, <4 x i8>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) { define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i16: ; LMULMAX1-LABEL: truncstore_v4i64_v4i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i16: ; LMULMAX4-LABEL: truncstore_v4i64_v4i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v10, zero
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i16> %y = trunc <4 x i64> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z store <4 x i16> %y, <4 x i16>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) { define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i32: ; LMULMAX1-LABEL: truncstore_v4i64_v4i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i32: ; LMULMAX4-LABEL: truncstore_v4i64_v4i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX4-NEXT: vse32.v v10, (a0) ; LMULMAX4-NEXT: vse32.v v10, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i32> %y = trunc <4 x i64> %x to <4 x i32>
store <4 x i32> %y, <4 x i32>* %z store <4 x i32> %y, <4 x i32>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) { define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i8: ; LMULMAX1-LABEL: truncstore_v8i64_v8i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i8: ; LMULMAX4-LABEL: truncstore_v8i64_v8i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v12, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i8> %y = trunc <8 x i64> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z store <8 x i8> %y, <8 x i8>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) { define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i16: ; LMULMAX1-LABEL: truncstore_v8i64_v8i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i16: ; LMULMAX4-LABEL: truncstore_v8i64_v8i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v12, zero
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i16> %y = trunc <8 x i64> %x to <8 x i16>
store <8 x i16> %y, <8 x i16>* %z store <8 x i16> %y, <8 x i16>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) { define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i32: ; LMULMAX1-LABEL: truncstore_v8i64_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v10, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i32: ; LMULMAX4-LABEL: truncstore_v8i64_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v8, zero
; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i32> %y = trunc <8 x i64> %x to <8 x i32>
store <8 x i32> %y, <8 x i32>* %z store <8 x i32> %y, <8 x i32>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) { define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i8: ; LMULMAX1-LABEL: truncstore_v16i64_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v12, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 10, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 10, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v13, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 10 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 10
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v14, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v14, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 14, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 14, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 12
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v15, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 14 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 14
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i8: ; LMULMAX4-LABEL: truncstore_v16i64_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v16, v12, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v16, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v12, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v14, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v14, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX4-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX4-NEXT: vslideup.vi v8, v12, 8
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i8> %y = trunc <16 x i64> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) { define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i16: ; LMULMAX1-LABEL: truncstore_v16i64_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v13, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v10, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v14, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v14, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v15, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 6
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i16: ; LMULMAX4-LABEL: truncstore_v16i64_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v16, v12, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v16, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v14, v8, zero
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX4-NEXT: vnsrl.wx v8, v14, zero
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu
; LMULMAX4-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX4-NEXT: vslideup.vi v8, v12, 8
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i16> %y = trunc <16 x i64> %x to <16 x i16>
store <16 x i16> %y, <16 x i16>* %z store <16 x i16> %y, <16 x i16>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) { define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i32: ; LMULMAX1-LABEL: truncstore_v16i64_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v10, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v13, zero
; LMULMAX1-NEXT: vnsrl.wi v11, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v11, v12, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v11, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v11, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v15, zero
; LMULMAX1-NEXT: vnsrl.wi v12, v14, 0 ; LMULMAX1-NEXT: vnsrl.wx v12, v14, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v9, 2
; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vse32.v v12, (a1) ; LMULMAX1-NEXT: vse32.v v12, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vse32.v v11, (a1) ; LMULMAX1-NEXT: vse32.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i32: ; LMULMAX4-LABEL: truncstore_v16i64_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vnsrl.wx v16, v12, zero
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wx v12, v8, zero
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu
; LMULMAX4-NEXT: vslideup.vi v12, v16, 8 ; LMULMAX4-NEXT: vslideup.vi v12, v16, 8
; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i32> %y = trunc <16 x i64> %x to <16 x i32>
store <16 x i32> %y, <16 x i32>* %z store <16 x i32> %y, <16 x i32>* %z
ret void ret void
} }
▲ Show 20 Lines • Show All 314 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

Show First 20 Lines • Show All 342 Lines • ▼ Show 20 Lines
define void @fp2si_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) { define void @fp2si_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
; CHECK-LABEL: fp2si_v2f64_v2i8: ; CHECK-LABEL: fp2si_v2f64_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%d = fptosi <2 x double> %a to <2 x i8> %d = fptosi <2 x double> %a to <2 x i8>
store <2 x i8> %d, <2 x i8>* %y store <2 x i8> %d, <2 x i8>* %y
ret void ret void
} }
define void @fp2ui_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) { define void @fp2ui_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
; CHECK-LABEL: fp2ui_v2f64_v2i8: ; CHECK-LABEL: fp2ui_v2f64_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%d = fptoui <2 x double> %a to <2 x i8> %d = fptoui <2 x double> %a to <2 x i8>
store <2 x i8> %d, <2 x i8>* %y store <2 x i8> %d, <2 x i8>* %y
ret void ret void
} }
Show All 24 Lines
define void @fp2si_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) { define void @fp2si_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
; LMULMAX8-LABEL: fp2si_v8f64_v8i8: ; LMULMAX8-LABEL: fp2si_v8f64_v8i8:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8 ; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX8-NEXT: vnsrl.wx v8, v12, zero
; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX8-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX8-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX8-NEXT: vse8.v v8, (a1) ; LMULMAX8-NEXT: vse8.v v8, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2si_v8f64_v8i8: ; LMULMAX1-LABEL: fp2si_v8f64_v8i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32 ; LMULMAX1-NEXT: addi a2, a0, 32
; LMULMAX1-NEXT: vle64.v v9, (a2) ; LMULMAX1-NEXT: vle64.v v9, (a2)
; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v10 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v11 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v11, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v11, v12, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v11, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v11, v11, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse8.v v10, (a1) ; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptosi <8 x double> %a to <8 x i8> %d = fptosi <8 x double> %a to <8 x i8>
store <8 x i8> %d, <8 x i8>* %y store <8 x i8> %d, <8 x i8>* %y
ret void ret void
} }
define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) { define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
; LMULMAX8-LABEL: fp2ui_v8f64_v8i8: ; LMULMAX8-LABEL: fp2ui_v8f64_v8i8:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX8-NEXT: vnsrl.wx v8, v12, zero
; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX8-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX8-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX8-NEXT: vse8.v v8, (a1) ; LMULMAX8-NEXT: vse8.v v8, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2ui_v8f64_v8i8: ; LMULMAX1-LABEL: fp2ui_v8f64_v8i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32 ; LMULMAX1-NEXT: addi a2, a0, 32
; LMULMAX1-NEXT: vle64.v v9, (a2) ; LMULMAX1-NEXT: vle64.v v9, (a2)
; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v10 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v12, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wx v10, v10, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v11 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v11, v12, 0 ; LMULMAX1-NEXT: vnsrl.wx v11, v12, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v11, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v11, v11, zero
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v11, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse8.v v10, (a1) ; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptoui <8 x double> %a to <8 x i8> %d = fptoui <8 x double> %a to <8 x i8>
store <8 x i8> %d, <8 x i8>* %y store <8 x i8> %d, <8 x i8>* %y
ret void ret void
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
} }
define void @trunc_v4i8_v4i32(<4 x i32>* %x, <4 x i8>* %z) { define void @trunc_v4i8_v4i32(<4 x i32>* %x, <4 x i8>* %z) {
; CHECK-LABEL: trunc_v4i8_v4i32: ; CHECK-LABEL: trunc_v4i8_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x %a = load <4 x i32>, <4 x i32>* %x
%b = trunc <4 x i32> %a to <4 x i8> %b = trunc <4 x i32> %a to <4 x i8>
store <4 x i8> %b, <4 x i8>* %z store <4 x i8> %b, <4 x i8>* %z
ret void ret void
} }
define void @trunc_v8i8_v8i32(<8 x i32>* %x, <8 x i8>* %z) { define void @trunc_v8i8_v8i32(<8 x i32>* %x, <8 x i8>* %z) {
; LMULMAX8-LABEL: trunc_v8i8_v8i32: ; LMULMAX8-LABEL: trunc_v8i8_v8i32:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: vle32.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX8-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX8-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX8-NEXT: vnsrl.wx v8, v10, zero
; LMULMAX8-NEXT: vse8.v v8, (a1) ; LMULMAX8-NEXT: vse8.v v8, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX2-LABEL: trunc_v8i8_v8i32: ; LMULMAX2-LABEL: trunc_v8i8_v8i32:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX2-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX2-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX2-NEXT: vnsrl.wx v10, v8, zero
; LMULMAX2-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX2-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX2-NEXT: vnsrl.wx v8, v10, zero
; LMULMAX2-NEXT: vse8.v v8, (a1) ; LMULMAX2-NEXT: vse8.v v8, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: trunc_v8i8_v8i32: ; LMULMAX1-LABEL: trunc_v8i8_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wx v8, v8, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wx v9, v9, zero
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse8.v v8, (a1) ; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%b = trunc <8 x i32> %a to <8 x i8> %b = trunc <8 x i32> %a to <8 x i8>
store <8 x i8> %b, <8 x i8>* %z store <8 x i8> %b, <8 x i8>* %z
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Show First 20 Lines • Show All 1,031 Lines • ▼ Show 20 Lines
define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i64: ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i64: ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i64: ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vzext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i64: ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 34 Lines
define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i64: ; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i64: ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i64: ; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i64: ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 33 Lines
define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_v8i32_v8i64: ; RV32-LABEL: mgather_baseidx_sext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_v8i32_v8i64: ; RV64-LABEL: mgather_baseidx_sext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 10 Lines
define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_v8i32_v8i64: ; RV32-LABEL: mgather_baseidx_zext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_v8i32_v8i64: ; RV64-LABEL: mgather_baseidx_zext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 9 Lines
} }
define <8 x i64> @mgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m, <8 x i64> %passthru) { define <8 x i64> @mgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_v8i64: ; RV32-LABEL: mgather_baseidx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_v8i64: ; RV64-LABEL: mgather_baseidx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
▲ Show 20 Lines • Show All 645 Lines • ▼ Show 20 Lines
define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f64: ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f64: ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f64: ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vzext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f64: ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f64: ; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f64: ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f64: ; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f64: ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_v8i32_v8f64: ; RV32-LABEL: mgather_baseidx_sext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_v8i32_v8f64: ; RV64-LABEL: mgather_baseidx_sext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_v8i32_v8f64: ; RV32-LABEL: mgather_baseidx_zext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_v8i32_v8f64: ; RV64-LABEL: mgather_baseidx_zext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 9 Lines
} }
define <8 x double> @mgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x i1> %m, <8 x double> %passthru) { define <8 x double> @mgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x i1> %m, <8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_v8f64: ; RV32-LABEL: mgather_baseidx_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_v8f64: ; RV64-LABEL: mgather_baseidx_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

Show All 38 Lines; RV64-NEXT: ret
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %val, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %val, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
ret void ret void
} }
define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 x i1> %m) { define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i16_truncstore_v2i8: ; RV32-LABEL: mscatter_v2i16_truncstore_v2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_v2i16_truncstore_v2i8: ; RV64-LABEL: mscatter_v2i16_truncstore_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i16> %val to <2 x i8> %tval = trunc <2 x i16> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
ret void ret void
} }
define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 x i1> %m) { define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i32_truncstore_v2i8: ; RV32-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i8: ; RV64-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i8> %tval = trunc <2 x i32> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
ret void ret void
} }
define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 x i1> %m) { define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i64_truncstore_v2i8: ; RV32-LABEL: mscatter_v2i64_truncstore_v2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i8: ; RV64-LABEL: mscatter_v2i64_truncstore_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i8> %tval = trunc <2 x i64> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8>, <4 x i8*>, i32, <4 x i1>) declare void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8>, <4 x i8*>, i32, <4 x i1>)
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %val, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %val, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
ret void ret void
} }
define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <2 x i1> %m) { define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i32_truncstore_v2i16: ; RV32-LABEL: mscatter_v2i32_truncstore_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i16: ; RV64-LABEL: mscatter_v2i32_truncstore_v2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i16> %tval = trunc <2 x i32> %val to <2 x i16>
call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
ret void ret void
} }
define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <2 x i1> %m) { define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i64_truncstore_v2i16: ; RV32-LABEL: mscatter_v2i64_truncstore_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i16: ; RV64-LABEL: mscatter_v2i64_truncstore_v2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i16> %tval = trunc <2 x i64> %val to <2 x i16>
call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>) declare void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>)
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, i32 4, <2 x i1> %m) call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, i32 4, <2 x i1> %m)
ret void ret void
} }
define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <2 x i1> %m) { define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i64_truncstore_v2i32: ; RV32-LABEL: mscatter_v2i64_truncstore_v2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i32: ; RV64-LABEL: mscatter_v2i64_truncstore_v2i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i32> %tval = trunc <2 x i64> %val to <2 x i32>
call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m) call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>) declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
▲ Show 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i64: ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v16, v12 ; RV32-NEXT: vsext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i64: ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64> %eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i64: ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v16, v12 ; RV32-NEXT: vzext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i64: ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf8 v16, v12 ; RV64-NEXT: vzext.vf8 v16, v12
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define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i64: ; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v16, v12 ; RV32-NEXT: vsext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i64: ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf4 v16, v12 ; RV64-NEXT: vsext.vf4 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64> %eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i64: ; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v16, v12 ; RV32-NEXT: vzext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i64: ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf4 v16, v12 ; RV64-NEXT: vzext.vf4 v16, v12
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define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8i64: ; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v16, v12 ; RV32-NEXT: vsext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8i64: ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf2 v16, v12 ; RV64-NEXT: vsext.vf2 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64> %eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8i64: ; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v16, v12 ; RV32-NEXT: vzext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8i64: ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v16, v12 ; RV64-NEXT: vzext.vf2 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64> %eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_v8i64: ; RV32-LABEL: mscatter_baseidx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_v8i64: ; RV64-LABEL: mscatter_baseidx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v12, v12, 3 ; RV64-NEXT: vsll.vi v12, v12, 3
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define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f64: ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v16, v12 ; RV32-NEXT: vsext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f64: ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64> %eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f64: ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v16, v12 ; RV32-NEXT: vzext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f64: ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf8 v16, v12 ; RV64-NEXT: vzext.vf8 v16, v12
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define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f64: ; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v16, v12 ; RV32-NEXT: vsext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f64: ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf4 v16, v12 ; RV64-NEXT: vsext.vf4 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64> %eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f64: ; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v16, v12 ; RV32-NEXT: vzext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f64: ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf4 v16, v12 ; RV64-NEXT: vzext.vf4 v16, v12
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define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8f64: ; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v16, v12 ; RV32-NEXT: vsext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8f64: ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf2 v16, v12 ; RV64-NEXT: vsext.vf2 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64> %eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8f64: ; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v16, v12 ; RV32-NEXT: vzext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8f64: ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v16, v12 ; RV64-NEXT: vzext.vf2 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64> %eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> %idxs, <8 x i1> %m) { define void @mscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> %idxs, <8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_v8f64: ; RV32-LABEL: mscatter_baseidx_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_v8f64: ; RV64-LABEL: mscatter_baseidx_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v12, v12, 3 ; RV64-NEXT: vsll.vi v12, v12, 3
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

Show First 20 Lines • Show All 959 Lines • ▼ Show 20 Lines
define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i64: ; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v12, v8 ; RV32-NEXT: vsext.vf8 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i64: ; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf8 v12, v8 ; RV64-NEXT: vsext.vf8 v12, v8
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define <8 x i64> @vpgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i64: ; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v12, v8 ; RV32-NEXT: vzext.vf8 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i64: ; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf8 v12, v8 ; RV64-NEXT: vzext.vf8 v12, v8
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define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i64: ; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v12, v8 ; RV32-NEXT: vsext.vf4 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i64: ; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf4 v12, v8 ; RV64-NEXT: vsext.vf4 v12, v8
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define <8 x i64> @vpgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i64: ; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v12, v8 ; RV32-NEXT: vzext.vf4 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i64: ; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf4 v12, v8 ; RV64-NEXT: vzext.vf4 v12, v8
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define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8i64: ; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v12, v8 ; RV32-NEXT: vsext.vf2 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8i64: ; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf2 v12, v8 ; RV64-NEXT: vsext.vf2 v12, v8
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define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8i64: ; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v12, v8 ; RV32-NEXT: vzext.vf2 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8i64: ; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v12, v8 ; RV64-NEXT: vzext.vf2 v12, v8
; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64> %eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
%v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vpgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v8i64: ; RV32-LABEL: vpgather_baseidx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v8i64: ; RV64-LABEL: vpgather_baseidx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
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define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f64: ; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v12, v8 ; RV32-NEXT: vsext.vf8 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f64: ; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf8 v12, v8 ; RV64-NEXT: vsext.vf8 v12, v8
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define <8 x double> @vpgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f64: ; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v12, v8 ; RV32-NEXT: vzext.vf8 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f64: ; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf8 v12, v8 ; RV64-NEXT: vzext.vf8 v12, v8
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define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f64: ; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v12, v8 ; RV32-NEXT: vsext.vf4 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f64: ; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf4 v12, v8 ; RV64-NEXT: vsext.vf4 v12, v8
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define <8 x double> @vpgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f64: ; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v12, v8 ; RV32-NEXT: vzext.vf4 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f64: ; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf4 v12, v8 ; RV64-NEXT: vzext.vf4 v12, v8
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define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8f64: ; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v12, v8 ; RV32-NEXT: vsext.vf2 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8f64: ; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf2 v12, v8 ; RV64-NEXT: vsext.vf2 v12, v8
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define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8f64: ; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v12, v8 ; RV32-NEXT: vzext.vf2 v12, v8
; RV32-NEXT: vsll.vi v8, v12, 3 ; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8f64: ; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v12, v8 ; RV64-NEXT: vzext.vf2 v12, v8
; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64> %eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
%v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x double> %v ret <8 x double> %v
} }
define <8 x double> @vpgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { define <8 x double> @vpgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v8f64: ; RV32-LABEL: vpgather_baseidx_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v12, v8, 0 ; RV32-NEXT: vnsrl.wx v12, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v8f64: ; RV64-LABEL: vpgather_baseidx_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB88_2: ; RV32-NEXT: .LBB88_2:
; RV32-NEXT: vsext.vf8 v24, v8 ; RV32-NEXT: vsext.vf8 v24, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v10, 2 ; RV32-NEXT: vslidedown.vi v0, v10, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v12, v16, 0 ; RV32-NEXT: vnsrl.wx v12, v16, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v12, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB88_4 ; RV32-NEXT: bltu a1, a2, .LBB88_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB88_4: ; RV32-NEXT: .LBB88_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v24, 0 ; RV32-NEXT: vnsrl.wx v4, v24, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: vmv1r.v v10, v0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB89_2: ; RV32-NEXT: .LBB89_2:
; RV32-NEXT: vzext.vf8 v24, v8 ; RV32-NEXT: vzext.vf8 v24, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v10, 2 ; RV32-NEXT: vslidedown.vi v0, v10, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v12, v16, 0 ; RV32-NEXT: vnsrl.wx v12, v16, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v12, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v12, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB89_4 ; RV32-NEXT: bltu a1, a2, .LBB89_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB89_4: ; RV32-NEXT: .LBB89_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v24, 0 ; RV32-NEXT: vnsrl.wx v4, v24, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: vmv1r.v v10, v0
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB91_2: ; RV32-NEXT: .LBB91_2:
; RV32-NEXT: vsext.vf4 v24, v8 ; RV32-NEXT: vsext.vf4 v24, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v12, 2 ; RV32-NEXT: vslidedown.vi v0, v12, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v16, 0 ; RV32-NEXT: vnsrl.wx v8, v16, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB91_4 ; RV32-NEXT: bltu a1, a2, .LBB91_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB91_4: ; RV32-NEXT: .LBB91_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v24, 0 ; RV32-NEXT: vnsrl.wx v4, v24, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB92_2: ; RV32-NEXT: .LBB92_2:
; RV32-NEXT: vzext.vf4 v24, v8 ; RV32-NEXT: vzext.vf4 v24, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v12, 2 ; RV32-NEXT: vslidedown.vi v0, v12, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v16, 0 ; RV32-NEXT: vnsrl.wx v8, v16, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB92_4 ; RV32-NEXT: bltu a1, a2, .LBB92_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB92_4: ; RV32-NEXT: .LBB92_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v24, 0 ; RV32-NEXT: vnsrl.wx v4, v24, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB94_2: ; RV32-NEXT: .LBB94_2:
; RV32-NEXT: vsext.vf2 v24, v8 ; RV32-NEXT: vsext.vf2 v24, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v1, 2 ; RV32-NEXT: vslidedown.vi v0, v1, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v8, 0 ; RV32-NEXT: vnsrl.wx v4, v8, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v4, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB94_4 ; RV32-NEXT: bltu a1, a2, .LBB94_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB94_4: ; RV32-NEXT: .LBB94_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v1, v0 ; RV64-NEXT: vmv1r.v v1, v0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB95_2: ; RV32-NEXT: .LBB95_2:
; RV32-NEXT: vzext.vf2 v24, v8 ; RV32-NEXT: vzext.vf2 v24, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v1, 2 ; RV32-NEXT: vslidedown.vi v0, v1, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v8, 0 ; RV32-NEXT: vnsrl.wx v4, v8, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v4, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB95_4 ; RV32-NEXT: bltu a1, a2, .LBB95_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB95_4: ; RV32-NEXT: .LBB95_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v1, v0 ; RV64-NEXT: vmv1r.v v1, v0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a2, a3 ; RV32-NEXT: mv a2, a3
; RV32-NEXT: .LBB96_2: ; RV32-NEXT: .LBB96_2:
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v24, 2 ; RV32-NEXT: vslidedown.vi v0, v24, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v28, v16, 0 ; RV32-NEXT: vnsrl.wx v28, v16, zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB96_4 ; RV32-NEXT: bltu a1, a2, .LBB96_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB96_4: ; RV32-NEXT: .LBB96_4:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v28, v8, 0 ; RV32-NEXT: vnsrl.wx v28, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32f64: ; RV64-LABEL: vpgather_baseidx_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi a3, a1, -16 ; RV64-NEXT: addi a3, a1, -16
Show All 27 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

Show All 20 Lines; RV64-NEXT: ret
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_v2i16_truncstore_v2i8: ; RV32-LABEL: vpscatter_v2i16_truncstore_v2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v2i16_truncstore_v2i8: ; RV64-LABEL: vpscatter_v2i16_truncstore_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i16> %val to <2 x i8> %tval = trunc <2 x i16> %val to <2 x i8>
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_v2i32_truncstore_v2i8: ; RV32-LABEL: vpscatter_v2i32_truncstore_v2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v2i32_truncstore_v2i8: ; RV64-LABEL: vpscatter_v2i32_truncstore_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i8> %tval = trunc <2 x i32> %val to <2 x i8>
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_v2i64_truncstore_v2i8: ; RV32-LABEL: vpscatter_v2i64_truncstore_v2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v2i64_truncstore_v2i8: ; RV64-LABEL: vpscatter_v2i64_truncstore_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i8> %tval = trunc <2 x i64> %val to <2 x i8>
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %val, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %val, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_v2i32_truncstore_v2i16: ; RV32-LABEL: vpscatter_v2i32_truncstore_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v2i32_truncstore_v2i16: ; RV64-LABEL: vpscatter_v2i32_truncstore_v2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i16> %tval = trunc <2 x i32> %val to <2 x i16>
call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_v2i64_truncstore_v2i16: ; RV32-LABEL: vpscatter_v2i64_truncstore_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v2i64_truncstore_v2i16: ; RV64-LABEL: vpscatter_v2i64_truncstore_v2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i16> %tval = trunc <2 x i64> %val to <2 x i16>
call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.vp.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i32.v2p0i32(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_v2i64_truncstore_v2i32: ; RV32-LABEL: vpscatter_v2i64_truncstore_v2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v2i64_truncstore_v2i32: ; RV64-LABEL: vpscatter_v2i64_truncstore_v2i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i32> %tval = trunc <2 x i64> %val to <2 x i32>
call void @llvm.vp.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, <2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, <2 x i1> %m, i32 %evl)
ret void ret void
} }
▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
define void @vpscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i64: ; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v16, v12 ; RV32-NEXT: vsext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i64: ; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v12
Show All 9 Lines
define void @vpscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i64: ; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v16, v12 ; RV32-NEXT: vzext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i64: ; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf8 v16, v12 ; RV64-NEXT: vzext.vf8 v16, v12
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define void @vpscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8i64: ; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v16, v12 ; RV32-NEXT: vsext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8i64: ; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf4 v16, v12 ; RV64-NEXT: vsext.vf4 v16, v12
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define void @vpscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8i64: ; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v16, v12 ; RV32-NEXT: vzext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8i64: ; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf4 v16, v12 ; RV64-NEXT: vzext.vf4 v16, v12
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define void @vpscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_v8i32_v8i64: ; RV32-LABEL: vpscatter_baseidx_sext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v16, v12 ; RV32-NEXT: vsext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v8i32_v8i64: ; RV64-LABEL: vpscatter_baseidx_sext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf2 v16, v12 ; RV64-NEXT: vsext.vf2 v16, v12
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define void @vpscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_v8i32_v8i64: ; RV32-LABEL: vpscatter_baseidx_zext_v8i32_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v16, v12 ; RV32-NEXT: vzext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v8i32_v8i64: ; RV64-LABEL: vpscatter_baseidx_zext_v8i32_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v16, v12 ; RV64-NEXT: vzext.vf2 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64> %eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_v8i64: ; RV32-LABEL: vpscatter_baseidx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_v8i64: ; RV64-LABEL: vpscatter_baseidx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v12, v12, 3 ; RV64-NEXT: vsll.vi v12, v12, 3
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define void @vpscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f64: ; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf8 v16, v12 ; RV32-NEXT: vsext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f64: ; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v12
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define void @vpscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f64: ; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf8 v16, v12 ; RV32-NEXT: vzext.vf8 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f64: ; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf8 v16, v12 ; RV64-NEXT: vzext.vf8 v16, v12
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define void @vpscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8f64: ; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf4 v16, v12 ; RV32-NEXT: vsext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8f64: ; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf4 v16, v12 ; RV64-NEXT: vsext.vf4 v16, v12
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define void @vpscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8f64: ; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf4 v16, v12 ; RV32-NEXT: vzext.vf4 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8f64: ; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf4 v16, v12 ; RV64-NEXT: vzext.vf4 v16, v12
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define void @vpscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_v8i32_v8f64: ; RV32-LABEL: vpscatter_baseidx_sext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsext.vf2 v16, v12 ; RV32-NEXT: vsext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v8i32_v8f64: ; RV64-LABEL: vpscatter_baseidx_sext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsext.vf2 v16, v12 ; RV64-NEXT: vsext.vf2 v16, v12
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define void @vpscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_v8i32_v8f64: ; RV32-LABEL: vpscatter_baseidx_zext_v8i32_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vzext.vf2 v16, v12 ; RV32-NEXT: vzext.vf2 v16, v12
; RV32-NEXT: vsll.vi v12, v16, 3 ; RV32-NEXT: vsll.vi v12, v16, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v8i32_v8f64: ; RV64-LABEL: vpscatter_baseidx_zext_v8i32_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v16, v12 ; RV64-NEXT: vzext.vf2 v16, v12
; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64> %eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_v8f64: ; RV32-LABEL: vpscatter_baseidx_v8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v16, v12, 0 ; RV32-NEXT: vnsrl.wx v16, v12, zero
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_v8f64: ; RV64-LABEL: vpscatter_baseidx_v8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v12, v12, 3 ; RV64-NEXT: vsll.vi v12, v12, 3
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; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB81_2: ; RV32-NEXT: .LBB81_2:
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8re8.v v24, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsext.vf2 v16, v24 ; RV32-NEXT: vsext.vf2 v16, v24
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: addi a1, a2, -16 ; RV32-NEXT: addi a1, a2, -16
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3 ; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8re8.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: bltu a2, a1, .LBB81_4 ; RV32-NEXT: bltu a2, a1, .LBB81_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: mv a3, a1 ; RV32-NEXT: mv a3, a1
; RV32-NEXT: .LBB81_4: ; RV32-NEXT: .LBB81_4:
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB82_2: ; RV32-NEXT: .LBB82_2:
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8re8.v v24, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vzext.vf2 v16, v24 ; RV32-NEXT: vzext.vf2 v16, v24
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: addi a1, a2, -16 ; RV32-NEXT: addi a1, a2, -16
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3 ; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8re8.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: bltu a2, a1, .LBB82_4 ; RV32-NEXT: bltu a2, a1, .LBB82_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: mv a3, a1 ; RV32-NEXT: mv a3, a1
; RV32-NEXT: .LBB82_4: ; RV32-NEXT: .LBB82_4:
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
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llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 4 x i5> @trunc_nxv4i32_to_nxv4i5(<vscale x 4 x i32> %a) { define <vscale x 4 x i5> @trunc_nxv4i32_to_nxv4i5(<vscale x 4 x i32> %a) {
; CHECK-LABEL: trunc_nxv4i32_to_nxv4i5: ; CHECK-LABEL: trunc_nxv4i32_to_nxv4i5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = trunc <vscale x 4 x i32> %a to <vscale x 4 x i5> %v = trunc <vscale x 4 x i32> %a to <vscale x 4 x i5>
ret <vscale x 4 x i5> %v ret <vscale x 4 x i5> %v
} }
define <vscale x 1 x i5> @trunc_nxv1i32_to_nxv1i5(<vscale x 1 x i32> %a) { define <vscale x 1 x i5> @trunc_nxv1i32_to_nxv1i5(<vscale x 1 x i32> %a) {
; CHECK-LABEL: trunc_nxv1i32_to_nxv1i5: ; CHECK-LABEL: trunc_nxv1i32_to_nxv1i5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = trunc <vscale x 1 x i32> %a to <vscale x 1 x i5> %v = trunc <vscale x 1 x i32> %a to <vscale x 1 x i5>
ret <vscale x 1 x i5> %v ret <vscale x 1 x i5> %v
} }

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

Show First 20 Lines • Show All 1,037 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i64: ; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v8 ; RV32-NEXT: vsext.vf8 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i64: ; RV64-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 10 Lines
define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i64: ; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v8 ; RV32-NEXT: vzext.vf8 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i64: ; RV64-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 34 Lines
define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8i64: ; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v8 ; RV32-NEXT: vsext.vf4 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_nxv8i16_nxv8i64: ; RV64-LABEL: mgather_baseidx_sext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 10 Lines
define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8i64: ; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v8 ; RV32-NEXT: vzext.vf4 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_nxv8i16_nxv8i64: ; RV64-LABEL: mgather_baseidx_zext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 33 Lines
define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_nxv8i32_nxv8i64: ; RV32-LABEL: mgather_baseidx_sext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v8 ; RV32-NEXT: vsext.vf2 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_nxv8i32_nxv8i64: ; RV64-LABEL: mgather_baseidx_sext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_nxv8i32_nxv8i64: ; RV32-LABEL: mgather_baseidx_zext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v8 ; RV32-NEXT: vzext.vf2 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_nxv8i32_nxv8i64: ; RV64-LABEL: mgather_baseidx_zext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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} }
define <vscale x 8 x i64> @mgather_baseidx_nxv8i64(i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) { define <vscale x 8 x i64> @mgather_baseidx_nxv8i64(i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) {
; RV32-LABEL: mgather_baseidx_nxv8i64: ; RV32-LABEL: mgather_baseidx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv8i64: ; RV64-LABEL: mgather_baseidx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f64: ; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v8 ; RV32-NEXT: vsext.vf8 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f64: ; RV64-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f64: ; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v8 ; RV32-NEXT: vzext.vf8 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f64: ; RV64-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8f64: ; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v8 ; RV32-NEXT: vsext.vf4 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_nxv8i16_nxv8f64: ; RV64-LABEL: mgather_baseidx_sext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8f64: ; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v8 ; RV32-NEXT: vzext.vf4 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_nxv8i16_nxv8f64: ; RV64-LABEL: mgather_baseidx_zext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_sext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_sext_nxv8i32_nxv8f64: ; RV32-LABEL: mgather_baseidx_sext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v8 ; RV32-NEXT: vsext.vf2 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_sext_nxv8i32_nxv8f64: ; RV64-LABEL: mgather_baseidx_sext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_zext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_zext_nxv8i32_nxv8f64: ; RV32-LABEL: mgather_baseidx_zext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v8 ; RV32-NEXT: vzext.vf2 v24, v8
; RV32-NEXT: vsll.vi v8, v24, 3 ; RV32-NEXT: vsll.vi v8, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_zext_nxv8i32_nxv8f64: ; RV64-LABEL: mgather_baseidx_zext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
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} }
define <vscale x 8 x double> @mgather_baseidx_nxv8f64(double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) { define <vscale x 8 x double> @mgather_baseidx_nxv8f64(double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x double> %passthru) {
; RV32-LABEL: mgather_baseidx_nxv8f64: ; RV32-LABEL: mgather_baseidx_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv8f64: ; RV64-LABEL: mgather_baseidx_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

Show All 38 Lines; RV64-NEXT: ret
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %val, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %val, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
ret void ret void
} }
define void @mscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m) { define void @mscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m) {
; RV32-LABEL: mscatter_nxv2i16_truncstore_nxv2i8: ; RV32-LABEL: mscatter_nxv2i16_truncstore_nxv2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_nxv2i16_truncstore_nxv2i8: ; RV64-LABEL: mscatter_nxv2i16_truncstore_nxv2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i16> %val to <vscale x 2 x i8> %tval = trunc <vscale x 2 x i16> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
ret void ret void
} }
define void @mscatter_nxv2i32_truncstore_nxv2i8(<vscale x 2 x i32> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m) { define void @mscatter_nxv2i32_truncstore_nxv2i8(<vscale x 2 x i32> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m) {
; RV32-LABEL: mscatter_nxv2i32_truncstore_nxv2i8: ; RV32-LABEL: mscatter_nxv2i32_truncstore_nxv2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i8: ; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8> %tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
ret void ret void
} }
define void @mscatter_nxv2i64_truncstore_nxv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m) { define void @mscatter_nxv2i64_truncstore_nxv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m) {
; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i8: ; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v11, v8, 0 ; RV32-NEXT: vnsrl.wx v11, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v11, 0 ; RV32-NEXT: vnsrl.wx v8, v11, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i8: ; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v12, v8, 0 ; RV64-NEXT: vnsrl.wx v12, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v12, 0 ; RV64-NEXT: vnsrl.wx v8, v12, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8> %tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.nxv4i8.nxv4p0i8(<vscale x 4 x i8>, <vscale x 4 x i8*>, i32, <vscale x 4 x i1>) declare void @llvm.masked.scatter.nxv4i8.nxv4p0i8(<vscale x 4 x i8>, <vscale x 4 x i8*>, i32, <vscale x 4 x i1>)
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %val, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %val, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m)
ret void ret void
} }
define void @mscatter_nxv2i32_truncstore_nxv2i16(<vscale x 2 x i32> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m) { define void @mscatter_nxv2i32_truncstore_nxv2i16(<vscale x 2 x i32> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m) {
; RV32-LABEL: mscatter_nxv2i32_truncstore_nxv2i16: ; RV32-LABEL: mscatter_nxv2i32_truncstore_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i16: ; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i16> %tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i16>
call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m)
ret void ret void
} }
define void @mscatter_nxv2i64_truncstore_nxv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m) { define void @mscatter_nxv2i64_truncstore_nxv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m) {
; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i16: ; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v11, v8, 0 ; RV32-NEXT: vnsrl.wx v11, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v11, 0 ; RV32-NEXT: vnsrl.wx v8, v11, zero
; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i16: ; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v12, v8, 0 ; RV64-NEXT: vnsrl.wx v12, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v12, 0 ; RV64-NEXT: vnsrl.wx v8, v12, zero
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16> %tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.nxv4i16.nxv4p0i16(<vscale x 4 x i16>, <vscale x 4 x i16*>, i32, <vscale x 4 x i1>) declare void @llvm.masked.scatter.nxv4i16.nxv4p0i16(<vscale x 4 x i16>, <vscale x 4 x i16*>, i32, <vscale x 4 x i1>)
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.masked.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %val, <vscale x 2 x i32*> %ptrs, i32 4, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %val, <vscale x 2 x i32*> %ptrs, i32 4, <vscale x 2 x i1> %m)
ret void ret void
} }
define void @mscatter_nxv2i64_truncstore_nxv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m) { define void @mscatter_nxv2i64_truncstore_nxv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m) {
; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i32: ; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v11, v8, 0 ; RV32-NEXT: vnsrl.wx v11, v8, zero
; RV32-NEXT: vsoxei32.v v11, (zero), v10, v0.t ; RV32-NEXT: vsoxei32.v v11, (zero), v10, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i32: ; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v12, v8, 0 ; RV64-NEXT: vnsrl.wx v12, v8, zero
; RV64-NEXT: vsoxei64.v v12, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v12, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32> %tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32>
call void @llvm.masked.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %tval, <vscale x 2 x i32*> %ptrs, i32 4, <vscale x 2 x i1> %m) call void @llvm.masked.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %tval, <vscale x 2 x i32*> %ptrs, i32 4, <vscale x 2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32>, <vscale x 4 x i32*>, i32, <vscale x 4 x i1>) declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32>, <vscale x 4 x i32*>, i32, <vscale x 4 x i1>)
▲ Show 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
define void @mscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i64: ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i64: ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsext.vf8 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i64: ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vzext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i64: ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v24, v16 ; RV64-NEXT: vzext.vf8 v24, v16
Show All 30 Lines
define void @mscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i64: ; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i64: ; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i64: ; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vzext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i64: ; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v24, v16 ; RV64-NEXT: vzext.vf4 v24, v16
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define void @mscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8i64: ; RV32-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8i64: ; RV64-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v24, v16 ; RV64-NEXT: vsext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8i64: ; RV32-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vzext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8i64: ; RV64-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v24, v16 ; RV64-NEXT: vzext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_nxv8i64: ; RV32-LABEL: mscatter_baseidx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_nxv8i64: ; RV64-LABEL: mscatter_baseidx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
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define void @mscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f64: ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f64: ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsext.vf8 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64> %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f64: ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vzext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f64: ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v24, v16 ; RV64-NEXT: vzext.vf8 v24, v16
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define void @mscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f64: ; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f64: ; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64> %eidxs = sext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f64: ; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vzext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f64: ; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v24, v16 ; RV64-NEXT: vzext.vf4 v24, v16
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define void @mscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8f64: ; RV32-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8f64: ; RV64-LABEL: mscatter_baseidx_sext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v24, v16 ; RV64-NEXT: vsext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = sext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8f64: ; RV32-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vzext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8f64: ; RV64-LABEL: mscatter_baseidx_zext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v24, v16 ; RV64-NEXT: vzext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs
call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m) { define void @mscatter_baseidx_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_nxv8f64: ; RV32-LABEL: mscatter_baseidx_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mscatter_baseidx_nxv8f64: ; RV64-LABEL: mscatter_baseidx_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
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llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll

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} }
define <vscale x 1 x i8> @vfptosi_nxv1f32_nxv1i8(<vscale x 1 x float> %va) { define <vscale x 1 x i8> @vfptosi_nxv1f32_nxv1i8(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptosi_nxv1f32_nxv1i8: ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i8> %evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec ret <vscale x 1 x i8> %evec
} }
define <vscale x 1 x i8> @vfptoui_nxv1f32_nxv1i8(<vscale x 1 x float> %va) { define <vscale x 1 x i8> @vfptoui_nxv1f32_nxv1i8(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptoui_nxv1f32_nxv1i8: ; CHECK-LABEL: vfptoui_nxv1f32_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i8> %evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec ret <vscale x 1 x i8> %evec
} }
define <vscale x 1 x i16> @vfptosi_nxv1f32_nxv1i16(<vscale x 1 x float> %va) { define <vscale x 1 x i16> @vfptosi_nxv1f32_nxv1i16(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptosi_nxv1f32_nxv1i16: ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 2 x i8> @vfptosi_nxv2f32_nxv2i8(<vscale x 2 x float> %va) { define <vscale x 2 x i8> @vfptosi_nxv2f32_nxv2i8(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptosi_nxv2f32_nxv2i8: ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i8> %evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec ret <vscale x 2 x i8> %evec
} }
define <vscale x 2 x i8> @vfptoui_nxv2f32_nxv2i8(<vscale x 2 x float> %va) { define <vscale x 2 x i8> @vfptoui_nxv2f32_nxv2i8(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptoui_nxv2f32_nxv2i8: ; CHECK-LABEL: vfptoui_nxv2f32_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i8> %evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec ret <vscale x 2 x i8> %evec
} }
define <vscale x 2 x i16> @vfptosi_nxv2f32_nxv2i16(<vscale x 2 x float> %va) { define <vscale x 2 x i16> @vfptosi_nxv2f32_nxv2i16(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptosi_nxv2f32_nxv2i16: ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 4 x i8> @vfptosi_nxv4f32_nxv4i8(<vscale x 4 x float> %va) { define <vscale x 4 x i8> @vfptosi_nxv4f32_nxv4i8(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptosi_nxv4f32_nxv4i8: ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i8> %evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec ret <vscale x 4 x i8> %evec
} }
define <vscale x 4 x i8> @vfptoui_nxv4f32_nxv4i8(<vscale x 4 x float> %va) { define <vscale x 4 x i8> @vfptoui_nxv4f32_nxv4i8(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptoui_nxv4f32_nxv4i8: ; CHECK-LABEL: vfptoui_nxv4f32_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i8> %evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec ret <vscale x 4 x i8> %evec
} }
define <vscale x 4 x i16> @vfptosi_nxv4f32_nxv4i16(<vscale x 4 x float> %va) { define <vscale x 4 x i16> @vfptosi_nxv4f32_nxv4i16(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptosi_nxv4f32_nxv4i16: ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 8 x i8> @vfptosi_nxv8f32_nxv8i8(<vscale x 8 x float> %va) { define <vscale x 8 x i8> @vfptosi_nxv8f32_nxv8i8(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptosi_nxv8f32_nxv8i8: ; CHECK-LABEL: vfptosi_nxv8f32_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x float> %va to <vscale x 8 x i8> %evec = fptosi <vscale x 8 x float> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec ret <vscale x 8 x i8> %evec
} }
define <vscale x 8 x i8> @vfptoui_nxv8f32_nxv8i8(<vscale x 8 x float> %va) { define <vscale x 8 x i8> @vfptoui_nxv8f32_nxv8i8(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptoui_nxv8f32_nxv8i8: ; CHECK-LABEL: vfptoui_nxv8f32_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x float> %va to <vscale x 8 x i8> %evec = fptoui <vscale x 8 x float> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec ret <vscale x 8 x i8> %evec
} }
define <vscale x 8 x i16> @vfptosi_nxv8f32_nxv8i16(<vscale x 8 x float> %va) { define <vscale x 8 x i16> @vfptosi_nxv8f32_nxv8i16(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptosi_nxv8f32_nxv8i16: ; CHECK-LABEL: vfptosi_nxv8f32_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 16 x i8> @vfptosi_nxv16f32_nxv16i8(<vscale x 16 x float> %va) { define <vscale x 16 x i8> @vfptosi_nxv16f32_nxv16i8(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptosi_nxv16f32_nxv16i8: ; CHECK-LABEL: vfptosi_nxv16f32_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x float> %va to <vscale x 16 x i8> %evec = fptosi <vscale x 16 x float> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec ret <vscale x 16 x i8> %evec
} }
define <vscale x 16 x i8> @vfptoui_nxv16f32_nxv16i8(<vscale x 16 x float> %va) { define <vscale x 16 x i8> @vfptoui_nxv16f32_nxv16i8(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptoui_nxv16f32_nxv16i8: ; CHECK-LABEL: vfptoui_nxv16f32_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x float> %va to <vscale x 16 x i8> %evec = fptoui <vscale x 16 x float> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec ret <vscale x 16 x i8> %evec
} }
define <vscale x 16 x i16> @vfptosi_nxv16f32_nxv16i16(<vscale x 16 x float> %va) { define <vscale x 16 x i16> @vfptosi_nxv16f32_nxv16i16(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptosi_nxv16f32_nxv16i16: ; CHECK-LABEL: vfptosi_nxv16f32_nxv16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 1 x i8> @vfptosi_nxv1f64_nxv1i8(<vscale x 1 x double> %va) { define <vscale x 1 x i8> @vfptosi_nxv1f64_nxv1i8(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i8: ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i8> %evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec ret <vscale x 1 x i8> %evec
} }
define <vscale x 1 x i8> @vfptoui_nxv1f64_nxv1i8(<vscale x 1 x double> %va) { define <vscale x 1 x i8> @vfptoui_nxv1f64_nxv1i8(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptoui_nxv1f64_nxv1i8: ; CHECK-LABEL: vfptoui_nxv1f64_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i8> %evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec ret <vscale x 1 x i8> %evec
} }
define <vscale x 1 x i16> @vfptosi_nxv1f64_nxv1i16(<vscale x 1 x double> %va) { define <vscale x 1 x i16> @vfptosi_nxv1f64_nxv1i16(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i16: ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i16> %evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec ret <vscale x 1 x i16> %evec
} }
define <vscale x 1 x i16> @vfptoui_nxv1f64_nxv1i16(<vscale x 1 x double> %va) { define <vscale x 1 x i16> @vfptoui_nxv1f64_nxv1i16(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptoui_nxv1f64_nxv1i16: ; CHECK-LABEL: vfptoui_nxv1f64_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vnsrl.wx v8, v9, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i16> %evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec ret <vscale x 1 x i16> %evec
} }
define <vscale x 1 x i32> @vfptosi_nxv1f64_nxv1i32(<vscale x 1 x double> %va) { define <vscale x 1 x i32> @vfptosi_nxv1f64_nxv1i32(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i32: ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 2 x i8> @vfptosi_nxv2f64_nxv2i8(<vscale x 2 x double> %va) { define <vscale x 2 x i8> @vfptosi_nxv2f64_nxv2i8(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i8: ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i8> %evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec ret <vscale x 2 x i8> %evec
} }
define <vscale x 2 x i8> @vfptoui_nxv2f64_nxv2i8(<vscale x 2 x double> %va) { define <vscale x 2 x i8> @vfptoui_nxv2f64_nxv2i8(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptoui_nxv2f64_nxv2i8: ; CHECK-LABEL: vfptoui_nxv2f64_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i8> %evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec ret <vscale x 2 x i8> %evec
} }
define <vscale x 2 x i16> @vfptosi_nxv2f64_nxv2i16(<vscale x 2 x double> %va) { define <vscale x 2 x i16> @vfptosi_nxv2f64_nxv2i16(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i16: ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i16> %evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec ret <vscale x 2 x i16> %evec
} }
define <vscale x 2 x i16> @vfptoui_nxv2f64_nxv2i16(<vscale x 2 x double> %va) { define <vscale x 2 x i16> @vfptoui_nxv2f64_nxv2i16(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptoui_nxv2f64_nxv2i16: ; CHECK-LABEL: vfptoui_nxv2f64_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i16> %evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec ret <vscale x 2 x i16> %evec
} }
define <vscale x 2 x i32> @vfptosi_nxv2f64_nxv2i32(<vscale x 2 x double> %va) { define <vscale x 2 x i32> @vfptosi_nxv2f64_nxv2i32(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i32: ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 4 x i8> @vfptosi_nxv4f64_nxv4i8(<vscale x 4 x double> %va) { define <vscale x 4 x i8> @vfptosi_nxv4f64_nxv4i8(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i8: ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i8> %evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec ret <vscale x 4 x i8> %evec
} }
define <vscale x 4 x i8> @vfptoui_nxv4f64_nxv4i8(<vscale x 4 x double> %va) { define <vscale x 4 x i8> @vfptoui_nxv4f64_nxv4i8(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptoui_nxv4f64_nxv4i8: ; CHECK-LABEL: vfptoui_nxv4f64_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i8> %evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec ret <vscale x 4 x i8> %evec
} }
define <vscale x 4 x i16> @vfptosi_nxv4f64_nxv4i16(<vscale x 4 x double> %va) { define <vscale x 4 x i16> @vfptosi_nxv4f64_nxv4i16(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i16: ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i16> %evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec ret <vscale x 4 x i16> %evec
} }
define <vscale x 4 x i16> @vfptoui_nxv4f64_nxv4i16(<vscale x 4 x double> %va) { define <vscale x 4 x i16> @vfptoui_nxv4f64_nxv4i16(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptoui_nxv4f64_nxv4i16: ; CHECK-LABEL: vfptoui_nxv4f64_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i16> %evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec ret <vscale x 4 x i16> %evec
} }
define <vscale x 4 x i32> @vfptosi_nxv4f64_nxv4i32(<vscale x 4 x double> %va) { define <vscale x 4 x i32> @vfptosi_nxv4f64_nxv4i32(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i32: ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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} }
define <vscale x 8 x i8> @vfptosi_nxv8f64_nxv8i8(<vscale x 8 x double> %va) { define <vscale x 8 x i8> @vfptosi_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i8: ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vnsrl.wx v10, v16, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i8> %evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec ret <vscale x 8 x i8> %evec
} }
define <vscale x 8 x i8> @vfptoui_nxv8f64_nxv8i8(<vscale x 8 x double> %va) { define <vscale x 8 x i8> @vfptoui_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptoui_nxv8f64_nxv8i8: ; CHECK-LABEL: vfptoui_nxv8f64_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vnsrl.wx v10, v16, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i8> %evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec ret <vscale x 8 x i8> %evec
} }
define <vscale x 8 x i16> @vfptosi_nxv8f64_nxv8i16(<vscale x 8 x double> %va) { define <vscale x 8 x i16> @vfptosi_nxv8f64_nxv8i16(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i16: ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i16> %evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec ret <vscale x 8 x i16> %evec
} }
define <vscale x 8 x i16> @vfptoui_nxv8f64_nxv8i16(<vscale x 8 x double> %va) { define <vscale x 8 x i16> @vfptoui_nxv8f64_nxv8i16(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptoui_nxv8f64_nxv8i16: ; CHECK-LABEL: vfptoui_nxv8f64_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i16> %evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec ret <vscale x 8 x i16> %evec
} }
define <vscale x 8 x i32> @vfptosi_nxv8f64_nxv8i32(<vscale x 8 x double> %va) { define <vscale x 8 x i32> @vfptosi_nxv8f64_nxv8i32(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i32: ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

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define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64: ; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64: ; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v8
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define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i8_nxv8i64(i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64: ; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vzext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64: ; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v16, v8 ; RV64-NEXT: vzext.vf8 v16, v8
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define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64: ; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64: ; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i16_nxv8i64(i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64: ; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64: ; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v16, v8 ; RV64-NEXT: vzext.vf4 v16, v8
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define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64: ; RV32-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64: ; RV64-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v16, v8 ; RV64-NEXT: vsext.vf2 v16, v8
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define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i32_nxv8i64(i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64: ; RV32-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64: ; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v16, v8 ; RV64-NEXT: vzext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3 ; RV64-NEXT: vsll.vi v8, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vpgather_baseidx_nxv8i64(i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpgather_baseidx_nxv8i64(i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_nxv8i64: ; RV32-LABEL: vpgather_baseidx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_nxv8i64: ; RV64-LABEL: vpgather_baseidx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
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define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i8_nxv6f64(double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i8_nxv6f64(double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv6i8_nxv6f64: ; RV32-LABEL: vpgather_baseidx_sext_nxv6i8_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv6i8_nxv6f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv6i8_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v8
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define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i8_nxv6f64(double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i8_nxv6f64(double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64: ; RV32-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vzext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v16, v8 ; RV64-NEXT: vzext.vf8 v16, v8
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define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i16_nxv6f64(double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i16_nxv6f64(double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv6i16_nxv6f64: ; RV32-LABEL: vpgather_baseidx_sext_nxv6i16_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv6i16_nxv6f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv6i16_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i16_nxv6f64(double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i16_nxv6f64(double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64: ; RV32-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v16, v8 ; RV64-NEXT: vzext.vf4 v16, v8
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define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i32_nxv6f64(double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i32_nxv6f64(double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv6i32_nxv6f64: ; RV32-LABEL: vpgather_baseidx_sext_nxv6i32_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv6i32_nxv6f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv6i32_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v16, v8 ; RV64-NEXT: vsext.vf2 v16, v8
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define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i32_nxv6f64(double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i32_nxv6f64(double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64: ; RV32-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v16, v8 ; RV64-NEXT: vzext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3 ; RV64-NEXT: vsll.vi v8, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 6 x i32> %idxs to <vscale x 6 x i64> %eidxs = zext <vscale x 6 x i32> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 6 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 6 x i64> %eidxs
%v = call <vscale x 6 x double> @llvm.vp.gather.nxv6f64.nxv6p0f64(<vscale x 6 x double*> %ptrs, <vscale x 6 x i1> %m, i32 %evl) %v = call <vscale x 6 x double> @llvm.vp.gather.nxv6f64.nxv6p0f64(<vscale x 6 x double*> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
ret <vscale x 6 x double> %v ret <vscale x 6 x double> %v
} }
define <vscale x 6 x double> @vpgather_baseidx_nxv6f64(double* %base, <vscale x 6 x i64> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define <vscale x 6 x double> @vpgather_baseidx_nxv6f64(double* %base, <vscale x 6 x i64> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_nxv6f64: ; RV32-LABEL: vpgather_baseidx_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_nxv6f64: ; RV64-LABEL: vpgather_baseidx_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
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define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64: ; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v16, v8 ; RV32-NEXT: vsext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v8
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define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i8_nxv8f64(double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64: ; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v16, v8 ; RV32-NEXT: vzext.vf8 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v16, v8 ; RV64-NEXT: vzext.vf8 v16, v8
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define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64: ; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
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define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i16_nxv8f64(double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64: ; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v16, v8 ; RV64-NEXT: vzext.vf4 v16, v8
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define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64: ; RV32-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v16, v8 ; RV64-NEXT: vsext.vf2 v16, v8
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define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i32_nxv8f64(double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64: ; RV32-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v16, v8 ; RV64-NEXT: vzext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3 ; RV64-NEXT: vsll.vi v8, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0f64(<vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x double> %v ret <vscale x 8 x double> %v
} }
define <vscale x 8 x double> @vpgather_baseidx_nxv8f64(double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x double> @vpgather_baseidx_nxv8f64(double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_nxv8f64: ; RV32-LABEL: vpgather_baseidx_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_nxv8f64: ; RV64-LABEL: vpgather_baseidx_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
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; RV32-NEXT: bltu a1, a4, .LBB104_2 ; RV32-NEXT: bltu a1, a4, .LBB104_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a3, a4 ; RV32-NEXT: mv a3, a4
; RV32-NEXT: .LBB104_2: ; RV32-NEXT: .LBB104_2:
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v8 ; RV32-NEXT: vsext.vf4 v24, v8
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v16, 0 ; RV32-NEXT: vnsrl.wx v8, v16, zero
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: bltu a1, a2, .LBB104_4 ; RV32-NEXT: bltu a1, a2, .LBB104_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a2
; RV32-NEXT: .LBB104_4: ; RV32-NEXT: .LBB104_4:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v24, 0 ; RV32-NEXT: vnsrl.wx v4, v24, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_nxv16i16_nxv16f64: ; RV64-LABEL: vpgather_baseidx_sext_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; RV32-NEXT: bltu a1, a4, .LBB105_2 ; RV32-NEXT: bltu a1, a4, .LBB105_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a3, a4 ; RV32-NEXT: mv a3, a4
; RV32-NEXT: .LBB105_2: ; RV32-NEXT: .LBB105_2:
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v8 ; RV32-NEXT: vzext.vf4 v24, v8
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v16, 0 ; RV32-NEXT: vnsrl.wx v8, v16, zero
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: bltu a1, a2, .LBB105_4 ; RV32-NEXT: bltu a1, a2, .LBB105_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a2
; RV32-NEXT: .LBB105_4: ; RV32-NEXT: .LBB105_4:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v4, v24, 0 ; RV32-NEXT: vnsrl.wx v4, v24, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v4, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64: ; RV64-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
Show All 32 Lines

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

Show All 38 Lines; RV64-NEXT: ret
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8: ; RV32-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8: ; RV64-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i16> %val to <vscale x 2 x i8> %tval = trunc <vscale x 2 x i16> %val to <vscale x 2 x i8>
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_nxv2i32_truncstore_nxv2i8(<vscale x 2 x i32> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_nxv2i32_truncstore_nxv2i8(<vscale x 2 x i32> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv2i32_truncstore_nxv2i8: ; RV32-LABEL: vpscatter_nxv2i32_truncstore_nxv2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_nxv2i32_truncstore_nxv2i8: ; RV64-LABEL: vpscatter_nxv2i32_truncstore_nxv2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8> %tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8>
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_nxv2i64_truncstore_nxv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_nxv2i64_truncstore_nxv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i8: ; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v11, v8, 0 ; RV32-NEXT: vnsrl.wx v11, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v11, 0 ; RV32-NEXT: vnsrl.wx v8, v11, zero
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i8: ; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v12, v8, 0 ; RV64-NEXT: vnsrl.wx v12, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v12, 0 ; RV64-NEXT: vnsrl.wx v8, v12, zero
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8> %tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_nxv2i32_truncstore_nxv2i16(<vscale x 2 x i32> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_nxv2i32_truncstore_nxv2i16(<vscale x 2 x i32> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv2i32_truncstore_nxv2i16: ; RV32-LABEL: vpscatter_nxv2i32_truncstore_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vnsrl.wx v8, v8, zero
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_nxv2i32_truncstore_nxv2i16: ; RV64-LABEL: vpscatter_nxv2i32_truncstore_nxv2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vnsrl.wx v8, v8, zero
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i16> %tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i16>
call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_nxv2i64_truncstore_nxv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_nxv2i64_truncstore_nxv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i16: ; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v11, v8, 0 ; RV32-NEXT: vnsrl.wx v11, v8, zero
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v11, 0 ; RV32-NEXT: vnsrl.wx v8, v11, zero
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i16: ; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v12, v8, 0 ; RV64-NEXT: vnsrl.wx v12, v8, zero
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v12, 0 ; RV64-NEXT: vnsrl.wx v8, v12, zero
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16> %tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
call void @llvm.vp.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %val, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %val, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_nxv2i64_truncstore_nxv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) { define void @vpscatter_nxv2i64_truncstore_nxv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i32: ; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v11, v8, 0 ; RV32-NEXT: vnsrl.wx v11, v8, zero
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; RV32-NEXT: vsoxei32.v v11, (zero), v10, v0.t ; RV32-NEXT: vsoxei32.v v11, (zero), v10, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i32: ; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v12, v8, 0 ; RV64-NEXT: vnsrl.wx v12, v8, zero
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; RV64-NEXT: vsoxei64.v v12, (zero), v10, v0.t ; RV64-NEXT: vsoxei64.v v12, (zero), v10, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32> %tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32>
call void @llvm.vp.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %tval, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %tval, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret void ret void
} }
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define void @vpscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsext.vf8 v24, v16
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define void @vpscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vzext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v24, v16 ; RV64-NEXT: vzext.vf8 v24, v16
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define void @vpscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v24, v16
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define void @vpscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vzext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v24, v16 ; RV64-NEXT: vzext.vf4 v24, v16
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define void @vpscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v24, v16 ; RV64-NEXT: vsext.vf2 v24, v16
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define void @vpscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vzext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v24, v16 ; RV64-NEXT: vzext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv8i64.nxv8p0i64(<vscale x 8 x i64> %val, <vscale x 8 x i64*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_nxv8i64(<vscale x 8 x i64> %val, i64* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_nxv8i64: ; RV32-LABEL: vpscatter_baseidx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_nxv8i64: ; RV64-LABEL: vpscatter_baseidx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
▲ Show 20 Lines • Show All 558 Lines • ▼ Show 20 Lines
define void @vpscatter_baseidx_sext_nxv6i8_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv6i8_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv6i8_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv6i8_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv6i8_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv6i8_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsext.vf8 v24, v16
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define void @vpscatter_baseidx_zext_nxv6i8_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv6i8_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vzext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v24, v16 ; RV64-NEXT: vzext.vf8 v24, v16
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define void @vpscatter_baseidx_sext_nxv6i16_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv6i16_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv6i16_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv6i16_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv6i16_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv6i16_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v24, v16
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define void @vpscatter_baseidx_zext_nxv6i16_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv6i16_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vzext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v24, v16 ; RV64-NEXT: vzext.vf4 v24, v16
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define void @vpscatter_baseidx_sext_nxv6i32_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv6i32_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv6i32_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv6i32_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv6i32_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv6i32_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v24, v16 ; RV64-NEXT: vsext.vf2 v24, v16
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define void @vpscatter_baseidx_zext_nxv6i32_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv6i32_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i32> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vzext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v24, v16 ; RV64-NEXT: vzext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 6 x i32> %idxs to <vscale x 6 x i64> %eidxs = zext <vscale x 6 x i32> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 6 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 6 x i64> %eidxs
call void @llvm.vp.scatter.nxv6f64.nxv6p0f64(<vscale x 6 x double> %val, <vscale x 6 x double*> %ptrs, <vscale x 6 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv6f64.nxv6p0f64(<vscale x 6 x double> %val, <vscale x 6 x double*> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i64> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_nxv6f64(<vscale x 6 x double> %val, double* %base, <vscale x 6 x i64> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_nxv6f64: ; RV32-LABEL: vpscatter_baseidx_nxv6f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_nxv6f64: ; RV64-LABEL: vpscatter_baseidx_nxv6f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
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define void @vpscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf8 v24, v16 ; RV32-NEXT: vsext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsext.vf8 v24, v16
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define void @vpscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf8 v24, v16 ; RV32-NEXT: vzext.vf8 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf8 v24, v16 ; RV64-NEXT: vzext.vf8 v24, v16
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define void @vpscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf4 v24, v16 ; RV32-NEXT: vsext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v24, v16
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define void @vpscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf4 v24, v16 ; RV32-NEXT: vzext.vf4 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf4 v24, v16 ; RV64-NEXT: vzext.vf4 v24, v16
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define void @vpscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_sext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsext.vf2 v24, v16 ; RV32-NEXT: vsext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf2 v24, v16 ; RV64-NEXT: vsext.vf2 v24, v16
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define void @vpscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vzext.vf2 v24, v16 ; RV32-NEXT: vzext.vf2 v24, v16
; RV32-NEXT: vsll.vi v16, v24, 3 ; RV32-NEXT: vsll.vi v16, v24, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v24, v16 ; RV64-NEXT: vzext.vf2 v24, v16
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64> %eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl) call void @llvm.vp.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret void ret void
} }
define void @vpscatter_baseidx_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) { define void @vpscatter_baseidx_nxv8f64(<vscale x 8 x double> %val, double* %base, <vscale x 8 x i64> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_baseidx_nxv8f64: ; RV32-LABEL: vpscatter_baseidx_nxv8f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v16, 0 ; RV32-NEXT: vnsrl.wx v24, v16, zero
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_nxv8f64: ; RV64-LABEL: vpscatter_baseidx_nxv8f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
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; RV32-NEXT: bltu a2, a1, .LBB97_2 ; RV32-NEXT: bltu a2, a1, .LBB97_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a3, a1 ; RV32-NEXT: mv a3, a1
; RV32-NEXT: .LBB97_2: ; RV32-NEXT: .LBB97_2:
; RV32-NEXT: li a4, 0 ; RV32-NEXT: li a4, 0
; RV32-NEXT: vsext.vf4 v16, v26 ; RV32-NEXT: vsext.vf4 v16, v26
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vl8re8.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: srli a3, a1, 3 ; RV32-NEXT: srli a3, a1, 3
; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, mu
; RV32-NEXT: sub a1, a2, a1 ; RV32-NEXT: sub a1, a2, a1
; RV32-NEXT: vslidedown.vx v0, v0, a3 ; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: bltu a2, a1, .LBB97_4 ; RV32-NEXT: bltu a2, a1, .LBB97_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a4, a1
; RV32-NEXT: .LBB97_4: ; RV32-NEXT: .LBB97_4:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a4, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a4, e64, m8, ta, mu
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: bltu a2, a1, .LBB98_2 ; RV32-NEXT: bltu a2, a1, .LBB98_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a3, a1 ; RV32-NEXT: mv a3, a1
; RV32-NEXT: .LBB98_2: ; RV32-NEXT: .LBB98_2:
; RV32-NEXT: li a4, 0 ; RV32-NEXT: li a4, 0
; RV32-NEXT: vzext.vf4 v16, v26 ; RV32-NEXT: vzext.vf4 v16, v26
; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v24, v8, 0 ; RV32-NEXT: vnsrl.wx v24, v8, zero
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vl8re8.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: srli a3, a1, 3 ; RV32-NEXT: srli a3, a1, 3
; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, mu ; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, mu
; RV32-NEXT: sub a1, a2, a1 ; RV32-NEXT: sub a1, a2, a1
; RV32-NEXT: vslidedown.vx v0, v0, a3 ; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: bltu a2, a1, .LBB98_4 ; RV32-NEXT: bltu a2, a1, .LBB98_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a4, a1
; RV32-NEXT: .LBB98_4: ; RV32-NEXT: .LBB98_4:
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsll.vi v8, v16, 3 ; RV32-NEXT: vsll.vi v8, v16, 3
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v16, v8, 0 ; RV32-NEXT: vnsrl.wx v16, v8, zero
; RV32-NEXT: vsetvli zero, a4, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a4, e64, m8, ta, mu
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
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llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @vtrunc_nxv1i16_nxv1i8(<vscale x 1 x i16> %va) { define <vscale x 1 x i8> @vtrunc_nxv1i16_nxv1i8(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8: ; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8> %tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec ret <vscale x 1 x i8> %tvec
} }
define <vscale x 2 x i8> @vtrunc_nxv2i16_nxv2i8(<vscale x 2 x i16> %va) { define <vscale x 2 x i8> @vtrunc_nxv2i16_nxv2i8(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8: ; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8> %tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec ret <vscale x 2 x i8> %tvec
} }
define <vscale x 4 x i8> @vtrunc_nxv4i16_nxv4i8(<vscale x 4 x i16> %va) { define <vscale x 4 x i8> @vtrunc_nxv4i16_nxv4i8(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8: ; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8> %tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec ret <vscale x 4 x i8> %tvec
} }
define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) { define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8: ; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8> %tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec ret <vscale x 8 x i8> %tvec
} }
define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) { define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8: ; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8> %tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %tvec ret <vscale x 16 x i8> %tvec
} }
define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) { define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8: ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8> %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec ret <vscale x 1 x i8> %tvec
} }
define <vscale x 1 x i16> @vtrunc_nxv1i32_nxv1i16(<vscale x 1 x i32> %va) { define <vscale x 1 x i16> @vtrunc_nxv1i32_nxv1i16(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16: ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16> %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %tvec ret <vscale x 1 x i16> %tvec
} }
define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) { define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8: ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8> %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec ret <vscale x 2 x i8> %tvec
} }
define <vscale x 2 x i16> @vtrunc_nxv2i32_nxv2i16(<vscale x 2 x i32> %va) { define <vscale x 2 x i16> @vtrunc_nxv2i32_nxv2i16(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16: ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16> %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %tvec ret <vscale x 2 x i16> %tvec
} }
define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) { define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8: ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8> %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec ret <vscale x 4 x i8> %tvec
} }
define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) { define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16: ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16> %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %tvec ret <vscale x 4 x i16> %tvec
} }
define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) { define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8: ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8> %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec ret <vscale x 8 x i8> %tvec
} }
define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) { define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16: ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16> %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %tvec ret <vscale x 8 x i16> %tvec
} }
define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) { define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8: ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8> %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %tvec ret <vscale x 16 x i8> %tvec
} }
define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) { define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16: ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16> %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %tvec ret <vscale x 16 x i16> %tvec
} }
define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) { define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8: ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8> %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec ret <vscale x 1 x i8> %tvec
} }
define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) { define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16: ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16> %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %tvec ret <vscale x 1 x i16> %tvec
} }
define <vscale x 1 x i32> @vtrunc_nxv1i64_nxv1i32(<vscale x 1 x i64> %va) { define <vscale x 1 x i32> @vtrunc_nxv1i64_nxv1i32(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32: ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32> %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %tvec ret <vscale x 1 x i32> %tvec
} }
define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) { define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8: ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8> %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec ret <vscale x 2 x i8> %tvec
} }
define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) { define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16: ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16> %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %tvec ret <vscale x 2 x i16> %tvec
} }
define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) { define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32: ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vnsrl.wx v10, v8, zero
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32> %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %tvec ret <vscale x 2 x i32> %tvec
} }
define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) { define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8: ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vnsrl.wx v8, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8> %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec ret <vscale x 4 x i8> %tvec
} }
define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) { define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16: ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wx v8, v12, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16> %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %tvec ret <vscale x 4 x i16> %tvec
} }
define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) { define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32: ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vnsrl.wx v12, v8, zero
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32> %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %tvec ret <vscale x 4 x i32> %tvec
} }
define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) { define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8: ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vnsrl.wx v10, v16, zero
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vnsrl.wx v8, v10, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8> %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec ret <vscale x 8 x i8> %tvec
} }
define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) { define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16: ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vnsrl.wx v8, v16, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16> %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %tvec ret <vscale x 8 x i16> %tvec
} }
define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) { define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32: ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vnsrl.wx v16, v8, zero
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32> %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %tvec ret <vscale x 8 x i32> %tvec
} }