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Differential D118257

[AArch64] Generate fcmps when appropriate for neon intrinsics
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Authored by john.brawn on Jan 26 2022, 8:47 AM.

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kpn
cameron.mcinally
dmgreen
t.p.northover
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rGbca998ed3c9a: [AArch64] Generate fcmps when appropriate for neon intrinsics

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john.brawn created this revision.Jan 26 2022, 8:47 AM
Herald added a subscriber: kristof.beyls. · View Herald TranscriptJan 26 2022, 8:47 AM
john.brawn requested review of this revision.Jan 26 2022, 8:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 26 2022, 8:47 AM
Harbormaster completed remote builds in B145765: Diff 403289.Jan 27 2022, 3:36 AM
john.brawn mentioned this in D117795: [AArch64] Add some missing strict FP vector lowering.Jan 27 2022, 5:19 AM
Matt added a subscriber: Matt.Jan 27 2022, 5:44 AM
dmgreen accepted this revision.Feb 3 2022, 11:44 PM

This seems OK. LGTM

This revision is now accepted and ready to land.Feb 3 2022, 11:44 PM
This revision was landed with ongoing or failed builds.Feb 4 2022, 5:00 AM
Closed by commit rGbca998ed3c9a: [AArch64] Generate fcmps when appropriate for neon intrinsics (authored by john.brawn). · Explain Why
This revision was automatically updated to reflect the committed changes.
john.brawn added a commit: rGbca998ed3c9a: [AArch64] Generate fcmps when appropriate for neon intrinsics.

Revision Contents

PathSize
clang/
lib/
CodeGen/
20 lines
test/
CodeGen/
32 lines

Diff 403289

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,276 Lines • ▼ Show 20 LinesValue *CodeGenFunction::EmitAArch64CompareBuiltinExpr(
// codegen context to find out what needs doing. Unfortunately TableGen // codegen context to find out what needs doing. Unfortunately TableGen
// currently gives us exactly the same calls for vceqz_f32 and vceqz_s32 // currently gives us exactly the same calls for vceqz_f32 and vceqz_s32
// (etc). // (etc).
if (BitCastInst *BI = dyn_cast<BitCastInst>(Op)) if (BitCastInst *BI = dyn_cast<BitCastInst>(Op))
OTy = BI->getOperand(0)->getType(); OTy = BI->getOperand(0)->getType();
Op = Builder.CreateBitCast(Op, OTy); Op = Builder.CreateBitCast(Op, OTy);
if (OTy->getScalarType()->isFloatingPointTy()) { if (OTy->getScalarType()->isFloatingPointTy()) {
if (Fp == CmpInst::FCMP_OEQ)
Op = Builder.CreateFCmp(Fp, Op, Constant::getNullValue(OTy)); Op = Builder.CreateFCmp(Fp, Op, Constant::getNullValue(OTy));
else
Op = Builder.CreateFCmpS(Fp, Op, Constant::getNullValue(OTy));
} else { } else {
Op = Builder.CreateICmp(Ip, Op, Constant::getNullValue(OTy)); Op = Builder.CreateICmp(Ip, Op, Constant::getNullValue(OTy));
} }
return Builder.CreateSExt(Op, Ty, Name); return Builder.CreateSExt(Op, Ty, Name);
} }
static Value *packTBLDVectorList(CodeGenFunction &CGF, ArrayRef<Value *> Ops, static Value *packTBLDVectorList(CodeGenFunction &CGF, ArrayRef<Value *> Ops,
Value *ExtOp, Value *IndexOp, Value *ExtOp, Value *IndexOp,
▲ Show 20 Lines • Show All 2,976 Lines • ▼ Show 20 Lines case NEON::BI__builtin_neon_vcgtd_f64: {
case NEON::BI__builtin_neon_vcled_f64: P = llvm::FCmpInst::FCMP_OLE; break; case NEON::BI__builtin_neon_vcled_f64: P = llvm::FCmpInst::FCMP_OLE; break;
case NEON::BI__builtin_neon_vcltd_f64: P = llvm::FCmpInst::FCMP_OLT; break; case NEON::BI__builtin_neon_vcltd_f64: P = llvm::FCmpInst::FCMP_OLT; break;
case NEON::BI__builtin_neon_vcged_f64: P = llvm::FCmpInst::FCMP_OGE; break; case NEON::BI__builtin_neon_vcged_f64: P = llvm::FCmpInst::FCMP_OGE; break;
case NEON::BI__builtin_neon_vcgtd_f64: P = llvm::FCmpInst::FCMP_OGT; break; case NEON::BI__builtin_neon_vcgtd_f64: P = llvm::FCmpInst::FCMP_OGT; break;
} }
Ops.push_back(EmitScalarExpr(E->getArg(1))); Ops.push_back(EmitScalarExpr(E->getArg(1)));
Ops[0] = Builder.CreateBitCast(Ops[0], DoubleTy); Ops[0] = Builder.CreateBitCast(Ops[0], DoubleTy);
Ops[1] = Builder.CreateBitCast(Ops[1], DoubleTy); Ops[1] = Builder.CreateBitCast(Ops[1], DoubleTy);
if (P == llvm::FCmpInst::FCMP_OEQ)
Ops[0] = Builder.CreateFCmp(P, Ops[0], Ops[1]); Ops[0] = Builder.CreateFCmp(P, Ops[0], Ops[1]);
else
Ops[0] = Builder.CreateFCmpS(P, Ops[0], Ops[1]);
return Builder.CreateSExt(Ops[0], Int64Ty, "vcmpd"); return Builder.CreateSExt(Ops[0], Int64Ty, "vcmpd");
} }
case NEON::BI__builtin_neon_vceqs_f32: case NEON::BI__builtin_neon_vceqs_f32:
case NEON::BI__builtin_neon_vcles_f32: case NEON::BI__builtin_neon_vcles_f32:
case NEON::BI__builtin_neon_vclts_f32: case NEON::BI__builtin_neon_vclts_f32:
case NEON::BI__builtin_neon_vcges_f32: case NEON::BI__builtin_neon_vcges_f32:
case NEON::BI__builtin_neon_vcgts_f32: { case NEON::BI__builtin_neon_vcgts_f32: {
llvm::CmpInst::Predicate P; llvm::CmpInst::Predicate P;
switch (BuiltinID) { switch (BuiltinID) {
default: llvm_unreachable("missing builtin ID in switch!"); default: llvm_unreachable("missing builtin ID in switch!");
case NEON::BI__builtin_neon_vceqs_f32: P = llvm::FCmpInst::FCMP_OEQ; break; case NEON::BI__builtin_neon_vceqs_f32: P = llvm::FCmpInst::FCMP_OEQ; break;
case NEON::BI__builtin_neon_vcles_f32: P = llvm::FCmpInst::FCMP_OLE; break; case NEON::BI__builtin_neon_vcles_f32: P = llvm::FCmpInst::FCMP_OLE; break;
case NEON::BI__builtin_neon_vclts_f32: P = llvm::FCmpInst::FCMP_OLT; break; case NEON::BI__builtin_neon_vclts_f32: P = llvm::FCmpInst::FCMP_OLT; break;
case NEON::BI__builtin_neon_vcges_f32: P = llvm::FCmpInst::FCMP_OGE; break; case NEON::BI__builtin_neon_vcges_f32: P = llvm::FCmpInst::FCMP_OGE; break;
case NEON::BI__builtin_neon_vcgts_f32: P = llvm::FCmpInst::FCMP_OGT; break; case NEON::BI__builtin_neon_vcgts_f32: P = llvm::FCmpInst::FCMP_OGT; break;
} }
Ops.push_back(EmitScalarExpr(E->getArg(1))); Ops.push_back(EmitScalarExpr(E->getArg(1)));
Ops[0] = Builder.CreateBitCast(Ops[0], FloatTy); Ops[0] = Builder.CreateBitCast(Ops[0], FloatTy);
Ops[1] = Builder.CreateBitCast(Ops[1], FloatTy); Ops[1] = Builder.CreateBitCast(Ops[1], FloatTy);
if (P == llvm::FCmpInst::FCMP_OEQ)
Ops[0] = Builder.CreateFCmp(P, Ops[0], Ops[1]); Ops[0] = Builder.CreateFCmp(P, Ops[0], Ops[1]);
else
Ops[0] = Builder.CreateFCmpS(P, Ops[0], Ops[1]);
return Builder.CreateSExt(Ops[0], Int32Ty, "vcmpd"); return Builder.CreateSExt(Ops[0], Int32Ty, "vcmpd");
} }
case NEON::BI__builtin_neon_vceqh_f16: case NEON::BI__builtin_neon_vceqh_f16:
case NEON::BI__builtin_neon_vcleh_f16: case NEON::BI__builtin_neon_vcleh_f16:
case NEON::BI__builtin_neon_vclth_f16: case NEON::BI__builtin_neon_vclth_f16:
case NEON::BI__builtin_neon_vcgeh_f16: case NEON::BI__builtin_neon_vcgeh_f16:
case NEON::BI__builtin_neon_vcgth_f16: { case NEON::BI__builtin_neon_vcgth_f16: {
llvm::CmpInst::Predicate P; llvm::CmpInst::Predicate P;
switch (BuiltinID) { switch (BuiltinID) {
default: llvm_unreachable("missing builtin ID in switch!"); default: llvm_unreachable("missing builtin ID in switch!");
case NEON::BI__builtin_neon_vceqh_f16: P = llvm::FCmpInst::FCMP_OEQ; break; case NEON::BI__builtin_neon_vceqh_f16: P = llvm::FCmpInst::FCMP_OEQ; break;
case NEON::BI__builtin_neon_vcleh_f16: P = llvm::FCmpInst::FCMP_OLE; break; case NEON::BI__builtin_neon_vcleh_f16: P = llvm::FCmpInst::FCMP_OLE; break;
case NEON::BI__builtin_neon_vclth_f16: P = llvm::FCmpInst::FCMP_OLT; break; case NEON::BI__builtin_neon_vclth_f16: P = llvm::FCmpInst::FCMP_OLT; break;
case NEON::BI__builtin_neon_vcgeh_f16: P = llvm::FCmpInst::FCMP_OGE; break; case NEON::BI__builtin_neon_vcgeh_f16: P = llvm::FCmpInst::FCMP_OGE; break;
case NEON::BI__builtin_neon_vcgth_f16: P = llvm::FCmpInst::FCMP_OGT; break; case NEON::BI__builtin_neon_vcgth_f16: P = llvm::FCmpInst::FCMP_OGT; break;
} }
Ops.push_back(EmitScalarExpr(E->getArg(1))); Ops.push_back(EmitScalarExpr(E->getArg(1)));
Ops[0] = Builder.CreateBitCast(Ops[0], HalfTy); Ops[0] = Builder.CreateBitCast(Ops[0], HalfTy);
Ops[1] = Builder.CreateBitCast(Ops[1], HalfTy); Ops[1] = Builder.CreateBitCast(Ops[1], HalfTy);
if (P == llvm::FCmpInst::FCMP_OEQ)
Ops[0] = Builder.CreateFCmp(P, Ops[0], Ops[1]); Ops[0] = Builder.CreateFCmp(P, Ops[0], Ops[1]);
else
Ops[0] = Builder.CreateFCmpS(P, Ops[0], Ops[1]);
return Builder.CreateSExt(Ops[0], Int16Ty, "vcmpd"); return Builder.CreateSExt(Ops[0], Int16Ty, "vcmpd");
} }
case NEON::BI__builtin_neon_vceqd_s64: case NEON::BI__builtin_neon_vceqd_s64:
case NEON::BI__builtin_neon_vceqd_u64: case NEON::BI__builtin_neon_vceqd_u64:
case NEON::BI__builtin_neon_vcgtd_s64: case NEON::BI__builtin_neon_vcgtd_s64:
case NEON::BI__builtin_neon_vcgtd_u64: case NEON::BI__builtin_neon_vcgtd_u64:
case NEON::BI__builtin_neon_vcltd_s64: case NEON::BI__builtin_neon_vcltd_s64:
case NEON::BI__builtin_neon_vcltd_u64: case NEON::BI__builtin_neon_vcltd_u64:
▲ Show 20 Lines • Show All 8,545 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-neon-intrinsics-constrained.c

Show First 20 Lines • Show All 579 Lines • ▼ Show 20 Lines
// COMMONIR: [[VCEQZ_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCEQZ_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCEQZ_I]] // COMMONIR: ret i64 [[VCEQZ_I]]
uint64_t test_vceqzd_f64(float64_t a) { uint64_t test_vceqzd_f64(float64_t a) {
return (uint64_t)vceqzd_f64(a); return (uint64_t)vceqzd_f64(a);
} }
// COMMON-LABEL: test_vcges_f32 // COMMON-LABEL: test_vcges_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge float %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge float %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}} // CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCMPD_I]] // COMMONIR: ret i32 [[VCMPD_I]]
uint32_t test_vcges_f32(float32_t a, float32_t b) { uint32_t test_vcges_f32(float32_t a, float32_t b) {
return (uint32_t)vcges_f32(a, b); return (uint32_t)vcges_f32(a, b);
} }
// COMMON-LABEL: test_vcged_f64 // COMMON-LABEL: test_vcged_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge double %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge double %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}} // CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCMPD_I]] // COMMONIR: ret i64 [[VCMPD_I]]
uint64_t test_vcged_f64(float64_t a, float64_t b) { uint64_t test_vcged_f64(float64_t a, float64_t b) {
return (uint64_t)vcged_f64(a, b); return (uint64_t)vcged_f64(a, b);
} }
// COMMON-LABEL: test_vcgezs_f32 // COMMON-LABEL: test_vcgezs_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge float %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge float %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp s{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
// COMMONIR: [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCGEZ_I]] // COMMONIR: ret i32 [[VCGEZ_I]]
uint32_t test_vcgezs_f32(float32_t a) { uint32_t test_vcgezs_f32(float32_t a) {
return (uint32_t)vcgezs_f32(a); return (uint32_t)vcgezs_f32(a);
} }
// COMMON-LABEL: test_vcgezd_f64 // COMMON-LABEL: test_vcgezd_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge double %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp oge double %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp d{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ge
// COMMONIR: [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCGEZ_I]] // COMMONIR: ret i64 [[VCGEZ_I]]
uint64_t test_vcgezd_f64(float64_t a) { uint64_t test_vcgezd_f64(float64_t a) {
return (uint64_t)vcgezd_f64(a); return (uint64_t)vcgezd_f64(a);
} }
// COMMON-LABEL: test_vcgts_f32 // COMMON-LABEL: test_vcgts_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt float %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt float %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}} // CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCMPD_I]] // COMMONIR: ret i32 [[VCMPD_I]]
uint32_t test_vcgts_f32(float32_t a, float32_t b) { uint32_t test_vcgts_f32(float32_t a, float32_t b) {
return (uint32_t)vcgts_f32(a, b); return (uint32_t)vcgts_f32(a, b);
} }
// COMMON-LABEL: test_vcgtd_f64 // COMMON-LABEL: test_vcgtd_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt double %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt double %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}} // CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCMPD_I]] // COMMONIR: ret i64 [[VCMPD_I]]
uint64_t test_vcgtd_f64(float64_t a, float64_t b) { uint64_t test_vcgtd_f64(float64_t a, float64_t b) {
return (uint64_t)vcgtd_f64(a, b); return (uint64_t)vcgtd_f64(a, b);
} }
// COMMON-LABEL: test_vcgtzs_f32 // COMMON-LABEL: test_vcgtzs_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt float %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt float %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp s{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
// COMMONIR: [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCGTZ_I]] // COMMONIR: ret i32 [[VCGTZ_I]]
uint32_t test_vcgtzs_f32(float32_t a) { uint32_t test_vcgtzs_f32(float32_t a) {
return (uint32_t)vcgtzs_f32(a); return (uint32_t)vcgtzs_f32(a);
} }
// COMMON-LABEL: test_vcgtzd_f64 // COMMON-LABEL: test_vcgtzd_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt double %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ogt double %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp d{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt // CHECK-ASM-NEXT:cset {{w[0-9]+}}, gt
// COMMONIR: [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCGTZ_I]] // COMMONIR: ret i64 [[VCGTZ_I]]
uint64_t test_vcgtzd_f64(float64_t a) { uint64_t test_vcgtzd_f64(float64_t a) {
return (uint64_t)vcgtzd_f64(a); return (uint64_t)vcgtzd_f64(a);
} }
// COMMON-LABEL: test_vcles_f32 // COMMON-LABEL: test_vcles_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole float %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole float %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}} // CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCMPD_I]] // COMMONIR: ret i32 [[VCMPD_I]]
uint32_t test_vcles_f32(float32_t a, float32_t b) { uint32_t test_vcles_f32(float32_t a, float32_t b) {
return (uint32_t)vcles_f32(a, b); return (uint32_t)vcles_f32(a, b);
} }
// COMMON-LABEL: test_vcled_f64 // COMMON-LABEL: test_vcled_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole double %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole double %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}} // CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCMPD_I]] // COMMONIR: ret i64 [[VCMPD_I]]
uint64_t test_vcled_f64(float64_t a, float64_t b) { uint64_t test_vcled_f64(float64_t a, float64_t b) {
return (uint64_t)vcled_f64(a, b); return (uint64_t)vcled_f64(a, b);
} }
// COMMON-LABEL: test_vclezs_f32 // COMMON-LABEL: test_vclezs_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole float %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole float %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp s{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
// COMMONIR: [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCLEZ_I]] // COMMONIR: ret i32 [[VCLEZ_I]]
uint32_t test_vclezs_f32(float32_t a) { uint32_t test_vclezs_f32(float32_t a) {
return (uint32_t)vclezs_f32(a); return (uint32_t)vclezs_f32(a);
} }
// COMMON-LABEL: test_vclezd_f64 // COMMON-LABEL: test_vclezd_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole double %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp ole double %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp d{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls // CHECK-ASM-NEXT:cset {{w[0-9]+}}, ls
// COMMONIR: [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCLEZ_I]] // COMMONIR: ret i64 [[VCLEZ_I]]
uint64_t test_vclezd_f64(float64_t a) { uint64_t test_vclezd_f64(float64_t a) {
return (uint64_t)vclezd_f64(a); return (uint64_t)vclezd_f64(a);
} }
// COMMON-LABEL: test_vclts_f32 // COMMON-LABEL: test_vclts_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt float %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt float %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}} // CHECK-ASM: fcmp s{{[0-9]+}}, s{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCMPD_I]] // COMMONIR: ret i32 [[VCMPD_I]]
uint32_t test_vclts_f32(float32_t a, float32_t b) { uint32_t test_vclts_f32(float32_t a, float32_t b) {
return (uint32_t)vclts_f32(a, b); return (uint32_t)vclts_f32(a, b);
} }
// COMMON-LABEL: test_vcltd_f64 // COMMON-LABEL: test_vcltd_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt double %a, %b // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt double %a, %b
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}} // CHECK-ASM: fcmp d{{[0-9]+}}, d{{[0-9]+}}
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
// COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCMPD_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCMPD_I]] // COMMONIR: ret i64 [[VCMPD_I]]
uint64_t test_vcltd_f64(float64_t a, float64_t b) { uint64_t test_vcltd_f64(float64_t a, float64_t b) {
return (uint64_t)vcltd_f64(a, b); return (uint64_t)vcltd_f64(a, b);
} }
// COMMON-LABEL: test_vcltzs_f32 // COMMON-LABEL: test_vcltzs_f32
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt float %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt float %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp s{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp s{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
// COMMONIR: [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i32 // COMMONIR: [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i32
// COMMONIR: ret i32 [[VCLTZ_I]] // COMMONIR: ret i32 [[VCLTZ_I]]
uint32_t test_vcltzs_f32(float32_t a) { uint32_t test_vcltzs_f32(float32_t a) {
return (uint32_t)vcltzs_f32(a); return (uint32_t)vcltzs_f32(a);
} }
// COMMON-LABEL: test_vcltzd_f64 // COMMON-LABEL: test_vcltzd_f64
// UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt double %a, 0.000000e+00 // UNCONSTRAINED: [[TMP0:%.*]] = fcmp olt double %a, 0.000000e+00
// CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") // CONSTRAINED: [[TMP0:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
// CHECK-ASM: fcmp d{{[0-9]+}}, #0.0 // CHECK-ASM: fcmp d{{[0-9]+}}, #0.0
// CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi // CHECK-ASM-NEXT:cset {{w[0-9]+}}, mi
// COMMONIR: [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i64 // COMMONIR: [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i64
// COMMONIR: ret i64 [[VCLTZ_I]] // COMMONIR: ret i64 [[VCLTZ_I]]
uint64_t test_vcltzd_f64(float64_t a) { uint64_t test_vcltzd_f64(float64_t a) {
return (uint64_t)vcltzd_f64(a); return (uint64_t)vcltzd_f64(a);
} }
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