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Differential D118030

[SelectionDAG][VP] Add widening support for VP_MERGE
ClosedPublic

Authored by frasercrmck on Jan 24 2022, 3:54 AM.

Details

Reviewers
craig.topper
victor-eds
rogfer01
simoll
RKSimon
Commits
rG7cb452bfde10: [SelectionDAG][VP] Add widening support for VP_MERGE
Summary

This patch adds widening support for ISD::VP_MERGE, which widens
identically to VP_SELECT and similarly to other select-like nodes.

Diff Detail

Event Timeline

frasercrmck created this revision.Jan 24 2022, 3:54 AM
Herald added subscribers: ecnelises, luismarques, apazos and 18 others. · View Herald TranscriptJan 24 2022, 3:54 AM
frasercrmck requested review of this revision.Jan 24 2022, 3:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 24 2022, 3:54 AM
Herald added subscribers: llvm-commits, • pcwang-thead, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B145199: Diff 402462.Jan 24 2022, 7:30 AM
craig.topper accepted this revision.Jan 24 2022, 8:53 AM

LGTM

This revision is now accepted and ready to land.Jan 24 2022, 8:53 AM
This revision was landed with ongoing or failed builds.Jan 25 2022, 3:09 AM
Closed by commit rG7cb452bfde10: [SelectionDAG][VP] Add widening support for VP_MERGE (authored by frasercrmck). · Explain Why
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rG7cb452bfde10: [SelectionDAG][VP] Add widening support for VP_MERGE.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
3 lines
test/
CodeGen/
RISCV/
rvv/
37 lines
37 lines

Diff 402462

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Show First 20 Lines • Show All 3,226 Lines • ▼ Show 20 Lines#endif
case ISD::SPLAT_VECTOR: case ISD::SPLAT_VECTOR:
case ISD::SCALAR_TO_VECTOR: case ISD::SCALAR_TO_VECTOR:
Res = WidenVecRes_ScalarOp(N); Res = WidenVecRes_ScalarOp(N);
break; break;
case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
case ISD::VSELECT: case ISD::VSELECT:
case ISD::SELECT: case ISD::SELECT:
case ISD::VP_SELECT: case ISD::VP_SELECT:
case ISD::VP_MERGE:
Res = WidenVecRes_Select(N); Res = WidenVecRes_Select(N);
break; break;
case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
case ISD::VECTOR_SHUFFLE: case ISD::VECTOR_SHUFFLE:
Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
break; break;
▲ Show 20 Lines • Show All 1,535 Lines • ▼ Show 20 Lines if (CondVT.isVector()) {
if (Cond1.getValueType() != CondWidenVT) if (Cond1.getValueType() != CondWidenVT)
Cond1 = ModifyToType(Cond1, CondWidenVT); Cond1 = ModifyToType(Cond1, CondWidenVT);
} }
SDValue InOp1 = GetWidenedVector(N->getOperand(1)); SDValue InOp1 = GetWidenedVector(N->getOperand(1));
SDValue InOp2 = GetWidenedVector(N->getOperand(2)); SDValue InOp2 = GetWidenedVector(N->getOperand(2));
assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
return Opcode == ISD::VP_SELECT return Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE
? DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2, ? DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2,
N->getOperand(3)) N->getOperand(3))
: DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2); : DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2);
} }
SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
SDValue InOp1 = GetWidenedVector(N->getOperand(2)); SDValue InOp1 = GetWidenedVector(N->getOperand(2));
SDValue InOp2 = GetWidenedVector(N->getOperand(3)); SDValue InOp2 = GetWidenedVector(N->getOperand(3));
▲ Show 20 Lines • Show All 1,378 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 2, i32 0 %elt.head = insertelement <4 x i8> poison, i8 2, i32 0
%va = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer %va = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.merge.v4i8(<4 x i1> %m, <4 x i8> %va, <4 x i8> %vb, i32 %evl) %v = call <4 x i8> @llvm.vp.merge.v4i8(<4 x i1> %m, <4 x i8> %va, <4 x i8> %vb, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
declare <6 x i8> @llvm.vp.merge.v6i8(<6 x i1>, <6 x i8>, <6 x i8>, i32)
define <6 x i8> @vpmerge_vv_v6i8(<6 x i8> %va, <6 x i8> %vb, <6 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vv_v6i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <6 x i8> @llvm.vp.merge.v6i8(<6 x i1> %m, <6 x i8> %va, <6 x i8> %vb, i32 %evl)
ret <6 x i8> %v
}
define <6 x i8> @vpmerge_vx_v6i8(i8 %a, <6 x i8> %vb, <6 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vx_v6i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%elt.head = insertelement <6 x i8> poison, i8 %a, i32 0
%va = shufflevector <6 x i8> %elt.head, <6 x i8> poison, <6 x i32> zeroinitializer
%v = call <6 x i8> @llvm.vp.merge.v6i8(<6 x i1> %m, <6 x i8> %va, <6 x i8> %vb, i32 %evl)
ret <6 x i8> %v
}
define <6 x i8> @vpmerge_vi_v6i8(<6 x i8> %vb, <6 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vi_v6i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: ret
%elt.head = insertelement <6 x i8> poison, i8 2, i32 0
%va = shufflevector <6 x i8> %elt.head, <6 x i8> poison, <6 x i32> zeroinitializer
%v = call <6 x i8> @llvm.vp.merge.v6i8(<6 x i1> %m, <6 x i8> %va, <6 x i8> %vb, i32 %evl)
ret <6 x i8> %v
}
declare <8 x i8> @llvm.vp.merge.v8i8(<8 x i1>, <8 x i8>, <8 x i8>, i32) declare <8 x i8> @llvm.vp.merge.v8i8(<8 x i1>, <8 x i8>, <8 x i8>, i32)
define <8 x i8> @vpmerge_vv_v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i8> @vpmerge_vv_v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vv_v8i8: ; CHECK-LABEL: vpmerge_vv_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
▲ Show 20 Lines • Show All 865 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 2, i32 0 %elt.head = insertelement <vscale x 2 x i8> poison, i8 2, i32 0
%va = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer %va = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i8> @llvm.vp.merge.nxv2i8(<vscale x 2 x i1> %m, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, i32 %evl) %v = call <vscale x 2 x i8> @llvm.vp.merge.nxv2i8(<vscale x 2 x i1> %m, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
declare <vscale x 3 x i8> @llvm.vp.merge.nxv3i8(<vscale x 3 x i1>, <vscale x 3 x i8>, <vscale x 3 x i8>, i32)
define <vscale x 3 x i8> @vpmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vv_nxv3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.merge.nxv3i8(<vscale x 3 x i1> %m, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, i32 %evl)
ret <vscale x 3 x i8> %v
}
define <vscale x 3 x i8> @vpmerge_vx_nxv3i8(i8 %a, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vx_nxv3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %a, i32 0
%va = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
%v = call <vscale x 3 x i8> @llvm.vp.merge.nxv3i8(<vscale x 3 x i1> %m, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, i32 %evl)
ret <vscale x 3 x i8> %v
}
define <vscale x 3 x i8> @vpmerge_vi_nxv3i8(<vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vi_nxv3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 2, i32 0
%va = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
%v = call <vscale x 3 x i8> @llvm.vp.merge.nxv3i8(<vscale x 3 x i1> %m, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, i32 %evl)
ret <vscale x 3 x i8> %v
}
declare <vscale x 4 x i8> @llvm.vp.merge.nxv4i8(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) declare <vscale x 4 x i8> @llvm.vp.merge.nxv4i8(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32)
define <vscale x 4 x i8> @vpmerge_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i8> @vpmerge_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vv_nxv4i8: ; CHECK-LABEL: vpmerge_vv_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0 ; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
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