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Differential D117188

[RISCV] Add patterns for vector widening integer add/subtract
ClosedPublic

Authored by jacquesguan on Jan 12 2022, 11:48 PM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
HsiangKai
khchen
benshi001
Commits
rGb148348ad486: [RISCV] Add patterns for vector widening integer add/subtract
Summary

Add patterns for vector widening integer add/subtract instructions

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
12 lines
34 lines
test/
CodeGen/
RISCV/
rvv/
427 lines

Diff 400222

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 1,028 Lines • ▼ Show 20 Lines
def mul_const_oneuse : PatFrag<(ops node:$A, node:$B), def mul_const_oneuse : PatFrag<(ops node:$A, node:$B),
(mul node:$A, node:$B), [{ (mul node:$A, node:$B), [{
if (auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) if (auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
if (N1C->hasOneUse()) if (N1C->hasOneUse())
return true; return true;
return false; return false;
}]>; }]>;
def sext_oneuse : PatFrag<(ops node:$A), (sext node:$A), [{
return N->hasOneUse();
}]>;
def zext_oneuse : PatFrag<(ops node:$A), (zext node:$A), [{
return N->hasOneUse();
}]>;
def anyext_oneuse : PatFrag<(ops node:$A), (anyext node:$A), [{
return N->hasOneUse();
}]>;
/// Simple arithmetic operations /// Simple arithmetic operations
def : PatGprGpr<add, ADD>; def : PatGprGpr<add, ADD>;
def : PatGprSimm12<add, ADDI>; def : PatGprSimm12<add, ADDI>;
def : PatGprGpr<sub, SUB>; def : PatGprGpr<sub, SUB>;
def : PatGprGpr<or, OR>; def : PatGprGpr<or, OR>;
def : PatGprSimm12<or, ORI>; def : PatGprSimm12<or, ORI>;
def : PatGprGpr<and, AND>; def : PatGprGpr<and, AND>;
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llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 357 Lines • ▼ Show 20 Lines foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti; defvar fwti = vtiToWti.Wti;
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))), def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
} }
} }
multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
foreach vti = AllWidenableIntVectors in {
def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
(vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX)
vti.Vti.RegClass:$rs2, GPR:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
(vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
(!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rs2, GPR:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
// 7.4. Vector Unit-Stride Instructions // 7.4. Vector Unit-Stride Instructions
foreach vti = !listconcat(FractionalGroupIntegerVectors, foreach vti = !listconcat(FractionalGroupIntegerVectors,
Show All 20 Lines def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)),
(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>;
def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)),
(vti.Vector vti.RegClass:$rs1)), (vti.Vector vti.RegClass:$rs1)),
(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>;
} }
// 12.2. Vector Widening Integer Add and Subtract
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">;
// 12.3. Vector Integer Extension // 12.3. Vector Integer Extension
defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2", defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2",
AllFractionableVF2IntVectors>; AllFractionableVF2IntVectors>;
defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2", defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2",
AllFractionableVF2IntVectors>; AllFractionableVF2IntVectors>;
defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4", defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
AllFractionableVF4IntVectors>; AllFractionableVF4IntVectors>;
defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4", defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
▲ Show 20 Lines • Show All 394 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i64> @vwadd_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwadd_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwadd.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%ve = add <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwaddu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwaddu_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%ve = add <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwadd_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vwadd_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwadd.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%ve = add <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwaddu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vwaddu_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwaddu.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%ve = add <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwadd_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwadd_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwadd.wv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = add <vscale x 1 x i64> %va, %vc
ret <vscale x 1 x i64> %vd
}
define <vscale x 1 x i64> @vwaddu_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwaddu_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwaddu.wv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = add <vscale x 1 x i64> %va, %vc
ret <vscale x 1 x i64> %vd
}
define <vscale x 1 x i64> @vwadd_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
; CHECK-LABEL: vwadd_wx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%vc = add <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vwaddu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
; CHECK-LABEL: vwaddu_wx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%vc = add <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vwadd_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwadd_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwadd.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%ve = add <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwaddu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwaddu_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%ve = add <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwadd_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vwadd_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwadd.vx v10, v8, a0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%ve = add <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwaddu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vwaddu_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwaddu.vx v10, v8, a0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%ve = add <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwadd_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwadd_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwadd.wv v12, v8, v10
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = add <vscale x 2 x i64> %va, %vc
ret <vscale x 2 x i64> %vd
}
define <vscale x 2 x i64> @vwaddu_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwaddu_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwaddu.wv v12, v8, v10
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = add <vscale x 2 x i64> %va, %vc
ret <vscale x 2 x i64> %vd
}
define <vscale x 2 x i64> @vwadd_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
; CHECK-LABEL: vwadd_wx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%vc = add <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vwaddu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
; CHECK-LABEL: vwaddu_wx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%vc = add <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vwadd_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwadd_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwadd.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%ve = add <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwaddu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwaddu_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwaddu.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%ve = add <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwadd_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vwadd_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwadd.vx v12, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%ve = add <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwaddu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vwaddu_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwaddu.vx v12, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%ve = add <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwadd_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwadd_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwadd.wv v16, v8, v12
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = add <vscale x 4 x i64> %va, %vc
ret <vscale x 4 x i64> %vd
}
define <vscale x 4 x i64> @vwaddu_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwaddu_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwaddu.wv v16, v8, v12
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = add <vscale x 4 x i64> %va, %vc
ret <vscale x 4 x i64> %vd
}
define <vscale x 4 x i64> @vwadd_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
; CHECK-LABEL: vwadd_wx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%vc = add <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vwaddu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
; CHECK-LABEL: vwaddu_wx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%vc = add <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vwadd_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwadd_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwadd.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%ve = add <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwaddu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwaddu_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwaddu.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%ve = add <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwadd_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vwadd_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwadd.vx v16, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%ve = add <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwaddu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vwaddu_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwaddu.vx v16, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%ve = add <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwadd_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwadd_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwadd.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = add <vscale x 8 x i64> %va, %vc
ret <vscale x 8 x i64> %vd
}
define <vscale x 8 x i64> @vwaddu_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwaddu_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwaddu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = add <vscale x 8 x i64> %va, %vc
ret <vscale x 8 x i64> %vd
}
define <vscale x 8 x i64> @vwadd_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
; CHECK-LABEL: vwadd_wx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%vc = add <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vwaddu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
; CHECK-LABEL: vwaddu_wx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%vc = add <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
}