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Differential D117392

[RISCV] Add tests for scalable-vector vwsub patterns
ClosedPublic

Authored by frasercrmck on Jan 15 2022, 4:00 AM.

Details

Reviewers
craig.topper
jacquesguan
Commits
rGaf219e567f96: [RISCV] Add tests for scalable-vector vwsub patterns
Summary

This patch adds tests for patterns introduced in D117188.

Diff Detail

Event Timeline

frasercrmck created this revision.Jan 15 2022, 4:00 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald TranscriptJan 15 2022, 4:00 AM
frasercrmck requested review of this revision.Jan 15 2022, 4:00 AM
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jacquesguan accepted this revision.Jan 15 2022, 4:12 AM

LGTM

This revision is now accepted and ready to land.Jan 15 2022, 4:12 AM
Harbormaster completed remote builds in B143582: Diff 400271.Jan 15 2022, 4:54 AM
This revision was landed with ongoing or failed builds.Jan 17 2022, 3:03 AM
Closed by commit rGaf219e567f96: [RISCV] Add tests for scalable-vector vwsub patterns (authored by frasercrmck). · Explain Why
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rGaf219e567f96: [RISCV] Add tests for scalable-vector vwsub patterns.
Herald added subscribers: alextsao1999, eopXD. · View Herald TranscriptJan 17 2022, 3:03 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
427 lines

Diff 400481

llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i64> @vwsub_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwsub_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsub.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%ve = sub <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwsubu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwsubu_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsubu.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%ve = sub <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwsub_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsub_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsub.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%ve = sub <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwsubu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsubu_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsubu.vx v9, v8, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%ve = sub <vscale x 1 x i64> %vc, %vd
ret <vscale x 1 x i64> %ve
}
define <vscale x 1 x i64> @vwsub_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwsub_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsub.wv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = sub <vscale x 1 x i64> %va, %vc
ret <vscale x 1 x i64> %vd
}
define <vscale x 1 x i64> @vwsubu_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vwsubu_wv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsubu.wv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = sub <vscale x 1 x i64> %va, %vc
ret <vscale x 1 x i64> %vd
}
define <vscale x 1 x i64> @vwsub_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsub_wx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%vc = sub <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 1 x i64> @vwsubu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsubu_wx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%vc = sub <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
}
define <vscale x 2 x i64> @vwsub_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwsub_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsub.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%ve = sub <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwsubu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwsubu_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsubu.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%ve = sub <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwsub_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsub_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsub.vx v10, v8, a0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%ve = sub <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwsubu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsubu_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsubu.vx v10, v8, a0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%ve = sub <vscale x 2 x i64> %vc, %vd
ret <vscale x 2 x i64> %ve
}
define <vscale x 2 x i64> @vwsub_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwsub_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsub.wv v12, v8, v10
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = sub <vscale x 2 x i64> %va, %vc
ret <vscale x 2 x i64> %vd
}
define <vscale x 2 x i64> @vwsubu_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vwsubu_wv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsubu.wv v12, v8, v10
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = sub <vscale x 2 x i64> %va, %vc
ret <vscale x 2 x i64> %vd
}
define <vscale x 2 x i64> @vwsub_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsub_wx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%vc = sub <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 2 x i64> @vwsubu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsubu_wx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%vc = sub <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
}
define <vscale x 4 x i64> @vwsub_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwsub_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsub.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%ve = sub <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwsubu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwsubu_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsubu.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%ve = sub <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwsub_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsub_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsub.vx v12, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%ve = sub <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwsubu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsubu_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsubu.vx v12, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%ve = sub <vscale x 4 x i64> %vc, %vd
ret <vscale x 4 x i64> %ve
}
define <vscale x 4 x i64> @vwsub_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwsub_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsub.wv v16, v8, v12
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = sub <vscale x 4 x i64> %va, %vc
ret <vscale x 4 x i64> %vd
}
define <vscale x 4 x i64> @vwsubu_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vwsubu_wv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsubu.wv v16, v8, v12
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = sub <vscale x 4 x i64> %va, %vc
ret <vscale x 4 x i64> %vd
}
define <vscale x 4 x i64> @vwsub_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsub_wx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%vc = sub <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 4 x i64> @vwsubu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsubu_wx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%vc = sub <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
}
define <vscale x 8 x i64> @vwsub_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwsub_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsub.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%ve = sub <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwsubu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwsubu_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsubu.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%ve = sub <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwsub_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsub_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsub.vx v16, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%ve = sub <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwsubu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vwsubu_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsubu.vx v16, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%ve = sub <vscale x 8 x i64> %vc, %vd
ret <vscale x 8 x i64> %ve
}
define <vscale x 8 x i64> @vwsub_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwsub_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = sub <vscale x 8 x i64> %va, %vc
ret <vscale x 8 x i64> %vd
}
define <vscale x 8 x i64> @vwsubu_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vwsubu_wv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = sub <vscale x 8 x i64> %va, %vc
ret <vscale x 8 x i64> %vd
}
define <vscale x 8 x i64> @vwsub_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsub_wx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%vc = sub <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
}
define <vscale x 8 x i64> @vwsubu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
; CHECK-LABEL: vwsubu_wx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%vc = sub <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
}