[GlobalISel] Add big endian support in CallLowering

[0x59616e]

Summary

When splitting values, CallLowering assumes Lo part goes first. But in big endian ISA such as M68k, Hi part goes first.

This patch fixes this.

[0x59616e]

update diff

[0x59616e]

This comment was removed by 0x59616e.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

680

Can hoist the TLI query out of the loop

[0x59616e]

update diff according to @arsenm suggestion

[0x59616e]

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

680

Done. Thanks :)

[0x59616e]

update diff.

Remove a test in this revision, since that test depends on the InstructionSelector of M68k and I defer that part.

[arsenm]

LGTM

[0x59616e]

Thanks @arsenm for reviewing ! Really appreciate all the help you give ;)

[RKSimon]

@0x59616e reverse ping - what's happening with this patch?

[0x59616e]

In D116877#3304027, @RKSimon wrote:

@0x59616e reverse ping - what's happening with this patch?

I think now it's ok to land this.
Could you help me ?

name: Sheng
email: [e-mail]

[0x59616e]

rebase.

[0x59616e]

Thanks ! Appreciate your help ;)

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

     for (unsigned Part = 0; Part < NumParts; ++Part) {
       Register ArgReg = Args[i].Regs[Part];
       // There should be Regs.size() ArgLocs per argument.
-      VA = ArgLocs[j + Part];
+      unsigned Idx = TLI->hasBigEndianPartOrdering(OrigVT, DL)
+                         ? NumParts - 1 - Part
+                         : Part;
+      CCValAssign &VA = ArgLocs[j + Idx];
       const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
 
       if (VA.isMemLoc() && !Flags.isByVal()) {

llvm/test/CodeGen/M68k/GlobalISel/c-call.ll

   %3 = call i32 @callee3(i32 %0, i32 %1)
   ret i32 %3
 }
-declare i32 @callee3(i32, i32)
+declare i32 @callee3(i32, i32)
+
+define i64 @test_ret_i64(i64 %0) nounwind {
+; CHECK-LABEL: test_ret_i64:
+; CHECK:       ; %bb.0
+; CHECK-NEXT:  move.l (8,%sp), %d1
+; CHECK-NEXT:  move.l (4,%sp), %d0
+; CHECK-NEXT:  rts
+  ret i64 %0
+}
+
+define void @test_passing_i64(i64 %0, i64 %1) nounwind {
+; CHECK-LABEL: test_passing_i64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:  suba.l  #20, %sp
+; CHECK-NEXT:  move.l (28,%sp), %d0
+; CHECK-NEXT:  move.l (24,%sp), %d1
+; CHECK-NEXT:  move.l (36,%sp), %a0
+; CHECK-NEXT:  move.l (32,%sp), %a1
+; CHECK-NEXT:  move.l %a0, (4,%sp)
+; CHECK-NEXT:  move.l %a1, (0,%sp)
+; CHECK-NEXT:  move.l %d0, (12,%sp)
+; CHECK-NEXT:  move.l %d1, (8,%sp)
+; CHECK-NEXT:  jsr callee_test_passing_i64
+; CHECK-NEXT:  adda.l #20, %sp
+; CHECK-NEXT:  rts
+  call void @callee_test_passing_i64(i64 %1, i64 %0)
+  ret void
+}
+declare void @callee_test_passing_i64(i64, i64)

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

   ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
   ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
   ; CHECK:   [[G_UNMERGE_VAL1:%[0-9]+]]:_(s32), [[G_UNMERGE_VAL2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[G_MERGE_VAL]](s64)
-  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL1]](s32)
-  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL2]](s32)
-  ; CHECK:   RTS implicit $d0, implicit $d1
+  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL1]](s32)
+  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL2]](s32)
+  ; CHECK:   RTS implicit $d1, implicit $d0
   ret i64 %a
 }