[GlobalISel][Legalizer] Support reducing load/store width in big endian order

[0x59616e]

Summary

LegalizerHelper::reduceLoadStoreWidth uses little endian order when splitting type. This patch adds big endian support.

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update diff

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update diff

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rebase

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update diff

[arsenm]

llvm/test/CodeGen/M68k/GlobalISel/legalizer_load_store.ll

1 ↗

(On Diff #399850)

Generally legalizer tests are MIR->MIR. I think it would be best to have some end to end IR tests, in addition to MIR->MIR tests that only run the legalizer

[0x59616e]

llvm/test/CodeGen/M68k/GlobalISel/legalizer_load_store.ll

1 ↗

(On Diff #399850)

Do you mind explaining the meaning of "end to end IR tests" ?

[0x59616e]

update diff

Rewrite tests in mir form suggested by @arsenm. Thanks !

[0x59616e]

llvm/test/CodeGen/M68k/GlobalISel/legalizer_load_store.ll

1 ↗

(On Diff #399850)

Guess: If you mean IR->assembly test, that needs instruction selector & regbank selector support, which I haven't started to do.

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ping.

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ping

[RKSimon]

llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir

98

pre-commit + rebase this so that the patch some the codegen diff?

[0x59616e]

rebase

[0x59616e]

llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir

98

Thanks for commenting !

Although I did some search on google and mailing list, I still don't know what "pre-commit" should do. I tried to commit this patch on the main branch and no error message happened. Do you mean "git clang-format" or other stuff ?

Apologize for my stupidity.

[0x59616e]

move test file into another patch + rebase

[0x59616e]

llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir

98

I guess what you mean is to separate test file into a "pre-commit test" patch ?

[RKSimon]

I meant rebase this patch on top of D119132 - that way we show the effect of this patch on the test's codegen. So D119132 must pass with current upstream trunk

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Address feedback from @RKSimon. Thanks !

[RKSimon]

LGTM

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Thanks @arsenm @RKSimon !

Since I don't have commit access, could someone commit this on behalf of me ?

[arsenm]

146c7820d9b67eea4577b59d7dce9601d774cf66

[0x59616e]

Thanks again @arsenm @RKSimon ! Really appreciate your help ;)

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
   const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
 
   unsigned TotalSize = ValTy.getSizeInBits();
 
   // Split the load/store into PartTy sized pieces starting at Offset. If this
   // is a load, return the new registers in ValRegs. For a store, each elements
   // of ValRegs should be PartTy. Returns the next offset that needs to be
   // handled.
+  bool isBigEndian = MIRBuilder.getDataLayout().isBigEndian();
   auto MMO = LdStMI.getMMO();
   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
-                             unsigned Offset) -> unsigned {
+                             unsigned NumParts, unsigned Offset) -> unsigned {
     MachineFunction &MF = MIRBuilder.getMF();
     unsigned PartSize = PartTy.getSizeInBits();
     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
-         Offset += PartSize, ++Idx) {
+         ++Idx) {
       unsigned ByteOffset = Offset / 8;
       Register NewAddrReg;
 
       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
 
       MachineMemOperand *NewMMO =
           MF.getMachineMemOperand(&MMO, ByteOffset, PartTy);
 
       if (IsLoad) {
         Register Dst = MRI.createGenericVirtualRegister(PartTy);
         ValRegs.push_back(Dst);
         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
       } else {
         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
       }
+      Offset = isBigEndian ? Offset - PartSize : Offset + PartSize;
     }
 
     return Offset;
   };
 
-  unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
+  unsigned Offset = isBigEndian ? TotalSize - NarrowTy.getSizeInBits() : 0;
+  unsigned HandledOffset =
+      splitTypePieces(NarrowTy, NarrowRegs, NumParts, Offset);
 
   // Handle the rest of the register if this isn't an even type breakdown.
   if (LeftoverTy.isValid())
-    splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
+    splitTypePieces(LeftoverTy, NarrowLeftoverRegs, NumLeftover, HandledOffset);
 
   if (IsLoad) {
     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
                 LeftoverTy, NarrowLeftoverRegs);
   }
 
   LdStMI.eraseFromParent();
   return Legalized;

llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir

body:             |
   bb.1:
     ; CHECK-LABEL: name: test_store_i128
     ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
     ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK-NEXT: G_STORE [[C]](s32), [[LOAD]](p0) :: (store (s32), align 16)
-    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
     ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C4]](s32)
-    ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
+    ; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 12)
     ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
     ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C5]](s32)
-    ; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
-    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
+    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
     ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C6]](s32)
-    ; CHECK-NEXT: G_STORE [[C3]](s32), [[PTR_ADD2]](p0) :: (store (s32) into unknown-address + 12)
+    ; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD2]](p0) :: (store (s32) into unknown-address + 4)
+    ; CHECK-NEXT: G_STORE [[C3]](s32), [[LOAD]](p0) :: (store (s32), align 16)
     ; CHECK-NEXT: RTS
     %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
     %0:_(p0) = G_LOAD %1(p0) :: (load (p0) from %fixed-stack.0, align 8)
     %2:_(s128) = G_CONSTANT i128 316912650112397582603894390785; 0x4000000030000000200000001
     G_STORE %2(s128), %0(p0) :: (store (s128))
     RTS
 
 ...