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Differential D119132

Pre-commit test of D116931
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Authored by 0x59616e on Feb 7 2022, 5:01 AM.

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Reviewers

arsenm
RKSimon

Diff Detail

Unit TestsFailed

	Time	Test
	60,100 ms	x64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp
	60,030 ms	x64 debian > MLIR.Examples/standalone::test.toy
	60,210 ms	x64 debian > lld.COFF::incremental.test

Event Timeline

0x59616e requested review of this revision.Feb 7 2022, 5:01 AM

0x59616e created this revision.

Herald added a project: Restricted Project. · View Herald TranscriptFeb 7 2022, 5:01 AM

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0x59616e set the repository for this revision to rG LLVM Github Monorepo.Feb 7 2022, 5:02 AM

0x59616e added a child revision: D116931: [GlobalISel][Legalizer] Support reducing load/store width in big endian order.

RKSimon mentioned this in D116931: [GlobalISel][Legalizer] Support reducing load/store width in big endian order.Feb 7 2022, 5:04 AM

update diff

LGTM - cheers

This revision is now accepted and ready to land.Feb 7 2022, 6:23 AM

Harbormaster completed remote builds in B147947: Diff 406416.Feb 7 2022, 6:57 AM

Thanks @RKSimon @arsenm !

Since I don't have commit access, could someone commit this on behalf of me ?

In D119132#3302865, @0x59616e wrote:

Thanks @RKSimon @arsenm !

Since I don't have commit access, could someone commit this on behalf of me ?

What's the full committer name/email?

name: Sheng
email: ox59616e@gmail.com

0fe419faa35bbf0e9d4d605aa40c2223be47d1f9

Revision Contents

Path

Size

llvm/

test/

CodeGen/

M68k/

GlobalISel/

legalize-load-store.mir

32 lines

Diff 406416

llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	bb.1 :
%13:_(p0) = G_FRAME_INDEX %fixed-stack.0		%13:_(p0) = G_FRAME_INDEX %fixed-stack.0
%5:_(p0) = G_LOAD %13(p0) :: (load (p0) from %fixed-stack.0)		%5:_(p0) = G_LOAD %13(p0) :: (load (p0) from %fixed-stack.0)
G_STORE %0(s8), %1(p0) :: (store (s8))		G_STORE %0(s8), %1(p0) :: (store (s8))
G_STORE %2(s16), %3(p0) :: (store (s16))		G_STORE %2(s16), %3(p0) :: (store (s16))
G_STORE %4(s32), %5(p0) :: (store (s32))		G_STORE %4(s32), %5(p0) :: (store (s32))
RTS		RTS

...		...
		---
		name: test_store_i128
		fixedStack:
		- { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
		isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
		debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
		body: \|
		bb.1:
		; CHECK-LABEL: name: test_store_i128
		; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
		; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
		; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
		; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
		; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
		; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
		; CHECK-NEXT: G_STORE [[C]](s32), [[LOAD]](p0) :: (store (s32), align 16)
		; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
		; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C4]](s32)
		; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
		; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
		; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C5]](s32)
		; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
		; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
		; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C6]](s32)
		; CHECK-NEXT: G_STORE [[C3]](s32), [[PTR_ADD2]](p0) :: (store (s32) into unknown-address + 12)
		; CHECK-NEXT: RTS
		%1:_(p0) = G_FRAME_INDEX %fixed-stack.0
		%0:_(p0) = G_LOAD %1(p0) :: (load (p0) from %fixed-stack.0, align 8)
		%2:_(s128) = G_CONSTANT i128 316912650112397582603894390785; 0x4000000030000000200000001
		G_STORE %2(s128), %0(p0) :: (store (s128))
		RTS

		...