[GlobalISel] Add big endian support in CallLowering

[0x59616e]

Summary

When splitting values, CallLowering assumes Lo part goes first. But in big endian ISA such as M68k, Hi part goes first.

This patch fixes this.

[0x59616e]

update diff

[0x59616e]

This comment was removed by 0x59616e.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

705–706

Can hoist the TLI query out of the loop

[0x59616e]

update diff according to @arsenm suggestion

[0x59616e]

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

705–706

Done. Thanks :)

[0x59616e]

update diff.

Remove a test in this revision, since that test depends on the InstructionSelector of M68k and I defer that part.

[arsenm]

LGTM

[0x59616e]

Thanks @arsenm for reviewing ! Really appreciate all the help you give ;)

[RKSimon]

@0x59616e reverse ping - what's happening with this patch?

[0x59616e]

In D116877#3304027, @RKSimon wrote:

@0x59616e reverse ping - what's happening with this patch?

I think now it's ok to land this.
Could you help me ?

name: Sheng
email: [e-mail]

[0x59616e]

rebase.

[0x59616e]

Thanks ! Appreciate your help ;)

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

for (unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
 
     // Coerce into outgoing value types before register assignment.
     if (!Handler.isIncomingArgumentHandler() && OrigTy != ValTy) {
       assert(Args[i].OrigRegs.size() == 1);
       buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
                       ValTy, extendOpFromFlags(Args[i].Flags[0]));
     }
 
+    bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
     for (unsigned Part = 0; Part < NumParts; ++Part) {
       Register ArgReg = Args[i].Regs[Part];
       // There should be Regs.size() ArgLocs per argument.
-      VA = ArgLocs[j + Part];
+      unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
+      CCValAssign &VA = ArgLocs[j + Idx];
       const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
 
       if (VA.isMemLoc() && !Flags.isByVal()) {
         // Individual pieces may have been spilled to the stack and others
         // passed in registers.
 
         // TODO: The memory size may be larger than the value we need to
         // store. We may need to adjust the offset for big endian targets.

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

define i64 @test_ret3(i64 %a) {
   ; CHECK-LABEL: name: test_ret3
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
   ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
   ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
   ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
   ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
   ; CHECK:   [[G_UNMERGE_VAL1:%[0-9]+]]:_(s32), [[G_UNMERGE_VAL2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[G_MERGE_VAL]](s64)
-  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL1]](s32)
-  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL2]](s32)
-  ; CHECK:   RTS implicit $d0, implicit $d1
+  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL1]](s32)
+  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL2]](s32)
+  ; CHECK:   RTS implicit $d1, implicit $d0
   ret i64 %a
 }