[RISCV] Select vl op to X0 when it is equal to ~0.

[jacquesguan]

Summary

Now the backend will select ~0 vl to a register and load instruction, we could use X0 to replace it.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1797

I don't think this works on RV32. getZExtValue would return 0xffffffff but VLMaxSentinel is 0xffffffffffffffff. I might be wrong. Please check.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1797

I think getSExtValue would work if I'm correct that the issue exists.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1797

Thanks, you are right, I changed to getSExtValue.

[jacquesguan]

Format code.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
 
   return true;
 }
 
 // Select VL as a 5 bit immediate or a value that will become a register. This
 // allows us to choose betwen VSETIVLI or VSETVLI later.
 bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
   auto *C = dyn_cast<ConstantSDNode>(N);
-  if (C && isUInt<5>(C->getZExtValue()))
+  if (C && (isUInt<5>(C->getZExtValue()) ||
+            C->getSExtValue() == RISCV::VLMaxSentinel))
     VL = CurDAG->getTargetConstant(C->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));
   else
     VL = N;
 
   return true;
 }
 

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

entry:
   %y = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(
     <vscale x 1 x double> %x, double %b, i64 2)
   ret <vscale x 1 x double> %y
 }
 
 define <vscale x 1 x double> @test13(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
 ; CHECK-LABEL: test13:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li a0, -1
-; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
 ; CHECK-NEXT:    vfadd.vv v8, v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
     <vscale x 1 x double> %a,
     <vscale x 1 x double> %b,
     i64 -1)
   ret <vscale x 1 x double> %0