[SDAG] remove FP-to-int cast attribute check in fold to FTRUNC

[spatel]

Summary

We were using a function attribute to indicate a non-standard FP mode, but now we can use intrinsics for that job as shown in the new tests.
Presumably the x86 asm could be improved for that IR with intrinsics, but I have not worked out exactly how to do that. Note that the transform to FTRUNC still requires a hacky check for "nsz" (because FMF are not applied to FP casts).

This is a cleanup based on the clang change in D115804 / 8c7f2a4f87192 .
This is effectively a revert of 5a90285bd98d2 + D46237 .

[RKSimon]

llvm/test/CodeGen/X86/ftrunc.ll

4

Should we have i686 test coverage here ?

[spatel]

llvm/test/CodeGen/X86/ftrunc.ll

4

Sure - are we looking for something particular or just add one i686 + avx RUN as a sanity check?

[pengfei]

llvm/test/CodeGen/X86/ftrunc.ll

559

So we can remove the attributes and all tests used it?

[spatel]

llvm/test/CodeGen/X86/ftrunc.ll

559

Yes, there's no need to test an attribute that does not exist. :)
That should make the diffs a little easier to follow. I could also pre-commit new tests with intrinsics and then delete the old tests if that seems better.

[spatel]

Adjusted tests - we do not need tests for a function attribute that does not exist anymore.

[pengfei]

LGTM.

[RKSimon]

llvm/test/CodeGen/X86/ftrunc.ll

4

i686 + AVX would be fine

[spatel]

Updated test diffs after including a RUN for 32-bit AVX target.

[RKSimon]

LGTM - cheers

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (ExponentIs025 || ExponentIs075) {
     return DAG.getNode(ISD::FMUL, DL, VT, Sqrt, SqrtSqrt);
   }
 
   return SDValue();
 }
 
 static SDValue foldFPToIntToFP(SDNode *N, SelectionDAG &DAG,
                                const TargetLowering &TLI) {
-  // This optimization is guarded by a function attribute because it may produce
-  // unexpected results. Ie, programs may be relying on the platform-specific
-  // undefined behavior when the float-to-int conversion overflows.
-  const Function &F = DAG.getMachineFunction().getFunction();
-  Attribute StrictOverflow = F.getFnAttribute("strict-float-cast-overflow");
-  if (StrictOverflow.getValueAsString().equals("false"))
-    return SDValue();
-
   // We only do this if the target has legal ftrunc. Otherwise, we'd likely be
   // replacing casts with a libcall. We also must be allowed to ignore -0.0
   // because FTRUNC will return -0.0 for (-1.0, -0.0), but using integer
   // conversions would return +0.0.
   // FIXME: We should be able to use node-level FMF here.
   // TODO: If strict math, should we use FABS (+ range check for signed cast)?
   EVT VT = N->getValueType(0);
   if (!TLI.isOperationLegal(ISD::FTRUNC, VT) ||

llvm/test/CodeGen/X86/ftrunc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2    | FileCheck %s --check-prefixes=SSE,SSE2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1  | FileCheck %s --check-prefixes=SSE,SSE41
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx     | FileCheck %s --check-prefixes=AVX1
 
+declare i32 @llvm.fptoui.sat.i32.f32(float)
+declare i64 @llvm.fptosi.sat.i64.f64(double)
+
 define float @trunc_unsigned_f32(float %x) #0 {
 ; SSE2-LABEL: trunc_unsigned_f32:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    cvttss2si %xmm0, %rax
 ; SSE2-NEXT:    movl %eax, %eax
 ; SSE2-NEXT:    xorps %xmm0, %xmm0
 ; SSE2-NEXT:    cvtsi2ss %rax, %xmm0
 ; SSE2-NEXT:    retq

 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vroundpd $11, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
   %i = fptosi <4 x double> %x to <4 x i64>
   %r = sitofp <4 x i64> %i to <4 x double>
   ret <4 x double> %r
 }
 
-; The fold may be guarded to allow existing code to continue
-; working based on its assumptions of float->int overflow.
+; The FTRUNC ("round**" x86 asm) fold relies on UB in the case of overflow.
+; This used to be guarded with an attribute check. That allowed existing
+; code to continue working based on its assumptions that float->int
+; overflow had saturating behavior.
+;
+; Now, we expect a front-end to use IR intrinsics if it wants to avoid this
+; transform.
 
-define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
-; SSE-LABEL: trunc_unsigned_f32_disable_via_attr:
+define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) #0 {
+; SSE-LABEL: trunc_unsigned_f32_disable_via_intrinsic:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    cvttss2si %xmm0, %rax
-; SSE-NEXT:    movl %eax, %eax
+; SSE-NEXT:    xorl %ecx, %ecx
+; SSE-NEXT:    xorps %xmm1, %xmm1
+; SSE-NEXT:    ucomiss %xmm1, %xmm0
+; SSE-NEXT:    cmovael %eax, %ecx
+; SSE-NEXT:    ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT:    movl $-1, %eax
+; SSE-NEXT:    cmovbel %ecx, %eax
 ; SSE-NEXT:    xorps %xmm0, %xmm0
 ; SSE-NEXT:    cvtsi2ss %rax, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
+; AVX1-LABEL: trunc_unsigned_f32_disable_via_intrinsic:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcvttss2si %xmm0, %rax
-; AVX1-NEXT:    movl %eax, %eax
-; AVX1-NEXT:    vcvtsi2ss %rax, %xmm1, %xmm0
+; AVX1-NEXT:    xorl %ecx, %ecx
+; AVX1-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vucomiss %xmm1, %xmm0
+; AVX1-NEXT:    cmovael %eax, %ecx
+; AVX1-NEXT:    vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX1-NEXT:    movl $-1, %eax
+; AVX1-NEXT:    cmovbel %ecx, %eax
+; AVX1-NEXT:    vcvtsi2ss %rax, %xmm2, %xmm0
 ; AVX1-NEXT:    retq
-  %i = fptoui float %x to i32
+  %i = call i32 @llvm.fptoui.sat.i32.f32(float %x)
   %r = uitofp i32 %i to float
   ret float %r
 }
 
-define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
-; SSE-LABEL: trunc_signed_f64_disable_via_attr:
+define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 {
+; SSE-LABEL: trunc_signed_f64_disable_via_intrinsic:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    cvttsd2si %xmm0, %rax
+; SSE-NEXT:    ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; SSE-NEXT:    cmovbeq %rax, %rcx
+; SSE-NEXT:    xorl %eax, %eax
+; SSE-NEXT:    ucomisd %xmm0, %xmm0
+; SSE-NEXT:    cmovnpq %rcx, %rax
 ; SSE-NEXT:    xorps %xmm0, %xmm0
 ; SSE-NEXT:    cvtsi2sd %rax, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX1-LABEL: trunc_signed_f64_disable_via_attr:
+; AVX1-LABEL: trunc_signed_f64_disable_via_intrinsic:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX1-NEXT:    vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; AVX1-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; AVX1-NEXT:    cmovbeq %rax, %rcx
+; AVX1-NEXT:    xorl %eax, %eax
+; AVX1-NEXT:    vucomisd %xmm0, %xmm0
+; AVX1-NEXT:    cmovnpq %rcx, %rax
 ; AVX1-NEXT:    vcvtsi2sd %rax, %xmm1, %xmm0
 ; AVX1-NEXT:    retq
-  %i = fptosi double %x to i64
+  %i = call i64 @llvm.fptosi.sat.i64.f64(double %x)
   %r = sitofp i64 %i to double
   ret double %r
 }
 
 attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
-attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" "strict-float-cast-overflow"="false" }