[M68k][GlobalISel] Implement lowerCall based on M68k calling convention

[0x59616e]

Summary

This patch implements CallLowering::lowerCall based on M68k calling convention and adds M68kOutgoingValueHandler and CallReturnHandler to handle argument passing and returned value.

[myhsu]

Also there is a little problem: GlobalISel reject to combine G_LOAD followed by G_STORE into a move <ea>, <ea> unless there're consecutive in order. That is to say, if there is any instruction between them, GlobalISel will generate weird code like this:

Some of the move <ea>, <ea> definitions are actually missing IIRC. I'm tidying up all the MOVE instructions (to add those missing definitions, for instance) as part of the D115128 series and I think that will solve this problem.

[myhsu]

llvm/lib/Target/M68k/M68kInstrData.td

71

is there any particular reason you made this change? Like, some restrictions imposed by GISel?

[xgupta]

Adding @sushmaunnibhavi (who started GISel support in M68k) as a reviewer in case she still working in this area.

[0x59616e]

llvm/lib/Target/M68k/M68kInstrData.td

71

Yes, GISel rejects the original pattern. It says "Dst operand has an unsupported type"

The SelectionDAG isn't affected. The MatcherTable is still the same after this change.

[0x59616e]

In D115874#3202014, @myhsu wrote:

Also there is a little problem: GlobalISel reject to combine G_LOAD followed by G_STORE into a move <ea>, <ea> unless there're consecutive in order. That is to say, if there is any instruction between them, GlobalISel will generate weird code like this:

Some of the move <ea>, <ea> definitions are actually missing IIRC. I'm tidying up all the MOVE instructions (to add those missing definitions, for instance) as part of the D115128 series and I think that will solve this problem.

I got it. Thanks for your hard work! I won't touch that part until you've done :)

[0x59616e]

update diff.

Since now I've discovered some problems in CallLowering and Legalizer, I want to defer the review of RegisterBankInfo & InstructionSelector. Doing that will also make reviewing simpler

[arsenm]

llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

199

Using F.getCallingConv() is using the calling function's calling convention. You want Info.CallConv like above

215

Ditto

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll

2

Don't need the 2>&1.

Also, probably should just use update_mir_test_checks

38

Value name in declaration list. I'm not sure why even parse this

42

These tests aren't comprehensive enough. You should add a wider variety of return value and outgoing argument types (particularly some pointers and aggregates). Maybe add some byval / sret too.

You're also testing a few different call instruction types which aren't covered (in particular indirect call and the isPositionIndependent switch).

[0x59616e]

Address the issue pointed out by @arsenm. Thanks arsenm !

The following additional tests are included in this revision:

• return value with i32 / i16 / i8 and sret
• outgoing argument with i32 / i16 / i8 / pointer / array / struct
• struct passed byval.
• integer passed byval.
• array passed byval.
• indirect call
• call with pic

[0x59616e]

llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

199

Done. Thanks :)

215

Done. Thanks :)

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll

2

Done. Thanks :)

38

I added it accidentally. It should not have been there. I've removed it. Thanks :)

42

I've added a few more tests. Thanks for reviewing ;)

[arsenm]

llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

199

Same with F.isVarArg

215

Same with F.isVarArg

[0x59616e]

Address feedback from @arsenm. Thanks !

[0x59616e]

llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

199

Done. Thanks !

215

Done. Thanks !

[0x59616e]

Thanks @arsenm @myhsu !

Could someone commit this on behalf of me ?

name: Sheng
email: [e-mail]

[arsenm]

5aa3af3fcb014145ab315090bd3cbea00bea0038

[0x59616e]

Thanks again ! Really appreciate your help ;)

llvm/lib/Target/M68k/GISel/M68kCallLowering.h

 
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/ValueTypes.h"
 
 namespace llvm {
 
 class M68kTargetLowering;
+class MachineInstrBuilder;
 
 class M68kCallLowering : public CallLowering {
   // TODO: We are only supporting return instruction with no value at this time
   // point
 
 public:
   M68kCallLowering(const M68kTargetLowering &TLI);
 
Register getStackAddress(uint64_t Size, int64_t Offset,
                            ISD::ArgFlagsTy Flags) override;
 };
 
 struct FormalArgHandler : public M68kIncomingValueHandler {
   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
       : M68kIncomingValueHandler(MIRBuilder, MRI) {}
 };
 
+struct CallReturnHandler : public M68kIncomingValueHandler {
+  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+                    MachineInstrBuilder &MIB)
+      : M68kIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
+
+private:
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+                        CCValAssign VA) override;
+
+  MachineInstrBuilder &MIB;
+};
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_M68K_GLSEL_M68KCALLLOWERING_H

llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
 
 using namespace llvm;
 
 M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
     : CallLowering(&TLI) {}
 
-struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
-  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler {
+  M68kOutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
                          MachineInstrBuilder MIB)
-      : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
+      : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
+        DL(MIRBuilder.getMF().getDataLayout()),
+        STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {}
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
                         CCValAssign VA) override {
     MIB.addUse(PhysReg, RegState::Implicit);
     Register ExtReg = extendRegister(ValVReg, VA);
     MIRBuilder.buildCopy(PhysReg, ExtReg);
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
                             MachinePointerInfo &MPO, CCValAssign &VA) override {
-    llvm_unreachable("unimplemented");
+    MachineFunction &MF = MIRBuilder.getMF();
+    Register ExtReg = extendRegister(ValVReg, VA);
+
+    auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
+                                        inferAlignFromPtrInfo(MF, MPO));
+    MIRBuilder.buildStore(ExtReg, Addr, *MMO);
   }
 
   Register getStackAddress(uint64_t Size, int64_t Offset,
                            MachinePointerInfo &MPO,
                            ISD::ArgFlagsTy Flags) override {
-    llvm_unreachable("unimplemented");
+    LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
+    LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
+    Register StackReg = STI.getRegisterInfo()->getStackRegister();
+    auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0);
+    auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
+    auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
+    MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
+    return AddrReg.getReg(0);
   }
-
   MachineInstrBuilder MIB;
+  const DataLayout &DL;
+  const M68kSubtarget &STI;
 };
 bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                    const Value *Val, ArrayRef<Register> VRegs,
                                    FunctionLoweringInfo &FLI,
                                    Register SwiftErrorVReg) const {
 
   auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS);
   bool Success = true;
   MachineFunction &MF = MIRBuilder.getMF();
   const Function &F = MF.getFunction();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
   CCAssignFn *AssignFn =
       TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
   auto &DL = F.getParent()->getDataLayout();
   if (!VRegs.empty()) {
     SmallVector<ArgInfo, 8> SplitArgs;
     ArgInfo OrigArg{VRegs, Val->getType(), 0};
     setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
     splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
     OutgoingValueAssigner ArgAssigner(AssignFn);
-    OutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
+    M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
     Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
                                             MIRBuilder, F.getCallingConv(),
                                             F.isVarArg());
   }
   MIRBuilder.insertInstr(MIB);
   return Success;
 }
 
Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
   // Build Frame Index
   llvm::LLT FramePtr = LLT::pointer(
       0, MIRBuilder.getMF().getDataLayout().getPointerSizeInBits());
   MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI);
   StackUsed = std::max(StackUsed, Size + Offset);
   return AddrReg.getReg(0);
 }
 
+void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg,
+                                         CCValAssign VA) {
+  MIB.addDef(PhysReg, RegState::Implicit);
+  MIRBuilder.buildCopy(ValVReg, PhysReg);
+}
+
 bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                                  CallLoweringInfo &Info) const {
+  MachineFunction &MF = MIRBuilder.getMF();
+  Function &F = MF.getFunction();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  auto &DL = F.getParent()->getDataLayout();
+  const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
+  const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
+  const TargetInstrInfo &TII = *STI.getInstrInfo();
+  const M68kRegisterInfo *TRI = STI.getRegisterInfo();
+
+  SmallVector<ArgInfo, 8> OutArgs;
+  for (auto &OrigArg : Info.OrigArgs)
+    splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
+
+  SmallVector<ArgInfo, 8> InArgs;
+  if (!Info.OrigRet.Ty->isVoidTy())
+    splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
+
+  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
+  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
+
+  unsigned Opc = TLI.getTargetMachine().isPositionIndependent() ? M68k::CALLq
+                 : Info.Callee.isReg()                          ? M68k::CALLj
+                                                                : M68k::CALLb;
+
+  auto MIB = MIRBuilder.buildInstrNoInsert(Opc)
+                 .add(Info.Callee)
+                 .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
+
+  CCAssignFn *AssignFn =
+      TLI.getCCAssignFn(F.getCallingConv(), false, F.isVarArg());
+  OutgoingValueAssigner Assigner(AssignFn);
+  M68kOutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
+  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
+                                     Info.CallConv, Info.IsVarArg))
     return false;
+
+  if (Info.Callee.isReg())
+    constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(),
+                             *STI.getRegBankInfo(), *MIB, MIB->getDesc(),
+                             Info.Callee, 0);
+
+  MIRBuilder.insertInstr(MIB);
+
+  if (!Info.OrigRet.Ty->isVoidTy()) {
+    CCAssignFn *RetAssignFn =
+        TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
+
+    OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn);
+    CallReturnHandler Handler(MIRBuilder, MRI, MIB);
+    if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
+                                       Info.CallConv, Info.IsVarArg))
+      return false;
+  }
+
+  CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
+
+  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
+  MIRBuilder.buildInstr(AdjStackUp).addImm(Assigner.StackOffset).addImm(0);
+
+  return true;
 }
 
 bool M68kCallLowering::enableBigEndian() const { return true; }

llvm/lib/Target/M68k/GISel/M68kInstructionSelector.cpp

 //===- M68kInstructionSelector.cpp ------------------------------*- C++ -*-===//
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the InstructionSelector class for
 /// M68k.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "M68kRegisterBankInfo.h"
+#include "M68kRegisterInfo.h"
 #include "M68kSubtarget.h"
 #include "M68kTargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "m68k-isel"
 
 using namespace llvm;
 
 #define GET_GLOBALISEL_PREDICATE_BITSET
 #include "M68kGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATE_BITSET
 
 namespace {
 
 class M68kInstructionSelector : public InstructionSelector {
 public:
   M68kInstructionSelector(const M68kTargetMachine &TM, const M68kSubtarget &STI,
                           const M68kRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
+  // Address Register Indirect
+  ComplexRendererFns selectARI(MachineOperand &Root) const;
+  // Address Register Indirect with PostIncrement
+  ComplexRendererFns selectARIPI(MachineOperand &Root) const;
+  // Address Register Indirect with PreDecrement
+  ComplexRendererFns selectARIPD(MachineOperand &Root) const;
+  // Address Register Indirect with Displacement
+  ComplexRendererFns selectARID(MachineOperand &Root) const;
+  // Address Register Indirect with Index
+  ComplexRendererFns selectARII(MachineOperand &Root) const;
+  // Absolute Long Address Mode
+  ComplexRendererFns selectAL(MachineOperand &Root) const;
+  // Program Counter with Displacement
+  ComplexRendererFns selectPCD(MachineOperand &Root) const;
+  // Program Counter with Index
+  ComplexRendererFns selectPCI(MachineOperand &Root) const;
+
 private:
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool constrainCopy(MachineInstr &I) const;
 
   const M68kTargetMachine &TM;
   const M68kInstrInfo &TII;
   const M68kRegisterInfo &TRI;
   const M68kRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "M68kGenGlobalISel.inc"

 #include "M68kGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_INIT
 #define GET_GLOBALISEL_TEMPORARIES_INIT
 #include "M68kGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectARI(MachineOperand &Root) const {
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectARIPI(MachineOperand &Root) const {
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectARIPD(MachineOperand &Root) const {
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectARID(MachineOperand &Root) const {
+  LLVM_DEBUG(dbgs() << "GISel: Selecting ARID\n");
+
+  MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
+
+  MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+
+  switch (RootDef->getOpcode()) {
+  default:
+    break;
+  case TargetOpcode::G_PTR_ADD: {
+    auto ValAndVReg = getIConstantVRegValWithLookThrough(
+        RootDef->getOperand(2).getReg(), MRI);
+
+    if (!ValAndVReg)
+      break;
+
+    int64_t Imm = ValAndVReg->Value.getSExtValue();
+    Register Reg = RootDef->getOperand(1).getReg();
+
+    return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Imm).addUse(Reg); }}};
+  }
+  case TargetOpcode::G_FRAME_INDEX:
+    return {{[=](MachineInstrBuilder &MIB) {
+      MIB.addImm(0).add(RootDef->getOperand(1));
+    }}};
+  }
+
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectARII(MachineOperand &Root) const {
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectAL(MachineOperand &Root) const {
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectPCD(MachineOperand &Root) const {
+  return None;
+}
+
+InstructionSelector::ComplexRendererFns
+M68kInstructionSelector::selectPCI(MachineOperand &Root) const {
+  return None;
+}
+
+bool M68kInstructionSelector::constrainCopy(MachineInstr &I) const {
+  MachineOperand &Dst = I.getOperand(0);
+  MachineOperand &Src = I.getOperand(1);
+  MachineRegisterInfo &MRI = I.getMF()->getRegInfo();
+
+  if (Dst.getReg().isVirtual() && Src.getReg().isPhysical()) {
+    auto &RegBankOrClass = MRI.getRegClassOrRegBank(Dst.getReg());
+    if (RegBankOrClass.is<const TargetRegisterClass *>())
+      return true;
+
+    LLT Ty = MRI.getType(Dst.getReg());
+    const TargetRegisterClass *TRI = nullptr;
+    if (Ty.getSizeInBits() <= 8) {
+      TRI = &M68k::DR8RegClass;
+    } else if (Ty.getSizeInBits() == 16) {
+      TRI = &M68k::XR16RegClass;
+    } else {
+      TRI = &M68k::XR32RegClass;
+    }
+
+    assert(TRI && "No register class ??");
+    return RBI.constrainGenericRegister(Dst.getReg(), *TRI, MRI) != nullptr;
+  }
+
+  return true;
+}
+
 bool M68kInstructionSelector::select(MachineInstr &I) {
+  if (I.isCopy())
+    return constrainCopy(I);
+
   // Certain non-generic instructions also need some special handling.
   if (!isPreISelGenericOpcode(I.getOpcode()))
     return true;
 
+  // GlobalISel does not support p0 very well.
+  // For example, we need to change:
+  // ```
+  // %0:_(p0) = G_LOAD ...
+  // ```
+  // into this:
+  // ```
+  // %0_(s32) = G_LOAD
+  // ```
+  switch (I.getOpcode()) {
+  case TargetOpcode::G_LOAD: {
+    MachineRegisterInfo &MRI = I.getMF()->getRegInfo();
+
+    Register Reg = I.getOperand(0).getReg();
+    LLT Ty = MRI.getType(Reg);
+    if (Ty.isPointer()) {
+      MRI.setType(Reg, LLT::scalar(32));
+    }
+    break;
+  }
+  }
+
   if (selectImpl(I, *CoverageInfo))
     return true;
 
   return false;
 }
 
 namespace llvm {
 InstructionSelector *
 createM68kInstructionSelector(const M68kTargetMachine &TM,
                               const M68kSubtarget &Subtarget,
                               const M68kRegisterBankInfo &RBI) {
   return new M68kInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.cpp

 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Type.h"
 
 using namespace llvm;
 
 M68kLegalizerInfo::M68kLegalizerInfo(const M68kSubtarget &ST) {
   using namespace TargetOpcode;
-  const LLT S32 = LLT::scalar(32);
-  const LLT P0 = LLT::pointer(0, 32);
-  getActionDefinitionsBuilder(G_LOAD).legalFor({S32});
-  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({P0});
-  getActionDefinitionsBuilder(G_ADD).legalFor({S32});
-  getActionDefinitionsBuilder(G_SUB).legalFor({S32});
-  getActionDefinitionsBuilder(G_MUL).legalFor({S32});
-  getActionDefinitionsBuilder(G_UDIV).legalFor({S32});
+  const LLT s32 = LLT::scalar(32);
+  const LLT p0 = LLT::pointer(0, 32);
+  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_UDIV, G_CONSTANT})
+      .legalFor({s32});
+  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
+
+  getActionDefinitionsBuilder({G_STORE, G_LOAD})
+      .legalForTypesWithMemDesc({{s32, p0, s32, 4}})
+      .legalForTypesWithMemDesc({{p0, p0, s32, 4}});
+
+  getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, s32}});
+
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp

M68kRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
   switch (Opc) {
   case G_ADD:
   case G_SUB:
   case G_MUL:
   case G_SDIV:
   case G_UDIV:
   case G_LOAD:
-  case G_STORE: {
+  case G_STORE:
+  case G_PTR_ADD: {
     OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
     break;
   }
 
   case G_CONSTANT:
   case G_FRAME_INDEX:
     OperandsMapping =
         getOperandsMapping({&M68k::ValueMappings[M68k::GPR3OpsIdx], nullptr});
     break;
   default:
     return getInvalidInstructionMapping();
   }
 
   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
                                NumOperands);
 }

llvm/lib/Target/M68k/M68kInstrData.td

 class MxMove_RR<MxType DST, MxType SRC, MxMoveEncoding ENC>
     : MxMove<DST.Prefix, (outs DST.ROp:$dst), (ins SRC.ROp:$src),
              [(null_frag)], ENC>;
 
 let mayStore = 1 in {
 class MxMove_MR<MxOperand MEMOpd, ComplexPattern MEMPat, MxType REG,
                 MxMoveEncoding ENC>
     : MxMove<REG.Prefix, (outs), (ins MEMOpd:$dst, REG.ROp:$src),
-             [(store REG.VT:$src, MEMPat:$dst)], ENC>;
+             [(store REG.VT:$src, (MEMPat MEMOpd:$dst))], ENC>;
 
 class MxMove_MI<MxOperand MEMOpd, ComplexPattern MEMPat, MxType TYPE,
                 MxMoveEncoding ENC>
     : MxMove<TYPE.Prefix, (outs), (ins MEMOpd:$dst, TYPE.IOp:$src),
-             [(store TYPE.IPat:$src, MEMPat:$dst)], ENC>;
+             [(store TYPE.IPat:$src, (MEMPat MEMOpd:$dst))], ENC>;
 } // let mayStore = 1
 
 class MxMove_RI<MxType DST, MxMoveEncoding ENC>
     : MxMove<DST.Prefix, (outs DST.ROp:$dst), (ins DST.IOp:$src),
               [(set DST.VT:$dst, DST.IPat:$src)], ENC>;
 
 
 let mayLoad = 1 in
 class MxMove_RM<MxType REG, MxOperand MEMOpd, ComplexPattern MEMPat,
                 MxBead2Bits SIZE,
                 MxEncEA SRCEA, MxEncExt SRCEXT,
                 MxEncEA DSTEA, MxEncExt DSTEXT>
     : MxMove<REG.Prefix, (outs REG.ROp:$dst), (ins MEMOpd:$src),
-             [(set REG.VT:$dst, (REG.Load MEMPat:$src))],
+             [(set REG.VT:$dst, (REG.Load (MEMPat MEMOpd:$src)))],
              MxMoveEncoding<SIZE, SRCEA, SRCEXT, DSTEA, DSTEXT>>;
 
 multiclass MMxMove_RM<MxType REG, MxMoveSize SIZE, MxEncEA EA_0> {
 
   // REG <- (An)+
   def NAME#REG.OOp.Letter#REG.Postfix : MxMove_RM<REG, REG.OOp, REG.OPat,
       SIZE, MxEncEAo_1, MxExtEmpty, EA_0, MxExtEmpty>;
 

 let mayLoad = 1, mayStore = 1 in {
 class MxMove_MM<string SIZE, PatFrag LOAD,
                 MxOperand DSTOpd, ComplexPattern DSTPat,
                 MxOperand SRCOpd, ComplexPattern SRCPat,
                 MxBead2Bits ESIZE,
                 MxEncEA SRCEA, MxEncExt SRCEXT,
                 MxEncEA DSTEA, MxEncExt DSTEXT>
     : MxMove<SIZE, (outs), (ins DSTOpd:$dst, SRCOpd:$src),
-             [(store (LOAD SRCPat:$src), DSTPat:$dst)],
+             [(store (LOAD (SRCPat SRCOpd:$src)), (DSTPat DSTOpd:$dst))],
              MxMoveEncoding<ESIZE, SRCEA, SRCEXT, DSTEA, DSTEXT>>;
 } // let mayLoad = 1, mayStore = 1
 
 multiclass MMxMove_MM<MxType TYPE, MxOperand DSTOpd, ComplexPattern DSTPat,
                       MxMoveSize SIZE, MxEncEA EA_0, MxEncExt EXT_0> {
 
   // MEM <- (An)+
   def NAME#TYPE.OOp.Letter#TYPE.Postfix

llvm/lib/Target/M68k/M68kInstrInfo.td

 
 def MxCP_PCD   : ComplexPattern<iPTR, 1, "SelectPCD",
                                 [add, sub, mul, or, shl],
                                 [SDNPWantParent]>;
 
 def MxCP_PCI   : ComplexPattern<iPTR, 2, "SelectPCI",
                                 [add, sub, mul, or, shl], [SDNPWantParent]>;
 
+def gi_MxCP_ARI : GIComplexOperandMatcher<s32, "selectARI">,
+                    GIComplexPatternEquiv<MxCP_ARI>;
+
+def gi_MxCP_ARIPI : GIComplexOperandMatcher<s32, "selectARIPI">,
+                      GIComplexPatternEquiv<MxCP_ARIPI>;
+
+def gi_MxCP_ARIPD : GIComplexOperandMatcher<s32, "selectARIPD">,
+                      GIComplexPatternEquiv<MxCP_ARIPD>;
+
+def gi_MxCP_ARID : GIComplexOperandMatcher<s32, "selectARID">,
+                      GIComplexPatternEquiv<MxCP_ARID>;
+
+def gi_MxCP_ARII : GIComplexOperandMatcher<s32, "selectARII">,
+                      GIComplexPatternEquiv<MxCP_ARII>;
+
+def gi_MxCP_AL : GIComplexOperandMatcher<s32, "selectAL">,
+                      GIComplexPatternEquiv<MxCP_AL>;
+
+def gi_MxCP_PCD : GIComplexOperandMatcher<s32, "selectPCD">,
+                      GIComplexPatternEquiv<MxCP_PCD>;
+
+def gi_MxCP_PCI : GIComplexOperandMatcher<s32, "selectPCI">,
+                      GIComplexPatternEquiv<MxCP_PCI>;
 
 //===----------------------------------------------------------------------===//
 // Pattern Fragments
 //===----------------------------------------------------------------------===//
 
 def MximmSExt8  : PatLeaf<(i8  imm)>;
 def MximmSExt16 : PatLeaf<(i16 imm)>;
 def MximmSExt32 : PatLeaf<(i32 imm)>;

 def Mxloadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
   if (ExtType == ISD::EXTLOAD)
     return LD->getAlignment() >= 2 && !LD->isSimple();
   return false;
-}]>;
+}]> {
+  let GISelPredicateCode = [{
+    return (*MI.memoperands_begin())->getSize() == 2;
+  }];
+}
 
 def Mxloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
   if (ExtType == ISD::EXTLOAD)
     return LD->getAlignment() >= 4 && !LD->isSimple();
   return false;
-}]>;
+}]> {
+  let GISelPredicateCode = [{
+    return (*MI.memoperands_begin())->getSize() == 4;
+  }];
+}
 
 def Mxloadi8         : PatFrag<(ops node:$ptr), (i8  (load node:$ptr))>;
 
 def MxSExtLoadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
 def MxSExtLoadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
 def MxSExtLoadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
 
 def MxZExtLoadi8i1   : PatFrag<(ops node:$ptr), (i8  (zextloadi1 node:$ptr))>;

llvm/lib/Target/M68k/M68kTargetMachine.cpp

 #include "M68kTargetMachine.h"
 #include "M68k.h"
 #include "M68kSubtarget.h"
 #include "M68kTargetObjectFile.h"
 #include "TargetInfo/M68kTargetInfo.h"
 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
+#include "llvm/CodeGen/GlobalISel/Localizer.h"
 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/PassRegistry.h"
 #include <memory>
public:
   }
 
   const M68kSubtarget &getM68kSubtarget() const {
     return *getM68kTargetMachine().getSubtargetImpl();
   }
   bool addIRTranslator() override;
   bool addLegalizeMachineIR() override;
   bool addRegBankSelect() override;
+  void addPreGlobalInstructionSelect() override;
   bool addGlobalInstructionSelect() override;
   bool addInstSelector() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
 };
 } // namespace
 
 TargetPassConfig *M68kTargetMachine::createPassConfig(PassManagerBase &PM) {
bool M68kPassConfig::addLegalizeMachineIR() {
   return false;
 }
 
 bool M68kPassConfig::addRegBankSelect() {
   addPass(new RegBankSelect());
   return false;
 }
 
+void M68kPassConfig::addPreGlobalInstructionSelect() {
+  addPass(new Localizer());
+}
+
 bool M68kPassConfig::addGlobalInstructionSelect() {
   addPass(new InstructionSelect());
   return false;
 }
 
 void M68kPassConfig::addPreSched2() { addPass(createM68kExpandPseudoPass()); }
 
 void M68kPassConfig::addPreEmitPass() {
   addPass(createM68kCollapseMOVEMPass());
 }

llvm/test/CodeGen/M68k/GlobalISel/c-call.ll

+; RUN: llc -mtriple=m68k -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+
+define i32 @test1() nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       ; %bb.0
+; CHECK-NEXT:  suba.l  #4, %sp
+; CHECK-NEXT:  jsr     callee1
+; CHECK-NEXT:  move.l  #0, %d0
+; CHECK-NEXT:  adda.l  #4, %sp
+; CHECK-NEXT:  rts
+  call void @callee1() nounwind
+  ret i32 0
+}
+declare void @callee1();
+
+define i32 @test2() nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:  suba.l  #12, %sp
+; CHECK-NEXT:  move.l  #12, (0,%sp)
+; CHECK-NEXT:  move.l  #18, (4,%sp)
+; CHECK-NEXT:  move.l  #-4, (8,%sp)
+; CHECK-NEXT:  jsr     callee2
+; CHECK-NEXT:  move.l  #0, %d0
+; CHECK-NEXT:  adda.l  #12, %sp
+; CHECK-NEXT:  rts
+  call void @callee2(i32 12, i32 18, i32 -4) nounwind
+  ret i32 0
+}
+declare void @callee2(i32, i32, i32);
+
+define i32 @test3(i32 %0, i32 %1) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:  suba.l  #12, %sp
+; CHECK-NEXT:  move.l  (16,%sp), %d0
+; CHECK-NEXT:  move.l  (20,%sp), %d1
+; CHECK-NEXT:  move.l  %d0, (0,%sp)
+; CHECK-NEXT:  move.l  %d1, (4,%sp)
+; CHECK-NEXT:  jsr     callee3
+; CHECK-NEXT:  adda.l  #12, %sp
+; CHECK-NEXT:  rts
+  %3 = call i32 @callee3(i32 %0, i32 %1)
+  ret i32 %3
+}
+declare i32 @callee3(i32, i32)
 No newline at end of file

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll

+; RUN: llc -mtriple=m68k -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+; CHECK-LABEL: name: test_trivial_call
+; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit-def $ccr, implicit $sp
+; CHECK: CALLb @trivial_callee, csr_std, implicit $sp
+; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit-def $ccr, implicit $sp
+; CHECK: RTS
+declare void @trivial_callee()
+define void @test_trivial_call() {
+  call void @trivial_callee()
+  ret void
+}
+
+; CHECK-LABEL: name: test_simple_return
+; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit-def $ccr, implicit $sp
+; CHECK: CALLb @simple_return_callee, csr_std, implicit $sp, implicit-def $d0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = COPY $d0
+; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit-def $ccr, implicit $sp
+; CHECK $d0 = COPY [[RES]]
+; CHECK RTS implicit $d0
+declare i32 @simple_return_callee()
+define i32 @test_simple_return() {
+  %res = call i32 @simple_return_callee()
+  ret i32 %res
+}
+
+; CHECK-LABEL: name: test_simple_arg
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = G_CONSTANT i32 1048596
+; CHECK: ADJCALLSTACKDOWN 4, 0, implicit-def $sp, implicit-def $ccr, implicit $sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
+; CHECK: [[OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFFSET]](s32)
+; CHECK: G_STORE [[ARG]](s32), [[PTR]](p0)
+; CHECK: CALLb @simple_arg_callee, csr_std, implicit $sp
+; CHECK: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit-def $ccr, implicit $sp
+; CHECK: RTS
+declare void @simple_arg_callee(i32 %0)
+define void @test_simple_arg() {
+  call void @simple_arg_callee(i32 1048596)
+  ret void
+}