[RISCV] Fix whole vector register move instruction's vector register constraint.

[jacquesguan]

Summary

According to the v-spec, the source and destination VR of vmv<nr>r.v should be aligned for the VR group size.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 
 // Vector Compress Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
     RVVConstraint = NoConstraint in {
-foreach n = [1, 2, 4, 8] in {
-  def VMV#n#R_V  : RVInstV<0b100111, !add(n, -1), OPIVI, (outs VR:$vd),
-                           (ins VR:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
+def VMV1R_V  : RVInstV<0b100111, 0, OPIVI, (outs VR:$vd), (ins VR:$vs2),
+                       "vmv1r.v", "$vd, $vs2">, VMVRSched<1> {
+  let Uses = [];
+  let vm = 1;
+}
+// A future extension may relax the vector register alignment restrictions.
+foreach n = [2, 4, 8] in {
+  defvar vrc = !cast<VReg>("VRM"#n);
+  def VMV#n#R_V  : RVInstV<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd),
+                           (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
                    VMVRSched<n> {
     let Uses = [];
     let vm = 1;
   }
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtZvlsseg] in {
   foreach nf=2-8 in {
     foreach eew = [8, 16, 32, 64] in {
       defvar w = !cast<RISCVWidth>("LSWidth"#eew);

llvm/test/MC/RISCV/rvv/invalid.s

 # CHECK-ERROR: invalid operand for instruction
 
 vs8r.v v6, (a0)
 # CHECK-ERROR: invalid operand for instruction
 
 vs8r.v v7, (a0)
 # CHECK-ERROR: invalid operand for instruction
 
+vmv2r.v v1, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv2r.v v0, v1
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v1, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v2, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v3, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v0, v1
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v0, v2
+# CHECK-ERROR: invalid operand for instruction
+
+vmv4r.v v0, v3
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v1, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v2, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v3, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v4, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v5, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v6, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v7, v0
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v1
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v2
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v3
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v4
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v5
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v6
+# CHECK-ERROR: invalid operand for instruction
+
+vmv8r.v v0, v7
+# CHECK-ERROR: invalid operand for instruction
+
 vmsge.vx v2, v4, a0, v0.t, v0
 # CHECK-ERROR: invalid operand for instruction
 
 vmsgeu.vx v2, v4, a0, v0.t, v0
 # CHECK-ERROR: invalid operand for instruction
 
 vmsge.vx v2, v4, a0, v0.t, v2
 # CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
 
 vmsgeu.vx v2, v4, a0, v0.t, v2
 # CHECK-ERROR: The temporary vector register cannot be the same as the destination register.